Samsung S6B0728 Datasheet

S6B0728

permission of LCD Driver IC Team.

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

Jan. 2000.

Ver. 0.1

Prepared by: Goohyung, Chung

Kuku81@samsung.co.kr

S6B0728 Specification Revision History

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

Version Content Date

0.0 Original Sep.1999

0.1 Change the supply voltage(VDD) range (2.4 to 5.5 -> 2.4 to 3.6) Jan.2000

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

NTENTS

INTRODUCTION ..................................................................................................................................................1

BLOCK DIAGRAM...............................................................................................................................................2

PAD CONFIGURATION .......................................................................................................................................3

PAD CENTER COORDINATES ............................................................................................................................4

PIN DESCRIPTION ..............................................................................................................................................6

FUNCTIONAL DESCRIPTION............................................................................................................................ 10

MICROPROCESSOR INTERFACE.............................................................................................................10

DISPLAY DATA RAM (DDRAM)..................................................................................................................14

LCD DISPLAY CIRCUITS............................................................................................................................17

LCD DRIVER CIRCUIT ...............................................................................................................................19

POWER SUPPLY CIRCUITS ......................................................................................................................21

REFERENCE CIRCUIT EXAMPLES ...........................................................................................................26

RESET CIRCUIT.........................................................................................................................................28

INSTRUCTION DESCRIPTION...........................................................................................................................29

SPECIFICATIONS..............................................................................................................................................48

ABSOLUTE MAXIMUM RATINGS...............................................................................................................48

DC CHARACTERISTICS .............................................................................................................................49

AC CHARACTERISTICS............................................................................................................................. 52

REFERENCE APPLICATIONS........................................................................................................................... 56

MICROPROCESSOR INTERFACE.............................................................................................................56

CONNECTIONS BETWEEN S6B0728 AND LCD PANEL............................................................................ 57

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B0728 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It contains 128 common and 132 segment driver circuits. It is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data RAM of 128 x 132 bits. It provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external-operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.

FEATURES

Driver Output Circuits

− 128 common outputs / 132 segment outputs

Applicable Duty-ratios

Programmable duty ratio Applicable LCD bias Maximum display area

1/16 to 1/128 1/5 to 1/12

− Various partial display

− Partial window moving & data scrolling

On-chip Display Data RAM

128 × 132

− Capacity: 128 x 132 = 16,896 bits

− Bit data "1": a dot of display is illuminated

− Bit data "0": a dot of display is not illuminated

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− Serial interface(only write operation) with 4-pin or 3-pin SPI(Serial Peripheral Interface)

On-chip Low Power Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x3, x4, x5, x6 or x7)

− Voltage regulator (temperature coefficient: -0.05%/°C or external input)

− On-chip electronic contrast control function (64 steps)

− Voltage follower (LCD bias: 1/5 to 1/12)

Operating Voltage Range

− Supply voltage (VDD): 2.4 to 3.6 [V]

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 17.0 [V]

Low Power Consumption

− TBD µΑ Typ. (VDD = 3V, x6 boosting, V0 = 15V, Internal power supply ON and display OFF)

− TBD µΑ Max. (during power save [standby] mode )

Package Type

− Gold bumped chip or TCP

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

DB0

DB1

COM127

COM

BLOCK DIAGRAM

SEG131

SEG130

VDD

V0 V1 V2 V3 V4

VSS

SEG2

SEG1

SEG0

132 SEGMENT

DRIVER CIRCUITS

SEG129

COM

128 COMMON

DRIVER CIRCUITS

126

INTRS

VEXT

REF

VOUT

C1-

C1+

C2C2+ C3+ C4+ C5+ C6+

VCI

V/F

CIRCUIT

V/R

RCIRCUIT

V/C

CIRCUIT

PAGE

ADDRESS

CIRCUIT

SEGMENT CONTROLLER

DISPLAY DATA RAM

128 X 132 = 16,896 Bits

COLUMN ADDRESS

CIRCUIT

INSTRUCTION DECODER & REGISTER

MPU INTERFACE (PARALLEL & SERIAL)

COMMON CONTROLLER

LINE

ADDRESS

CIRCUIT

STATUS REGISTERBUS HOLDER

TIMING

GENERATOR

CIRCUIT

OSCILLATOR

DB2

DB3

DB4

DB5

DB6(SCLK)

DB7(SID)

RW_WR

E_RD

CS2

CS1B

C68

RESETB

Figure 1. Block Diagram

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

161

312

160

313

127

346

126

ðððð

- - - -

ðððð

- - - -

ðððð

PAD CONFIGURATION

рр ррррррррррррррррррр

- - - - - - - - - -

S6B0728

(TOP VIEW)

(0,0) X

ррррррррррррррррррр

ðð

рррррррррррррррррррррр

- - - - - - - - - -

ррррррррррррррррррррррр

Figure 2. S6B0728 Chip Configuration

Table 1. S6B0728 Pad Dimensions

Size

Item Pad No.

X Y

Chip size - 8740 2470

27 to 100 70 (Min.)

Pad pitch

1 to 26, 101 to 346 54 (Min.)

27 to 100 60 78

128 to 159, 314 to 345 78 44

Bumped pad size

3 to 26, 101 to 124

163 to 310

1, 2, 125, 126,

160, 161, 313, 346

44 78

70 78

127, 162, 311, 312 78 70

Bumped pad

height

1 to 346 14 (Typ.)

Unit

µm

30 um

30 um 30 um

(-3810, -705)

*1 : Bump Align Key

30 um

42 um

(-3920, 825)

*2 : ILB Align Key 1

108 um

42 um

108 um

*3 : ILB Align Key 2

42 um

(3870, 783)

108 um

42 um

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y NO NAME X Y

1 DUMMY -4161 -1110 51 DB6 -875 -1110 101 COM63 2759 -1110 151 COM16 4245 405 2 DUMMY -4081 -1110 52 DB7 -805 -1110 102 COM62 2813 -1110 152 COM15 4245 459 3 COM104 -4001 -1110 53 VDD -735 -1110 103 COM61 2867 -1110 153 COM14 4245 513 4 COM105 -3947 -1110 54 VDD -665 -1110 104 COM60 2921 -1110 154 COM13 4245 567 5 COM106 -3893 -1110 55 VDD -595 -1110 105 COM59 2975 -1110 155 COM12 4245 621 6 COM107 -3839 -1110 56 VDD -525 -1110 106 COM58 3029 -1110 156 COM11 4245 675 7 COM108 -3785 -1110 57 VCI -455 -1110 107 COM57 3083 -1110 157 COM10 4245 729 8 COM109 -3731 -1110 58 VCI -385 -1110 108 COM56 3137 -1110 158 COM9 4245 783

9 COM110 -3677 -1110 59 VSS -315 -1110 109 COM55 3191 -1110 159 COM8 4245 837 10 COM111 -3623 -1110 60 VSS -245 -1110 110 COM54 3245 -1110 160 DUMMY 4245 917 11 COM112 -3569 -1110 61 VSS -175 -1110 111 COM53 3299 -1110 161 DUMMY 4129 1110 12 COM113 -3515 -1110 62 VSS -105 -1110 112 COM52 3353 -1110 162 DUMMY 4049 1110 13 COM114 -3461 -1110 63 VOUT -35 -1110 113 COM51 3407 -1110 163 COM7 3969 1110 14 COM115 -3407 -1110 64 VOUT 35 -1110 114 COM50 3461 -1110 164 COM6 3915 1110 15 COM116 -3353 -1110 65 C5+ 105 -1110 115 COM49 3515 -1110 165 COM5 3861 1110 16 COM117 -3299 -1110 66 C5+ 175 -1110 116 COM48 3569 -1110 166 COM4 3807 1110 17 COM118 -3245 -1110 67 C3+ 245 -1110 117 COM47 3623 -1110 167 COM3 3753 1110 18 COM119 -3191 -1110 68 C3+ 315 -1110 118 COM46 3677 -1110 168 COM2 3699 1110 19 COM120 -3137 -1110 69 C1- 385 -1110 119 COM45 3731 -1110 169 COM1 3645 1110 20 COM121 -3083 -1110 70 C1- 455 -1110 120 COM44 3785 -1110 170 COM0 3591 1110 21 COM122 -3029 -1110 71 C1+ 525 -1110 121 COM43 3839 -1110 171 SEG0 3537 1110 22 COM123 -2975 -1110 72 C1+ 595 -1110 122 COM42 3893 -1110 172 SEG1 3483 1110 23 COM124 -2921 -1110 73 C2+ 665 -1110 123 COM41 3947 -1110 173 SEG2 3429 1110 24 COM125 -2867 -1110 74 C2+ 735 -1110 124 COM40 4001 -1110 174 SEG3 3375 1110 25 COM126 -2813 -1110 75 C2- 805 -1110 125 DUMMY 4081 -1110 175 SEG4 3321 1110 26 COM127 -2759 -1110 76 C2- 875 -1110 126 DUMMY 4161 -1110 176 SEG5 3267 1110 27 TEST1 -2555 -1110 77 C4+ 945 -1110 127 DUMMY 4245 -917 177 SEG6 3213 1110 28 TEST2 -2485 -1110 78 C4+ 1015 -1110 128 COM39 4245 -837 178 SEG7 3159 1110 29 TEST3 -2415 -1110 79 C6+ 1085 -1110 129 COM38 4245 -783 179 SEG8 3105 1110 30 CL -2345 -1110 80 C6+ 1155 -1110 130 COM37 4245 -729 180 SEG9 3051 1110 31 M -2275 -1110 81 VSS 1225 -1110 131 COM36 4245 -675 181 SEG10 2997 1110 32 VDD -2205 -1110 82 VSS 1295 -1110 132 COM35 4245 -621 182 SEG11 2943 1110 33 PS -2135 -1110 83 V4 1365 -1110 133 COM34 4245 -567 183 SEG12 2889 1110 34 C68 -2065 -1110 84 V4 1435 -1110 134 COM33 4245 -513 184 SEG13 2835 1110 35 VSS -1995 -1110 85 V3 1505 -1110 135 COM32 4245 -459 185 SEG14 2781 1110 36 CS1B -1925 -1110 86 V3 1575 -1110 136 COM31 4245 -405 186 SEG15 2727 1110 37 CS2 -1855 -1110 87 V2 1645 -1110 137 COM30 4245 -351 187 SEG16 2673 1110 38 VDD -1785 -1110 88 V2 1715 -1110 138 COM29 4245 -297 188 SEG17 2619 1110 39 RESETB -1715 -1110 89 V1 1785 -1110 139 COM28 4245 -243 189 SEG18 2565 1110 40 RS -1645 -1110 90 V1 1855 -1110 140 COM27 4245 -189 190 SEG19 2511 1110 41 VSS -1575 -1110 91 V0 1925 -1110 141 COM26 4245 -135 191 SEG20 2457 1110 42 RW_WR -1505 -1110 92 V0 1995 -1110 142 COM25 4245 -81 192 SEG21 2403 1110 43 E_RD -1435 -1110 93 VR 2065 -1110 143 COM24 4245 -27 193 SEG22 2349 1110 44 VDD -1365 -1110 94 VR 2135 -1110 144 COM23 4245 27 194 SEG23 2295 1110 45 DB0 -1295 -1110 95 VSS 2205 -1110 145 COM22 4245 81 195 SEG24 2241 1110 46 DB1 -1225 -1110 96 REF 2275 -1110 146 COM21 4245 135 196 SEG25 2187 1110 47 DB2 -1155 -1110 97 VEXT 2345 -1110 147 COM20 4245 189 197 SEG26 2133 1110 48 DB3 -1085 -1110 98 VDD 2415 -1110 148 COM19 4245 243 198 SEG27 2079 1110 49 DB4 -1015 -1110 99 INTRS 2485 -1110 149 COM18 4245 297 199 SEG28 2025 1110 50 DB5 -945 -1110 100 VSS 2555 -1110 150 COM17 4245 351 200 SEG29 1971 1110

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y

201 SEG30 1917 1110 251 SEG80 -783 1110 301 SEG130 -3483 1110 202 SEG31 1863 1110 252 SEG81 -837 1110 302 SEG131 -3537 1110 203 SEG32 1809 1110 253 SEG82 -891 1110 303 COM64 -3591 1110 204 SEG33 1755 1110 254 SEG83 -945 1110 304 COM65 -3645 1110 205 SEG34 1701 1110 255 SEG84 -999 1110 305 COM66 -3699 1110 206 SEG35 1647 1110 256 SEG85 -1053 1110 306 COM67 -3753 1110 207 SEG36 1593 1110 257 SEG86 -1107 1110 307 COM68 -3807 1110 208 SEG37 1539 1110 258 SEG87 -1161 1110 308 COM69 -3861 1110 209 SEG38 1485 1110 259 SEG88 -1215 1110 309 COM70 -3915 1110 210 SEG39 1431 1110 260 SEG89 -1269 1110 310 COM71 -3969 1110 211 SEG40 1377 1110 261 SEG90 -1323 1110 311 DUMMY -4049 1110 212 SEG41 1323 1110 262 SEG91 -1377 1110 312 DUMMY -4129 1110 213 SEG42 1269 1110 263 SEG92 -1431 1110 313 DUMMY -4245 917 214 SEG43 1215 1110 264 SEG93 -1485 1110 314 COM72 -4245 837 215 SEG44 1161 1110 265 SEG94 -1539 1110 315 COM73 -4245 783 216 SEG45 1107 1110 266 SEG95 -1593 1110 316 COM74 -4245 729 217 SEG46 1053 1110 267 SEG96 -1647 1110 317 COM75 -4245 675 218 SEG47 999 1110 268 SEG97 -1701 1110 318 COM76 -4245 621 219 SEG48 945 1110 269 SEG98 -1755 1110 319 COM77 -4245 567 220 SEG49 891 1110 270 SEG99 -1809 1110 320 COM78 -4245 513 221 SEG50 837 1110 271 SEG100 -1863 1110 321 COM79 -4245 459 222 SEG51 783 1110 272 SEG101 -1917 1110 322 COM80 -4245 405 223 SEG52 729 1110 273 SEG102 -1971 1110 323 COM81 -4245 351 224 SEG53 675 1110 274 SEG103 -2025 1110 324 COM82 -4245 297 225 SEG54 621 1110 275 SEG104 -2079 1110 325 COM83 -4245 243 226 SEG55 567 1110 276 SEG105 -2133 1110 326 COM84 -4245 189 227 SEG56 513 1110 277 SEG106 -2187 1110 327 COM85 -4245 135 228 SEG57 459 1110 278 SEG107 -2241 1110 328 COM86 -4245 81 229 SEG58 405 1110 279 SEG108 -2295 1110 329 COM87 -4245 27 230 SEG59 351 1110 280 SEG109 -2349 1110 330 COM88 -4245 -27 231 SEG60 297 1110 281 SEG110 -2403 1110 331 COM89 -4245 -81 232 SEG61 243 1110 282 SEG111 -2457 1110 332 COM90 -4245 -135 233 SEG62 189 1110 283 SEG112 -2511 1110 333 COM91 -4245 -189 234 SEG63 135 1110 284 SEG113 -2565 1110 334 COM92 -4245 -243 235 SEG64 81 1110 285 SEG114 -2619 1110 335 COM93 -4245 -297 236 SEG65 27 1110 286 SEG115 -2673 1110 336 COM94 -4245 -351 237 SEG66 -27 1110 287 SEG116 -2727 1110 337 COM95 -4245 -405 238 SEG67 -81 1110 288 SEG117 -2781 1110 338 COM96 -4245 -459 239 SEG68 -135 1110 289 SEG118 -2835 1110 339 COM97 -4245 -513 240 SEG69 -189 1110 290 SEG119 -2889 1110 340 COM98 -4245 -567 241 SEG70 -243 1110 291 SEG120 -2943 1110 341 COM99 -4245 -621 242 SEG71 -297 1110 292 SEG121 -2997 1110 342 COM100 -4245 -675 243 SEG72 -351 1110 293 SEG122 -3051 1110 343 COM101 -4245 -729 244 SEG73 -405 1110 294 SEG123 -3105 1110 344 COM102 -4245 -783 245 SEG74 -459 1110 295 SEG124 -3159 1110 345 COM103 -4245 -837 246 SEG75 -513 1110 296 SEG125 -3213 1110 346 DUMMY -4245 -917 247 SEG76 -567 1110 297 SEG126 -3267 1110 248 SEG77 -621 1110 298 SEG127 -3321 1110 249 SEG78 -675 1110 299 SEG128 -3375 1110 250 SEG79 -729 1110 300 SEG129 -3429 1110

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

PIN DESCRIPTION

Table 3. Power Supply Pins

Name I/O Description

VDD Supply Power supply

Vss Supply Ground

LCD drivers supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier

V0 V1 V2 V3 V4

I/O

for application. Voltages should have the following relationship: V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ Vss When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias.

LCD bias V1 V2 V3 V4

1/N bias (N-1)/N x V0 (N-2)/N x V0 2/N x V0 1/N x V0

NOTE : *N = 5 to 12

Table 4. LCD Driver Supply Pins

Name I/O Description

C1-, C2- I/O Capacitor negative connection pins used for voltage converter

C1+, C2+ C3+, C4+ C5+, C6+

VOUT I/O

VCI I Voltage converter input voltage pin for internal booster.

VR I V0 voltage adjustment pin used to adjust V0 by means of external resistors(INTRS = “ L” )

REF I

VEXT I

INTRS I

I/O Capacitor positive connection pins used for voltage converter

Voltage converter input/output pin. VOUT = Boost level × VCI, for internal booster

Selects the external VREF voltage via VEXT pin

− REF = "L": using the external VREF

− REF = "H": using the internal VREF

Externally-input reference voltage(VREF) for the internal voltage regulator. It is valid only when REF is “L”.

Internal resistors select pin used to select resistors for adjusting V0 voltage level.

− INTRS = "H”: use the internal resistors.

− INTRS = "L”: use the external resistors. VR pin and external resistive divider control V0

voltage.

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Table 5. Microprocessor Interface Pins

Name I/O Description

RESETB I

PS I

C68 I

CS1B

CS2

RS I

RW_WR I

Reset input pin. When RESETB is “L”, initialization is executed.

Parallel / Serial data input select input

PS Interface

mode

H Parallel RS DB0 to DB7

Data /

instruction

Data Read / Write Serial clock

E_RD

RW_WR

L Serial RS SID (DB7) Write only SCLK (DB6)

*NOTE: When PS is “L”, DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.

Microprocessor interface(PS = “H”) / Register Select(PS = “L”) input pin

PS C68 Interface mode

H 6800-series MPU mode

L 8080-series MPU mode

H 4-Pin SPI MPU mode

L 3-Pin SPI MPU mode

Chip select input pins Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is

non-active, DB0 to DB7 may be high impedance. Register select input pin

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

C68 MPU Type RW_WR Description

Read/Write control input pin

H 6800-series RW

− RW = “H”: read

− RW = “L”: write

Write enable clock input pin

L 8080-series /WR

The data on DB0 to DB7 are latched at the rising edge of the /WR signal.

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

Table 5. Microprocessor Interface Pins (Continued)

Name I/O Description

Read / Write execution control pin

C68 MPU type E_RD Description

Read / Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 are in an

E_RD I

H 6800-series E

output status.

− RW = “L”: The data on DB0 to DB7 are latched at the falling edge of the E signal.

L 8080-series /RD

Read enable clock input pin When /RD is “L”, DB0 to DB7 are in an output status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus.

DB0

DB7

I/O

When the serial interface selected (PS = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID).

When chip select is not active, DB0 to DB7 may be high impedance.

Table 6. Test Pins

Name I/O Description

TEST1

TEST3

Test pins

Don’ t use these pins.

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Table 7. LCD driver output pins

Name I/O Description

LCD segment driver outputs The display data and the M signal control the output voltage of segment driver.

SEG0

SEG131

COM0

COM127

Display data M

Segment driver output voltage

Normal display Reverse display

H H V0 V2

H L Vss V3

L H V2 V0 L L V3 Vss

Power save mode Vss Vss

LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver.

Scan data M Common driver output voltage

H H Vss

H L V0

L H V1 L L V4

Power save mode Vss

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for chip selection. The S6B0728 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.

Parallel / Serial Interface

The S6B0728 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 8.

Table 8. Parallel / Serial Interface Mode.

PS Type CS1B CS2 C68 Interface mode

H Parallel CS1B CS2

L Serial CS1B CS2

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in

Table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in Table 10.

Table 9. Microprocessor Selection for Parallel Interface

C68 CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus

H CS1B CS2 RS E RW DB0 to DB7 6800-series

L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series

Table 10. Parallel Data Transfer

Common 6800-series 8080-series

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

H 6800-series MPU mode

L 8080-series MPU mode

H 4-Pin SPI MPU mode

L 3-Pin SPI MPU mode

Description

H H H L H Read display data H H L H L Write display data

L H H L H Read out internal status register L H L H L Write instruction data

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Serial Interface (PS = "L")

Communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when PS is low. When using the serial interface, read operations are not allowed. . When the chip select inputs are valid(CS1B = “L” & CS2 = “H”), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and processed as 8-bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. And not valid, the internal 8-bit shift register and the 3-bit counter are reset. The serial interface type is selected by setting C68 as shown in Table 11.

Table 11. Microprocessor Selection for Serial Interface

C68 Serial interface mode Chip Select Register Select Serial Data / Clock input

H 4-Pin SPI CS1B, CS2 by RS pin DB7 / DB6

L 3-Pin SPI CS1B, CS2 by software DB7 / DB6

4-Pin SPI Interface (PS = "L", C68 = "H")

In 4-pin SPI interface mode, RS pin is used for indicating whether serial data input is display or instruction data. Data is display data when RS is high and instruction data when RS is low.

CS1B

CS2

SID

SCLK

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. 4-Pin SPI Timing (RS is used)

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

3-Pin SPI Interface (PS = "L" , C68 = "L")

In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length, is used to indicate whether serial data input is display or instruction data instead of RS pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists two bytes instruction. The first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes(1 to 256) are to be transmitted. The next byte after the display data string is handled as instruction data. For details, refers the Figure 4.

Chip Select

24 12321 16

CS1B = L, CS2 = H

2 15 1 2 8079

Serial clock

3 bytes 10 bytes2 bytes

Serial data

10110001 00010000 00001000 11111100 00001001

Page = 1 Column address = 16 DDL DDL = 9 User's display data

10 bytes display data

Internal RS

Figure 4. 3 Pin SPI Timing (RS is not used)

*NOTES:

- In spite of transmission of data, if CS1B will be disable, state terminates abnormally. Next state is initialized.

- The number of writing display data = DDL register value + 1

Busy Flag

The Busy Flag indicates whether the S6B0728 is operating or not. When DB7 is “H” in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

DB0 to DB7

BUS HOLDER

D(N)

D(N+1)

D(N+2)

N+1

N+2

N+3

Data Transfer

The S6B0728 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.

MPU signals

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

MPU signals

/WR

/RD

Internal signals

/WR

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 5. Write Timing

Dummy D(N) D(N+1)

/RD

COLUMN ADDRESS

Figure 6. Read Timing

132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0728

- -

001

- -

011

- -

101

- -

000

- -

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 128-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 128 rows are divided into 16 pages of 8 lines. Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.

DB0 DB1 DB2 DB3 DB4

1 0 0 - - 1

COM0

COM1 COM2 COM3 COM4

- -

Display Data RAM LCD Display

Figure 7. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a page address to Display Data RAM shown in figure 8. It incorporates 4-bit page address register changed by only the “Set Page” instruction.

Line Address Circuit

This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 7. It incorporates 7-bit line address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by internal latch signal and generates the Line Address for transferring the 132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.

S6B0728 PRELIMINARY SPEC. VER. 0.1 132 SEG / 128 COM DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column Address circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not incremented and locked if a non-existing address above 83H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is independent of page address register.

ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7.

SEG Output

SEG

... ...

SEG

128

SEG

129

SEG

130

SEG

131

Column address [Y7:Y0] 00H 01H 02H 03H ... ... 80H 81H 82H 83H

Display data 1 0 1 0 1 1 0 0

LCD panel display

... ...

( ADC = 0 )

LCD panel display

( ADC = 1 )

... ...

Figure 8. The Relationship between the Column Address and The Segment Outputs

Segment Control Circuit

This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.

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