Samsung S6B0721X01-B0CY, S6B0721X01-B0CZ, S6B0721X01-xxX0, S6B0721X01-xxXN, S6B0721X11-B0CY Datasheet
...
S6B0721
written permission of LCD Driver IC Team.
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
June.2000.
Ver. 0.1
Prepared by: Jae-Su, Ko
Ko1942@samsung.co.kr
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
S6B0721 Specification Revision History
Version Content Date
0.0 Initial version Nov.1999
0.1 Read timing is changed (Figure 5) Jun.2000
2
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
CO
NTENTS
INTRODUCTION ..................................................................................................................................................1
FEATURES..........................................................................................................................................................1
BLOCK DIAGRAM...............................................................................................................................................3
PAD CONFIGURATION .......................................................................................................................................4
PAD CENTER COORDINATES ............................................................................................................................5
PIN DESCRIPTION ..............................................................................................................................................7
POWER SUPPLY ..........................................................................................................................................7
LCD DRIVER SUPPLY..................................................................................................................................7
SYSTEM CONTROL .....................................................................................................................................8
MICROPROCESSOR INTERFACE.............................................................................................................10
LCD DRIVER OUTPUTS.............................................................................................................................12
FUNCTIONAL DESCRIPTION............................................................................................................................ 13
MICROPROCESSOR INTERFACE.............................................................................................................13
DISPLAY DATA RAM (DDRAM)..................................................................................................................17
LCD DISPLAY CIRCUITS............................................................................................................................20
LCD DRIVER CIRCUIT ...............................................................................................................................22
POWER SUPPLY CIRCUITS ...................................................................................................................... 23
REFERECE CIRCUIT EXAMPLES..............................................................................................................30
RESET CIRCUIT.........................................................................................................................................32
INSTRUCTION DESCRIPTION...........................................................................................................................33
SPECIFICATIONS..............................................................................................................................................47
ABSOLUTE MAXIMUM RATINGS...............................................................................................................47
DC CHARACTERISTICS .............................................................................................................................48
REFERENCE DATA....................................................................................................................................51
AC CHARACTERISTICS.............................................................................................................................53
REFERENCE APPLICATIONS........................................................................................................................... 57
MICROPROCESSOR INTERFACE.............................................................................................................57
CONNECTIONS BETWEEN S6B0721 AND LCD PANEL............................................................................58
TCP PIN LAYOUT (SAMPLE)......................................................................................................................63
3
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0721 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65
commons and 132 segments driver circuits. This chip is connected directly to a microprocessor, accepts serial or
8-bit parallel display data and stores in an on-chip Display Data RAM of 65 x 132 bits. It provides a high-flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no externally operating clock to minimize power
consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible
to make a display system with the fewest components.
FEATURES
Driver Output Circuits
− 65 common outputs / 132 segment outputs
On-chip Display Data RAM
− Capacity: 65 x 132 = 8,580 bits
Applicable Duty Ratios
Duty ratio Applicable LCD bias Maximum display area
1/65 1/7 or 1/9
1/49 1/6 or 1/8
1/33 1/5 or 1/6
Microprocessor Interface
− 8-bit parallel bi-directional interface with 6800-series or 8080-series
− Serial interface (only write operation) available
Function Set
− Various instructions sets
− H/W, S/W reset capable
Built-in Analog Circuit
− On-chip oscillator circuit
− Voltage converter (x2, x3, x4, x5)
− Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)
− Voltage follower
− Electronic contrast control function (64 steps)
Operating Voltage Range
− Supply voltage (VDD): 2.4 to 3.6 V
− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
Low Power Consumption
65 × 132
49 × 132
33 × 132
− 70 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 11V, internal power supply ON)
− 10 µΑ Max. (during power save [standby] mode)
Package Type
− Gold bump chip or TCP
1
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
Series Specifications
Product code Internal TEMPS Temp. coefficient Package Chip thickness
S6B0721X01-B0CZ
S6B0721X01-B0CY
S6B0721X11-B0CZ
S6B0721X11-B0CY
S6B0721X01-xxX0
S6B0721X01-xxXN
S6B0721X11-xxX0
S6B0721X11-xxXN
* XX: TCP ordering number
0
(VSS connected)
1
(VDD connected)
0
(VSS connected)
1
(VDD connected)
-0.05%/°C
670 µm
470 µm
COG
670 µm
-0.2%/°C
470 µm
670 µm
-0.05%/°C
470 µm
TCP
670 µm
-0.2%/°C
470 µm
2
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
VSS
DB0
DB1
COMS
COM64
BLOCK DIAGRAM
SEG132
SEG131
VDD
V0
V1
V2
V3
V4
COMS
COM1
:
33 COMMON
DRIVER
CIRCUITS
COM32
SEG1
SEG3
SEG2
132 SEGMENT
DRIVER CIRCUITS
SEG130
:
:
COM33
:
33 COMMON
DRIVER
CIRCUITS
HPM
V0
VR
INTRS
VOUT
C1-
C1+
C2-
C2+
C3-
C3+
DCDC5B
V / F
CIRCUIT
V / R
CIRCUIT
V / C
CIRCUIT
PAGE
ADDRESS
CIRCUIT
SEGMENT CONTROLLER
I/O
BUFFER
DISPLAY DATA RAM
65 X 132 = 8,580 Bits
COLUMN ADDRESS
CIRCUIT
STATUS REGISTER INSTRUCTION REGISTER
COMMON CONTROLLER
LINE
ADDRESS
CIRCUIT
INSTRUCTION DECODERBUS HOLDER
DISPLAY
TIMING
GENERATOR
CIRCUIT
OSCILLATOR
MS
CL
M
FRS
DISP
DUTY0
DUTY1
CLS
MPU INTERFACE (PARALLEL & SERIAL)
DB5
DB6(SCLK)
DB7(SID)
MI
RESETB
PS
RW_WR
E_RD
RS
CS2
CS1B
Figure 1. Block Diagram
DB4
DB3
DB2
3
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
138
283
137
284
109
312
108
1
ð
ðððð
- - - -
ðððð
ð
ð
ðððð
- - - -
ðððð
ð
(-4094, -565)
30
µ
m
30
µ
m
30
µ
m
60µm
30µm
42µm
108µm
42
µ
m
108
µ
m
(-4161, +473)
(+4161, -597)
PAD CONFIGURATION
р рр ррррррррррррррррррр
- - - - - - - - - -
Y
ррррррррррррррррррр
S6B0721
(TOP VIEW)
р рррррррррррррррррр
Figure 2. S6B0721 Chip Configuration
Table 1. S6B0721 Pad Dimensions
Items Pad No.
Chip size - 9640 2020
1,108,109,137,138,283,
Pad pitch
110 to 136, 139 to 282
Bumped pad size
(Top size)
109,137,284,312 110 60
110 to 136,285 to 311 110 45
(0,0)
- - - - - - - - - -
284,312
2 to 107 70
285 to 311
1,108 70 100
2 to 107 50 100
X
рррррррррррррррррр
X Y
Size
90
60
ðð
ð
ð
Unit
µm
139 to 282 45 110
138,283 60 110
Bumped pad height 1 to 312 14(Typ.)
COG Align Key Coordinate ILB Align Key Coordinate
30µm 30µm 30µm
(+4089, +312)
4
30µm 30µm 30µm
42µm 108µm
42µm108µm
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Pad
Pad
Pad
Pad
Pad
Pad
No
Name
No
Name
No
Name
1
DUMMY
-3765
-89555VDD35-895
109
DUMMY
4673
-8502FRS
-3675
-89556VOUT
105
-895
110
COMS
4673
-7803M
-3605
-89557VOUT
175
-895
111
COM1
4673
-7204CL
-3535
-89558VOUT
245
-895
112
COM2
4673
-6605DISP
-3465
-89559VOUT
315
-895
113
COM3
4673
-6006VSS
-3395
-89560C3+
385
-895
114
COM4
4673
-5407CS1B
-3325
-89561C3+
455
-895
115
COM5
4673
-4808CS2
-3255
-89562C3+
525
-895
116
COM6
4673
-4209VDD
-3185
-89563C3+
595
-895
117
COM7
4673
-36010RESETB
-3115
-89564C3-
665
-895
118
COM8
4673
-30011RS
-3045
-89565C3-
735
-895
119
COM9
4673
-24012VSS
-2975
-89566C3-
805
-895
120
COM10
4673
-18013RW_WR
-2905
-89567C3-
875
-895
121
COM11
4673
-12014E_RD
-2835
-89568C1+
945
-895
122
COM12
4673
-6015VDD
-2765
-89569C1+
1015
-895
123
COM13
4673016
DB0
-2695
-89570C1+
1085
-895
124
COM14
46736017
DB1
-2625
-89571C1+
1155
-895
125
COM15
4673
12018DB2
-2555
-89572C1-
1225
-895
126
COM16
4673
18019DB3
-2485
-89573C1-
1295
-895
127
COM17
4673
24020DB4
-2415
-89574C1-
1365
-895
128
COM18
4673
30021DB5
-2345
-89575C1-
1435
-895
129
COM19
4673
36022DB6
-2275
-89576C2+
1505
-895
130
COM20
4673
42023DB7
-2205
-89577C2+
1575
-895
131
COM21
4673
48024VSS
-2135
-89578C2+
1645
-895
132
COM22
4673
54025DUMMY
-2065
-89579C2+
1715
-895
133
COM23
4673
60026DUMMY
-1995
-89580C2-
1785
-895
134
COM24
4673
66027VDD
-1925
-89581C2-
1855
-895
135
COM25
4673
72028DUTY0
-1855
-89582C2-
1925
-895
136
COM26
4673
78029DUTY1
-1785
-89583C2-
1995
-895
137
DUMMY
4673
85030VSS
-1715
-89584VSS
2065
-895
138
DUMMY
4380
86331MS
-1645
-89585VSS
2135
-895
139
COM27
4290
86332CLS
-1575
-89586VR
2205
-895
140
COM28
4230
86333VDD
-1505
-89587VR
2275
-895
141
COM29
4170
86334MI
-1435
-89588V0
2345
-895
142
COM30
4110
86335PS
-1365
-89589V0
2415
-895
143
COM31
4050
86336VSS
-1295
-89590V1
2485
-895
144
COM32
3990
86337VSS
-1225
-89591V1
2555
-895
145
SEG1
3930
86338VSS
-1155
-89592V2
2625
-895
146
SEG2
3870
86339VSS
-1085
-89593V2
2695
-895
147
SEG3
3810
86340VSS
-1015
-89594V3
2765
-895
148
SEG4
3750
86341VSS
-945
-89595V3
2835
-895
149
SEG5
3690
86342VSS
-875
-89596V4
2905
-895
150
SEG6
3630
86343VSS
-805
-89597V4
2975
-895
151
SEG7
3570
86344VSS
-735
-89598VSS
3045
-895
152
SEG8
3510
86345VSS
-665
-89599VSS
3115
-895
153
SEG9
3450
86346VDD
-595
-895
100
DUMMY
3185
-895
154
SEG10
3390
86347VDD
-525
-895
101
DCDC5B
3255
-895
155
SEG11
3330
86348VDD
-455
-895
102
VDD
3325
-895
156
SEG12
3270
86349VDD
-385
-895
103
HPM
3395
-895
157
SEG13
3210
86350VDD
-315
-895
104
INTRS
3465
-895
158
SEG14
3150
86351VDD
-245
-895
105
VSS
3535
-895
159
SEG15
3090
86352VDD
-175
-895
106
DUMMY
3605
-895
160
SEG16
3030
86353VDD
-105
-895
107
VDD
3675
-895
161
SEG17
2970
86354VDD
-35
-895
108
TESTCK
3765
-895
162
SEG18
2910
863
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
X Y X Y
X
Y
5
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
Pad
Pad
Pad
Pad
Pad
Pad
No
Name
No
Name
No
Name
163
SEG19
2850
863
217
SEG73
-390
863
271
SEG127
-3630
863
164
SEG20
2790
863
218
SEG74
-450
863
272
SEG128
-3690
863
165
SEG21
2730
863
219
SEG75
-510
863
273
SEG129
-3750
863
166
SEG22
2670
863
220
SEG76
-570
863
274
SEG130
-3810
863
167
SEG23
2610
863
221
SEG77
-630
863
275
SEG131
-3870
863
168
SEG24
2550
863
222
SEG78
-690
863
276
SEG132
-3930
863
169
SEG25
2490
863
223
SEG79
-750
863
277
COMS
-3990
863
170
SEG26
2430
863
224
SEG80
-810
863
278
COM64
-4050
863
171
SEG27
2370
863
225
SEG81
-870
863
279
COM63
-4110
863
172
SEG28
2310
863
226
SEG82
-930
863
280
COM62
-4170
863
173
SEG29
2250
863
227
SEG83
-990
863
281
COM61
-4230
863
174
SEG30
2190
863
228
SEG84
-1050
863
282
COM60
-4290
863
175
SEG31
2130
863
229
SEG85
-1110
863
283
DUMMY
-4380
863
176
SEG32
2070
863
230
SEG86
-1170
863
284
DUMMY
-4673
850
177
SEG33
2010
863
231
SEG87
-1230
863
285
COM59
-4673
780
178
SEG34
1950
863
232
SEG88
-1290
863
286
COM58
-4673
720
179
SEG35
1890
863
233
SEG89
-1350
863
287
COM57
-4673
660
180
SEG36
1830
863
234
SEG90
-1410
863
288
COM56
-4673
600
181
SEG37
1770
863
235
SEG91
-1470
863
289
COM55
-4673
540
182
SEG38
1710
863
236
SEG92
-1530
863
290
COM54
-4673
480
183
SEG39
1650
863
237
SEG93
-1590
863
291
COM53
-4673
420
184
SEG40
1590
863
238
SEG94
-1650
863
292
COM52
-4673
360
185
SEG41
1530
863
239
SEG95
-1710
863
293
COM51
-4673
300
186
SEG42
1470
863
240
SEG96
-1770
863
294
COM50
-4673
240
187
SEG43
1410
863
241
SEG97
-1830
863
295
COM49
-4673
180
188
SEG44
1350
863
242
SEG98
-1890
863
296
COM48
-4673
120
189
SEG45
1290
863
243
SEG99
-1950
863
297
COM47
-467360190
SEG46
1230
863
244
SEG100
-2010
863
298
COM46
-46730191
SEG47
1170
863
245
SEG101
-2070
863
299
COM45
-4673
-60
192
SEG48
1110
863
246
SEG102
-2130
863
300
COM44
-4673
-120
193
SEG49
1050
863
247
SEG103
-2190
863
301
COM43
-4673
-180
194
SEG50
990
863
248
SEG104
-2250
863
302
COM42
-4673
-240
195
SEG51
930
863
249
SEG105
-2310
863
303
COM41
-4673
-300
196
SEG52
870
863
250
SEG106
-2370
863
304
COM40
-4673
-360
197
SEG53
810
863
251
SEG107
-2430
863
305
COM39
-4673
-420
198
SEG54
750
863
252
SEG108
-2490
863
306
COM38
-4673
-480
199
SEG55
690
863
253
SEG109
-2550
863
307
COM37
-4673
-540
200
SEG56
630
863
254
SEG110
-2610
863
308
COM36
-4673
-600
201
SEG57
570
863
255
SEG111
-2670
863
309
COM35
-4673
-660
202
SEG58
510
863
256
SEG112
-2730
863
310
COM34
-4673
-720
203
SEG59
450
863
257
SEG113
-2790
863
311
COM33
-4673
-780
204
SEG60
390
863
258
SEG114
-2850
863
312
DUMMY
-4673
-850
205
SEG61
330
863
259
SEG115
-2910
863
206
SEG62
270
863
260
SEG116
-2970
863
207
SEG63
210
863
261
SEG117
-3030
863
208
SEG64
150
863
262
SEG118
-3090
863
209
SEG65
90
863
263
SEG119
-3150
863
210
SEG66
30
863
264
SEG120
-3210
863
211
SEG67
-30
863
265
SEG121
-3270
863
212
SEG68
-90
863
266
SEG122
-3330
863
213
SEG69
-150
863
267
SEG123
-3390
863
214
SEG70
-210
863
268
SEG124
-3450
863
215
SEG71
-270
863
269
SEG125
-3510
863
216
SEG72
-330
863
270
SEG126
-3570
863
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
X YX Y X Y
6
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pin Description
Name I/O Description
VDD Supply Power supply
VSS Supply Ground
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
V0
V1
V2
V3
V4
I/O
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.
LCD bias V1 V2 V3 V4
1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0
1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0
1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pin Description
Name I/O Description
C1- O Capacitor 1 negative connection pin for voltage converter
C1+ O Capacitor 1 positive connection pin for voltage converter
C2- O Capacitor 2 negative connection pin for voltage converter
C2+ O Capacitor 2 positive connection pin for voltage converter
C3- O Capacitor 3 negative connection pin for voltage converter
C3+ O Capacitor 3 positive connection pin for voltage converter
VOUT I/O Voltage converter input / output pin
5 times boosting circuit enable input pin
DCDC5B I
VR I
When this pin is low in 4 times boosting circuit, the 5-times boosting voltage appears at
VOUT.
V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = “L”).
7
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
SYSTEM CONTROL
Table 5. System Control Pin Description
Name I/O Description
Master / Slave operation select pin
− MS = "H": master operation
− MS = "L": slave operation
The following table depends on the MS status.
MS I
CLS I
CL I/O
M I/O
FRS O
DISP I/O
INTRS I
HPM I
MS CLS
H Enabled Enabled Output Output Output Output
H
L Disabled Enabled Input Output Output Output
L - Disabled Disabled Input Input Output Input
Built-in oscillator circuit enable / disable select pin
− CLS = “H”: enable
− CLS = “L”: disable (external display clock input to CL pin)
Display clock input / output pin
When the S6B0721 is used in master/slave mode (multi-chip), the CL pins must be
connected each other.
LCD AC signal input / output pin
When the S6B0721 is used in master/slave mode (multi-chip), the M pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
Static driver segment output pin
This pin is used together with the M pin.
LCD display blanking control input / output
When S6B0721 is used in master/slave mode (multi-chip), the DISP pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.
− INTRS = "H": use the internal resistors.
− INTRS = "L": use the external resistors.
V0 voltage is controlled with VR pin and external resistive divider.
Power control pin of the power supply circuit for LCD driver
− HPM = "H": high power mode
− HPM = "L": normal mode
This pin is valid in master operation.
OSC
circuit
Power
supply
circuit
CL M FRS DISP
8
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Table 5. System Control Pin Description (Continued)
Name I/O Description
The LCD driver duty ratio depends on the following table
DUTY1 DUTY0 Duty ratio
DUTY0
DUTY1
I
L L 1/33
L H 1/49
H L/H 1/65
9
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pin Description
Name I/O Description
RESETB I
PS I
MI I
CS1B
CS2
RS I
RW_WR I
Reset input pin
When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
PS
H Parallel
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to
DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.
Microprocessor interface selects input pin
− MI = "H": 6800-series MPU interface
− MI = "L": 8080-series MPU interface
Chip select input pins
I
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.
Register select input pin
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
MI MPU type RW_WR Description
H 6800-series RW
Interface
mode
L Serial
L 8080-series /WR
Chip
select
CS1B,
CS2
CS1B,
CS2
Data /
instruction
RS DB0 to DB7
RS SID(DB7) Write only SCLK(DB6)
Read / Write control input pin
− RW = “H”: read
− RW = “L”: write
Write enable clock input pin
The data ON DB0 to DB7 are latched at the rising
edge of the /WR signal.
Data Read / Write Serial clock
E_RD
RW_WR
-
10
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Table 6. Microprocessor Interface Pin Description (Continued)
Name I/O Description
Read / Write execution control pin
MI MPU type E_RD Description
Read / Write control input pin
− RW = “H”: When E is “H”, DB0 to DB7 are in an
E_RD I
H 6800-series E
output status.
− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.
DB0
to
DB7
I/O
L 8080-series /RD
Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
11
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
LCD DRIVER OUTPUTS
Table 7. LCD Driver Outputs Pin Description
Name I/O Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG1
to
SEG132
COM1
to
COM64
COMS O
Display data M
H H V0 V2
O
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
O
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open.
In multi-chip (master / slave) mode, all COMS pins on both master and slave units are the
same signal.
H L VSS V3
L H V2 V0
L L V3 VSS
Power save mode VSS VSS
Scan data M Common driver output voltage
H H VSS
H L V0
L H V1
L L V4
Power save mode VSS
Segment driver output voltage
Normal display Reverse display
NOTE: DUMMY - These pins should be opened (floated).
12
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for Chip Selection. The S6B0721 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the
counter are reset.
Parallel / Serial Interface
S6B0721 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel
or serial interface is determined by PS pin as shown in table 8.
Table 8. Parallel / Serial Interface Mode
PS Type CS1B CS2 MI Interface mode
H Parallel CS1B CS2
L Serial CS1B CS2
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in
table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10.
Table 9. Microprocessor Selection for Parallel Interface
MI CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus
H CS1B CS2 RS E RW DB0 to DB7 6800-series
L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series
Table 10. Parallel Data Transfer
Common 6800-series 8080-series
RS
E_RD
(E)
RW_WR
(RW)
E_RD
(/RD)
RW_WR
(/WR)
H 6800-series MPU mode
L 8080-series MPU mode
*×
Description
Serial-mode
*× : Don't care
H H H L H Display data read out
H H L H L Display data write
L H H L H Register status read
L H L H L Writes to internal register (instruction)
13
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
Serial Interface (PS = "L")
When the S6B0721 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the
internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock
going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data
when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the
external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
SCLK
RS
DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the S6B0721 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
14
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Data Transfer
The S6B0721 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure
5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
N D(N) D(N+1) D(N+2) D(N+3)
N D(N) D(N+1) D(N+2) D(N+3)
N N+1 N+2 N+3
Figure 4. Write Timing
15
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
N
D(N)
D(N+1)
D(N+2)
N
N+1
N+2
N+3
MPU signals
RS
/WRB
/RDB
DB0 to DB7
Internal signals
/WRB
/RDB
BUS HOLDER
COLUMN ADDRESS
N
Dummy D(N) D(N+1)
Figure 5. Read Timing
D(N+2)
16
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8
lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in Figure 6. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
DB0 0 0 1 - - 0
DB1 1 0 0 - - 1
DB2 0 1 1 - - 0
DB3 1 0 1 - - 0
DB4 0 0 0 - - 1
COM1 - -
COM2 - COM3 - COM4 - COM5 - -
Display Data RAM LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it
is impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM1) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the
MPU can not access Line Address of icons.
17
Loading...