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S6B0717
55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
January.2000
Ver. 1.0
Prepared by: Yong-Jin, Jeon
Yjjeon@samsung.co.kr
Contents in this document are subject to change without notice. No part
55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0717
S6B0717 Specification Revision History
Version Content Date
0.0 Apr.1999
1.0
Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V
Jan.2000
2
S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
FEATURES ......................................................................................................................................................... 1
PAD CONFIGURATION....................................................................................................................................... 4
PAD CENTER COORDINATES........................................................................................................................... 5
POWER SUPPLY......................................................................................................................................... 7
CONNECTIONS BETWEEN S6B0717 AND LCD PANEL............................................................................58
3
S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0717 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 55 common
and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel
display data and stores in an on-chip display data RAM of 65 x 100 bits. It provides a high-flexible display section
due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display
data RAM read/write operation with no external operating clock to minimize power consumption. In addition,
because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system
with the fewest components.
FEATURES
Driver Output Circuits
− 55 common outputs / 100 segment outputs
On-chip Display Data RAM
− Capacity: 65 x 100 = 6,500 bits
− Bit data "1": a dot of display is illuminated.
− Bit data "0": a dot of display is not illuminated.
Multi-chip Operation (Master, Slave) Available
Applicable Duty Ratios
Duty ratio Applicable LCD bias Maximum display area
1/55 1/8 or 1/6
1/34 1/6 or 1/5
Microprocessor Interface
− 8-bit parallel bi-directional interface with 6800-series or 8080-series
− Serial interface (only write operation) available
On-Chip Low Power Analog Circuit
− On-chip oscillator circuit
− Voltage converter (x2, x3, x4, x5)
− Voltage regulator (temperature coefficient: -0.05%/°C or external input)
− Voltage follower (LCD bias: 1/5, 1/6 or 1/8)
− Electronic contrast control function (64 steps)
Operating Voltage Range
− Supply voltage (VDD): 2.4 to 3.6 V
− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pins Description
Name I/O Description
VDD Supply Power supply
VSS Supply Ground
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.
LCD bias V1 V2 V3 V4
1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
V0
V1
V2
V3
V4
I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pins Description
Name I/O Description
C1- O Capacitor 1 negative connection pin for voltage converter
C1+ O Capacitor 1 positive connection pin for voltage converter
C2- O Capacitor 2 negative connection pin for voltage converter
C2+ O Capacitor 2 positive connection pin for voltage converter
C3- O Capacitor 3 negative connection pin for voltage converter
C3+ O Capacitor 3 positive connection pin for voltage converter
VOUT I/O Voltage converter input / output pin
DCDC5B
VR I
VEXT I External VREF input pin for the LCD power supply voltage regulator
REF I
5 times boosting circuit enable input pin. When this pin is low in 4 times boosting circuit,
I
the 5 times boosting voltage appears at VOUT
V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = “L”)
Selects the external VREF voltage via the VEXT pin
− REF = "H": using the internal VREF
− REF = "L": using the external VREF
7
55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0717
When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
PS
Interface
mode
H Parallel
L Serial
Chip
select
CS1B,
CS2
CS1B,
CS2
Data /
instruction
RS DB0 to DB7
Data Read / Write Serial clock
E_RD
RW_WR
RS SID (DB7) Write only SCLK (DB6)
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to
DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.
Microprocessor interface select input pin
− C68 = "H": 6800-series MPU interface
− C68 = "L": 8080-series MPU interface
Chip select input pins
I
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip
select is non-active, DB0 to DB7 may be high impedance.
Register select input pin
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
C68 MPU type RW_WR Description
Read/Write control input pin
H 6800-series
I
RW
− RW = “H”: read
− RW = “L”: write
Write enable clock input pin
L 8080-series
/WR
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
-
10
S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.
DB0
DB7
to
I/O
L 8080-series
/RD
Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
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55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0717
LCD DRIVER OUTPUTS
Table 9. LCD Driver Outputs Pins Description
Name I/O Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG0
to
SEG99
COM0
to
COM53
COMS O
O
O
Display data M
Segment driver output voltage
Normal display Reverse display
H H V0 V2
H L VSSV3
L H V2 V0
L L V3 VSS
Power save mode VSSVSS
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
Scan data M Common driver output voltage
H H VSS
H L V0
L H V1
L L V4
Power save mode VSS
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open. In
multi-chip (master / slave) mode, all COMS pins on both master and slave units are the
same signal.
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S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for chip selection. The S6B0717 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and
DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are
reset.
Parallel / Serial Interface
S6B0717 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 10.
Table 10. Parallel / Serial Interface Mode
PS Type CS1B CS2 C68 Interface mode
H Parallel CS1B CS2
L Serial CS1B CS2
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in Parallel Interface and the type of MPU is selected by C68 as shown in
table 11. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 12.
Table 11. Microprocessor Selection for Parallel Interface
C68 CS1B CS2 RS E_RD RW_WR
H CS1B CS2 RS E RW DB0 to DB7 6800-series
L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series
Table 12. Parallel Data Transfer
Common
RS
H H H L H Display data read out
H H L H L Display data write
L H H L H Register status read
L H L H L Writes to internal register (instruction)
6800-series 8080-series
E_RD
(E)
RW_WR
(RW)
E_RD
(/RD)
RW_WR
(/WR)
H 6800-series MPU mode
L 8080-series MPU mode
*×
DB0 to DB7 MPU bus
Description
Serial-mode
*×: Don't care
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55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0717
Serial Interface (PS = "L")
When the S6B0717 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high
and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by
the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
SCLK
RS
DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the S6B0717 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
14
S6B0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Data Transfer
The S6B0717 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.
This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
ND(N)D(N+1)D(N+2)D(N+3)
ND(N)D(N+1)D(N+2)D(N+3)
NN+1N+2N+3
Figure 4. Write Timing
15
55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0717
N
D(N)
D(N+1)
D(N+2)
N
N+1
N+2
N+3
MPU signals
RS
/WR
/RD
DB0 to DB7
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
DummyD(N)D(N+1)
Figure 5. Read Timing
16
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