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S6A009064 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0090 Specification Revision History
VersionContentDate
0.0OriginalJun.1998
0.1KS0090 à KS0090B, add ILB keyApr.1999
0.2Add power ON / OFF sequenceApr.1999
InspectionJun.2000
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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
PAD CONFIGURATION ...................................................................................................................................... 4
PAD CENTER COORDINATES ........................................................................................................................... 5
POWER SUPPLY ..........................................................................................................................................7
FUNCTION DESCRIPTION ............................................................................................................................... 10
SYSTEM INTERFACE.................................................................................................................................10
DC CHARACTERISTICS .............................................................................................................................44
AC CHARACTERISTICS.............................................................................................................................47
3
64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
INTRODUCTION
The S6A0090 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can
display 2 or 3 lines of 12 characters with 5 x 8 dots format. It is capable of interfacing with various
microprocessors, supporting the 4-bit and 8-bit parallel mode and the clock synchronized serial mode. Voltage
converter (2 or 3 times), voltage regulator, divider resistor and voltage follower OP AMP are built in the IC and a
low operation current of 50µA is achieved. The slim shape of the chip makes it suitable for the COG module
application and TCP. The S6A0090 is an ideal solution for display on portable equipment such as cellular phones.
* NOTE: The COMS1 has two terminals (#101, #110), and these two COMS1 are the same signal at the same time
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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
NameI/ODescription
VDD
VSS
V0
V1
V2
V3
V4
Power
I/O
LCD DRIVER SUPPLY
NameI/ODescription
CAP1+O
CAP1-O
CAP2+O
CAP2–O
VOUTI/O
VRI
Power supply
Connect to MPU power supply pin
0V (GND)
Bias voltage level for LCD driving
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the built-in power circuit is on, the following voltages are given to pins V1
to V4 by internal 1/5 bias resistors are used.
LCD biasV1V2V3V4
(1/5) bias(4/5) x V0(3/5) x V0(2/5) x V0(1/5) x V0
Table 3. Pin Description (continued)
Capacitor 1+ connecting pin for the internal voltage converter
This pin connects the capacitor with CAP1-.
Capacitor1- connecting pin for the internal voltage converter
This pin connects the capacitor with CAP1+.
Capacitor 2+ connecting pin for the internal voltage converter
When VOUT is 2 times boosting, this pin connects the capacitor with VDD,
when 3 times boosting, this pin connects the capacitor with CAP2Capacitor2- connecting pin for the internal voltage converter
When VOUT is 2 times boosting, this pin is not used, when 3 times boosting,
this pin connects the capacitor with CAP2+
2 or 3 times DC/DC voltage converter output
This pin connects a capacitor with VDD pin.
Voltage adjust pin
This pin gives a voltage between V0 and VSS by resistance-division of voltage.
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S6A009064 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL
Table 3. Pin Description (continued)
NameI/ODescription
External clock input pin
CKI
PSI
IFI
BIDI
It must be fixed to "High" when the internal oscillation circuit is used.
In the external clock mode, it is used as external clock input pin.
Parallel / serial selection pin
When PS = "Low": serial mode
When PS = "High": 4-bit/8-bit bus mode
Interface data length selection pin for parallel data input
When PS = "Low"
IF = "Low " or "High": serial interface mode
When PS = “High”
IF = "Low": 4-bit bus mode
IF = "High": 8-bit bus mode
SEG direction selection pin
When BID = "Low";
Initialization is performed by edge sensing of the RES signal.
An interface type for the 68/80 series MPU is selected by input level after
initialization.
When RES = "Low": 68 series MPU
When RES = "High": 80 series MPU
Chip selection pin
When CSB = "Low": selected
When CSB = "High": not selected
Register selection pin
When RS = "Low": instruction register
When RS = "High": data register
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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
Table 3. Pin Description (Continued)
NameI/ODescription
In 80 series MPU interface mode, active "Low".
This pin connects the WR pin of the 80 series MPU.
EI
DB0 to DB3
DB4 to DB5
DB6 (SCL)
DB7 (SI)
I
The signal on the data bus is fetched at the rise of the WR signal.
In 68 series MPU interface mode, active "High".
This pin becomes an enable clock input of the 68 series MPU.
When in 8-bit interface mode, DB0 to DB7 are used as input data bus pin
In the 4-bit bus mode, only DB4 to DB7 are used as data input pin and DB0 to
DB3 are not used.
In the serial mode, DB6 (SCL) is used as serial clock input pin, DB7 (SI) is
used as serial data input pin and the others are not used.
LCD DRIVER OUTPUTS (DYNAMIC)
Table 3. Pin Description
NameI/ODescription
COM1 to COM24O
COMS1, COMS2O
SEG1 to SEG60O
SEGS1, SEGS2
SEGS4, SEGS5
O
Common signal output for character display
Common signal output for icon display
The COMS1 has two terminals and these two COMS1 are the same signal at
the same time.
Segment signal output for character display
Segment signal output for vertical icon display
LCD DRIVER OUTPUTS (STATIC)
Table 3. Pin Description (continued)
NameI/ODescription
COMSAOStatic common signal output for static icon display
SEGSA, B, C, D, EOStatic segment signal output for static icon display
* NOTE: DUMMY - These pins should be opened (floated).
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S6A009064 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE
S6A0090 has two kinds of interface type with MPU: bus mode and serial mode. Bus mode or serial mode is
selected by PS pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU
is selected by RES pin.
Table 4. Various kinds of MPU interface according to PS, RES and IF
PSRESIFCSBRSEDB0 to 3DB4 to 5DB6DB7
80 series
Bus
mode (H)
Serial
mode (L)
"*": Don't care ("High", "Low" or "Open"), (H)/(L): fixed "High"(VDD) or "Low"(VSS)
PS: "High" = bus mode, "Low" = serial mode
RES: "High" = 80-series MPU, "Low" = 68-series MPU
IF: "High" = 8-bit mode, "Low" = 4-bit mode (PS: "High")
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, “Low" = instruction register
E: 80-series active "Low", 68-series active "High"
SCL (DB6): serial clock input
SI (DB7): serial data input
Interface with MPU in Parallel Mode (PS = "High")
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM, and
one of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to
store instruction code transferred from MPU. To select DR or IR register, RS input pin is used in bus mode or
serial mode. In 4-bit bus mode, it is needed to transfer 4-bit data (DB4 to DB7) by two times. The high order bits
(for 8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3). The DB0 to
DB3 pins are floated in this 4-bit bus mode. After RES resets, S6A0090 considers first 4-bit data from MPU as the
high order bits.
(H)
68 series
(L)
(H)/(L)(H)/(L)CSBRS(H)/(L)**SCLSI
8 bit (H)CSBRSWRDB0 to 3DB4 to 5DB6DB7
4 bit (L)CSBRSWR*DB4 to 5DB6DB7
8 bit (H)CSBRSEDB0 to 3DB4 to 5DB6DB7
4 bit (L)CSBRSE*DB4 to 5DB6DB7
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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
Write
Write
RES
CSBRSE
DB0 to DB7
4-bit
4-bit
4-bi
t
4-bit
RES
CSB
RS
E
DB0 to DB7
Instruction
Write
Data
Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
RES
CSB
RS
E
to DB7
Instruction
Data
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
upper
lower
upper
lower
Instruction WriteData Write
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
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S6A009064 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
RES
CSB
RS
E
DB0 to DB7
4-bit
4-bit
4-bit
4-bit
upper
lower
upper
lower
Instruction WriteData Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCDS6A0090
D7D6D5D4D3D2D1D0D7
123456789
Interface with MPU in Serial Mode (PS = "Low")
When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, SCL
(DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip
selection input) are used. By setting CSB to "Low", S6A0090 can receive SCL input. If CSB is set to "High",
S6A0090 resets the internal 8-bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5,
D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6). At the
rising edge of the 8th serial clock, the serial data (D7–D0) is converted into 8-bit bus mode data. The RS input of
the DR / IR selection is latched at the rising edge of the 8th serial clock (SCL).
CSB
SI (DB7)
SCL (DB6)
RS
Figure 7. Timing Diagram of Serial Data Transfer
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