34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0079
INTRODUCTION
S6A0079 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can
display 2, or 4 lines with 5 x 8 dots format.
FUNCTIONS
• Character type dot matrix LCD driver & controller
• Internal driver: 34 common and 120 segment signal output
• Easy interface with 4-bit or 8-bit MPU
• 5 x 8 dots matrix possible
• Voltage converter for LCD drive voltage: 13V max (2 times/3 times)
• Automatic power on reset
FEATURES
• Internal memory
- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)
- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)
- Icon RAM (CGRAM): 16 x 8 bits (80 icons max.)
- Display Data RAM (DDRAM): 96 x 8 bits (96 characters max.)
• Low power operation
- Power supply voltage range: 2.7 - 5.5V (VDD)
- LCD Drive voltage range: 3.0 - 13.0V (VDD - V5)
• CMOS process
• Duty cycle: 1/33
• Internal oscillator with an external resistor
• Bare chip available
PROGRAMMABLE DUTY CYCLES
5-Dot Font Width
Display Line Duty Ratio Single-chip Operation
Numbers
2 1/33 2-line of 48 characters 80
Displayable Characters Possible Icons
4 1/33 4-line of 24 characters 80
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S6A0079 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
OSC1 OSC2TEST1
RESET
TEST2
RS
RW
DB4-DB7
DB3-DB1
DB0
Power on Reset
(POR)
Instruction
8
System
E
Interface
4-bit
8-bit
Input/
Output
Buffer
Register
(IR)
7
Data
88
Register
(DR)
Busy Flag
Oscillator
Instruction
Decoder
Address
Counter
78
Display Data
RAM (DDRAM)
96 x 8-bit
7
Timing Generator
7
8
8
120-bit
Shift
Register
34-bit
Shift
Register
120-bit
Latch
Circuit
Common
Driver
Segment
Driver
LCD Driver
Voltage Selector
COM0COM33
SEG1SEG120
Vci
C1
C2
V5OUT2
V5OUT3
VDD
GND(VSS)
Character
Generator
RAM
(CGRAM)
64 bytes
Voltage Converter
Parallel/Serial Converter and
Character
Generator
ROM
(CGROM)
9600 bits
55
Smooth Scroll Circuit
Cursor and
Blink
Controller
V1 - V5
2
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0079
In RW= "High", read operation.
When RW = "Low", write operation.
E (69) Input Read/write
enable
DB0-DB3
(70-73)
Input.
Output
Data bus 0-7 In 8-bit bus mode, used as low order bi-
Read/write enable signal.
directional data bus.
During 4-bit bus mode, open these pins.
DB4-DB7
(74-77)
In 8-bit bus mode, used as high order bi-
directional data bus. In case of 4-bit bus
mode, used as both high and low order.
DB7 used for busy flag output.
MPU
MPU
MPU
MPU
7
S6A0079 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE
This chip has all two kinds interface type with MPU: 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by
DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register
(DR), the other is instruction register(IR).
The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM target RAM is selected by RAM address setting instruction. Each internal operation, reading
from or writing into RAM, is done automatically.
Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR
automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM
automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS input pin in 4-bit/8-bit bus mode.
RS R/W Operation
0 0 Instruction write operation (MPU writes instruction code into IR)
0 1 Read busy flag (DB7) and address counter (DB0 - DB6)
1 0 Data write operation (MPU writes data into DR)
1 1 Data read operation (MPU reads data from DR)
BUSY FLAG (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not high.
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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0079
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 96 x 8 bits (96 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSBLSB
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Figure 1. DDRAM Address
5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-2FH, 40H-6FH. (refer to Figure 2)
Figure 2. 2-line X 48ch. Display (5-dot Font Width)
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
9
S6A0079 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 4-line Display
In case of 4-line display with 5-dot font, the address range of DDRAM is 00H-17H, 20H-37H, 40H-57H, 60H-77H.
(refer to Figure 3)
Display Position
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
12345
00 01 02 03 04
61 62 63 6460
SEG1
12345
01 02 03 04
2421 22 23
4441 42 43
61 62 63 64
12345
00 01 02 03
17
20 21 22 23
37
40 41 42 43
57
77
61 62 6360
20 21 22 23 24
. . . .13 14 15 16 17
2420 21 22 23
. . . .33 34 35 36 37
4440 41 42 43
. . . .53 54 55 56
. . . .74 75 76 7773
DDRAM Address
S6A0079
20 21 22 23 24
. . . .14 15 16 17
05
. . . .34 35 36 37
25
. . . .54 55 56
45
. . . .74 75 76 77
65
(After Shift Left)
20 21 22 23 24
. . . .13 14 15 1612
. . . .33 34 35 3632
. . . .53 54 55 56
. . . .74 75 7672 73
(After Shift Right)
52
57
SEG120
00
20
57
40
60
Figure 3. 4-line X 24ch. Display (5-dot Font Width)
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34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0079
TIMING GENERATION CIRCUIT
Timing generation circuit generates clock signals for the internal operations.
ADDRESS COUNTER (AC)
Address Counter (AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from)
DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can
be read through DB0 - DB6.
CURSOR/BLINK CONTROL CIRCUIT
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from CGRAM/CGROM is
transferred to 120-bit segment latch serially, which is stored to 120-bit shift latch. When each common is selected
by 34-bit common register, segment data also output through segment driver from 120-bit segment latch. In case
of 2-line or 4-line mode, COM0-COM33 have 1/33 duty ratio. COM0 (COM33) makes the data of CGRAM (Icon
RAM) enable to display icons.
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