120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
written permission of LCD Driver IC Team.
June. 2000.
Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
S6A0078 is a dot matrix LCD driver & controller IC which is fabricated by low power CMOS technology. It can
display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
•Character type dot matrix LCD driver & controller
•Internal driver: 34 common and 120 segment signal output
•Easy interface with 4-bit or 8-bit MPU
•Clock synchronized serial interface
•5 x 8 dots matrix possible
•6 x 8 dots matrix possible
•Bi-directional shift function
•All character reverse display
•Display shift per line
•Voltage converter for LCD drive voltage: 13V max (2 times/3 times)
•Various instruction functions
•Automatic power on reset
FEATURES
• Internal Memory
- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)
- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)
S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Table 2. Pad Description
PAD (No)
Input/
Output
NameDescriptionInterface
VDD (60)for logical circuit (+3V, +5V)
VSS1, VSS2
(66, 81)
V1-V5
(88-84)
Power supply
0V (GND)
Bias voltage level for LCD driving.
Power supply
Input voltage to the voltage converter to
Vci (78)Input
generate LCD drive voltage
(Vci = 2.5 - 4.5V).
SEG1-SEG80
(106-183, 1-42)
COM0-COM33
(105-89, 43-59)
OSC1, OSC2
(61, 62)
C1, C2
(80, 79)
Output
Output
Input
(OSC1),
Output
(OSC2)
Input
Segment
output
Common
output
Oscillator
External
capacitance
input
Segment signal output for LCD drive.LCD
Common signal output for LCD drive.LCD
When use internal oscillator, connect
external Rf resistor.
If external clock is used, connect it to
OSC1.
To use the voltage converter (2 times/3
times), these pins must be connected to the
external capacitance.
External
resistor/oscillator
(OSC1)
External
capacitance
RESET (63)InputReset pinInitialized to low-
When IE = "High", Instruction set is
IE (65)Input
Select pin of
instruction set
selected as Table 6.
When IE = "Low", Instruction set is selected
as Table 10.
The value of Vci is converted two times.
To use three times converter, the same
capacitance as that of C1-C2 should be
connected here.
V5 capacitance
V5OUT2 (82)
Two times
converter
output
Output
Three times
V5OUT3 (83)
converter
The value of Vci is converted three times.V5
output
IM (64)Input
Interface
mode
selection
Select Interface mode with the MPU.
When IM = "Low": Serial mode,
When IM = "High": 4-bit/8-bit bus mode.
-
-
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120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCDS6A0078
Table 2. Pad Description (Continued)
PAD (No)
Input/
Output
RS/CS (67)Input
RW/SID (68)Input
E/SCLK (69)Input
Input
DB0/SOD (70)
Output/
Output
DB1-DB3
(71-73)
Input.
Ouptut
DB4-DB7
(74-77)
NameDescriptionInterface
When bus mode, used as register selection
input. When RS/CS = "High", data register
Register
select/chip
select
is selected. When RS/CS = "Low",
Instruction register is selected.
When serial mode, used as chip selection
input. When RS/CS = "Low", selected.
When RS/CS = "High", not selected.
(low access enable)
When bus mode, used as read/write
Read
write/serial
input data
selection input. When RW/SID = "High",
read operation. When RW/SID = "Low",
write operation.
When serial mode, used for data input pin.
Read write
enable/serial
clock
When bus mode, used as read write enable
signal.
When serial mode, used as serial clock
input pin.
When 8-bit bus mode, used as lowest biData bus 0
bit/serial
output data
directional data bit. During 4-bit bus mode,
open this pin.
When serial mode, used as serial data
output pin. If not in read operation, open
this pin.
When 8-bit bus mode, used as low order bi-
directional data bus.
During 4-bit bus mode or serial mode, open
these pins.
Data bus 1- 7
When 8-bit bus mode, used as high order
bi-directional data bus. In case of 4-bit bus
mode, used as both high and low order.
DB7 used for Busy Flag output.
During serial mode, open these pins.
MPU
MPU
MPU
MPU
MPU
MPU
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S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE
This chip has all three kinds interface type with MPU: Serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is
selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or
write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The
data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the
next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR,
the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register (IR) is used
only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select
register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in serial mode (IM = "Low").
RSR/WOperation
00Instruction Write operation (MPU writes Instruction code into IR)
01Read busy flag (DB7) and address counter (DB0-DB6)
10Data write operation (MPU writes data into DR)
11Data read operation (MPU reads data from DR)
BUSY FLAG (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = low and R/W = high (read instruction operation),
through DB7 Before executing the next instruction, be sure that BF is not high.
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120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCDS6A0078
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 96 x 8 bits (96 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1)
MSBLSB
AC6AC5AC4AC3AC2AC1AC0
Figure 1. DDRAM Address
Display of 5-dot Font Width Character
5-dot 1-line Display
In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-5FH (Refer to Figure 2).
COM1
COM8
COM1
COM8
COM1
COM8
12345
00 01 02 03 04
SEG1
12345
12345
00 01 02 035F
20 21 22 23 24
. . . .13 14 15 16 17
SEG120
S6A0078S6A0078
20 21 22 23 24
0501 02 03 04
. . . .14 15 16 17
(After Shift Left)
20 21 22 23 24
. . . .13 14 15 1617
12
(After Shift Right)
25 26 27 28 29
18 19 1A 1B 1C
SEG1
25 26 27 28 29
19 1A 1B 1C
181D
25 26 27 28 29
18 19 1A 1B
Figure 2. 1-line X 48ch. Display
Display Position
44 45 46 47 48
. . . .2B 2C 2D 2E 2F
DDRAM Address
44 45 46 47 48
. . . .2C 2D 2E 2F 30
44 45 46 47 48
. . . .2A 2B 2C 2D 2E
COM9
COM16
SEG120
COM9
COM16
COM9
COM16
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S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-2FH, 40H-6FH (refer to Figure 3).
Figure 6. 2-line X 40ch. Display (6-dot Font width)
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
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S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-dot 4-line Display
In case of 4-line display with 6-dot font, the address range of DDARM is 00H-17H, 20H-37H, 40H-57H, 60H-77H
(refer to Figure 7).
Display Position
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
12345
00 01 02 03 04
61 62 63 6460
SEG1
12345
01 02 03 04
2421 22 23
4441 42 43
61 62 63 64
12345
00 01 02 03
17
20 21 22 23
37
40 41 42 43
57
77
61 62 6360
16 17 18 19 20
. . . .0F 10 11 12 13
2420 21 22 23
. . . .2F 30 31 32 33
4440 41 42 43
. . . .4F 50 51 52
. . . .70 71 72 736F
DDRAM Address
S6A0078
16 17 18 19 20
. . . .10 11 12 13
05
. . . .30 31 32 33
25
. . . .50 51 52
45
. . . .70 71 72 73
65
(After Shift Left)
16 17 18 19 20
. . . .0F 10 11 120E
. . . .2F 30 31 322E
. . . .4F 50 51 52
. . . .70 71 726E 6F
(After Shift Right)
4E
53
SEG120
14
34
53
54
74
16
Figure 7. 4-line X 20ch. Display (6-dot Font Width)
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCDS6A0078
TIMING GENERATION CIRCUIT
Timing generation circuit generates clock signals for the internal operations.
ADDRESS COUNTER (AC)
Address Counter (AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading
from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =
"High", AC can be read through DB0-DB6
CURSOR/BLINK CONTROL CIRCUIT
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from
SEGRAM/CGRAM/CGROM is transferred to 120-bit segment latch serially, and then it is stored to 120-bit shift
latch. When each common is selected by 34-bit common register, segment data also output through segment
driver from 100-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or
4-line mode, COM0-COM33 have 1/33 duty ratio.
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S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM (CHARACTER GENERATOR ROM)
CGROM has 5 × 8-dot 240 character pattern
CGRAM (CHARACTER GENERATOR RAM)
CGRAM has up to 5 × 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used
(refer to Table 4).
5x8 Dot Character Pattern
Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data)CGRAM AddressCGRAM Data
1. When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.
In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1",
enabled dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1",
enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.
2. "X": Don't care
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S6A0078 120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEGRAM (SEGMENT ICON RAM)
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17)
makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does
that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 7).
Table 5. Relationship Between SEGRAM Address and Display Pattern