Samsung S6A0031 Datasheet
S6A0031
Contents in this document are subject to change without notice. No part of this document may be reproduced or
for any purpose, without the express written
permission of LCD Driver IC Team.
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
June. 1999.
Ver. 0.5
Prepared by: Tae-Kwang, Park
parktk@samsung.co.kr
transmitted in any form or by any means, electronic or mechanical,
S6A0031 Specification Revision History
Version Content Date
0.0 Original Feb.1999
0.1
ECKON pad added
POR circuit added
Page 6: E_RD signal description is changed
E_RD: Active low signal for writing command in 6800 mode or high enable
0.2
signal for reading command in 8080 mode. →
E_RD: Active low signal for writing command or high enable signal for reading
command in 6800 mode, low enable signal for reading command in
8080 mode.
Page 6: LCD DRIVER OUTPUT added
Page 18: Power ON / OFF timing added
0.3
Page 29: I
Page 30: I
(VDD = 2.4~3.6V): 150µA → 50µA
DD1
(VDD = 3.6~5.5V): 250µA → 80µA
DD1
0.4 Page 1, 2, 11: CGROM character size is changed from 256 to 254. Jun.1999
Page 6: RW_WR active low -> active high
0.5
Page 6: RW_WR active low -> low enable
Page 20: Wait for more than 1.2us or Busy Check -> delete “or Busy Check”
Page 21: Wait for more than 1.2us or Busy Check -> delete “or Busy Check”
Mar.1999
Apr.1999
May.1999
Jun.1999
S6A0031 PRELIMINARY SPEC. VER. 0.5 8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CO
NTENTS
INTRODUCTION.......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
BLOCK DIAGRAM ...................................................................................................................................... 2
PAD CONFIGURATION............................................................................................................................... 3
PAD CENTER COORDINATES...................................................................................................................4
PIN DESCRIPTION...................................................................................................................................... 5
POWER SUPPLY.................................................................................................................................5
SYSTEM CONTROL............................................................................................................................. 5
MPU INTERFACE ................................................................................................................................ 6
LCD DRIVER OUTPUT......................................................................................................................... 6
TEST....................................................................................................................................................6
FUNCTIONAL DESCRIPTION.....................................................................................................................7
MICROPROCESSOR INTERFACE ...................................................................................................... 7
ADDRESS COUNTER (AC)................................................................................................................ 10
DISPLAY DATA RAM (DDRAM)......................................................................................................... 10
CHARACTER GENERATOR ROM (CGROM)..................................................................................... 11
CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 12
LCD DRIVER CIRCUIT....................................................................................................................... 13
INSTRUCTION DESCRIPTION.................................................................................................................. 14
INITIALIZING............................................................................................................................................. 18
HARDWARE RESET.......................................................................................................................... 18
INSTRUCTION INITIALIZING WITH RESET....................................................................................... 20
LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 22
MPU INTERFACE...................................................................................................................................... 23
INTERFACING WITH 8080-SERIES MICROPROCESSORS.............................................................. 23
INTERFACING WITH 6800-SERIES MICROPROCESSORS.............................................................. 23
APPLICATION INFORMATION FOR LCD PANEL.................................................................................... 24
FRAME FREQUENCY............................................................................................................................... 26
MAXIMUM ABSOLUTE RATE................................................................................................................... 27
ELECTRICAL CHARACTERISTICS.......................................................................................................... 28
DC CHARACTERISTICS.................................................................................................................... 28
AC CHARACTERISTICS.................................................................................................................... 30
2
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.5 S6A0031
INTRODUCTION
This character driver and controller LSI for liquid crystal dot matrix display systems can display 1-line of 16
characters with the 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit or
8-bit parallel mode. Voltage follower and bias circuit is built in the IC.
FEATURES
Driver Output Circuits
− 8 common outputs / 80 segment outputs
Applicable Duty Ratio
Font size Display size Duty Contents of outputs
5 x 8 1-line x 16 characters 1/8 1 x 16 characters
On-chip Display Data RAM
− Character Generator ROM (CGROM): 10,160 bits (254 characters x 5 x 8 dots)
− Character Generator RAM (CGRAM): 80 bits (2 characters x 5 x 8 dots)
− Display Data RAM (DDRAM): 256 bits (16 characters x 1-line + 16 extended characters)
Microprocessor Interface
− 8-bit parallel interface with 6800-series or 8080-series MPU
− 4-bit parallel interface with 6800-series or 8080-series MPU
Function Set
− Simple instruction set
− COM / SEG bi-directional (4 types LCD application available)
− Hardware reset (RESETB)
On-chip Analog Circuit
− Internal RC oscillator circuit
− Voltage follower & bias circuit
− Automatic power on reset circuit
Operating Voltage Range
− Supply voltage (VDD): 2.4 to 5.5 V
− LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.
Low Power Consumption
Package Type
− Gold bumped chip
1
S6A0031 PRELIMINARY SPEC. VER. 0.5 8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
DB4
DIRC
CK
555
8
8
(OR)
MI
ECKON
BLOCK DIAGRAM
Power On
Reset (POR)
RESETB
CSB
RS
RW_WR
E_RD
DB7 to
DB3 to
DB0
Input Buffer
Parallel
Interface
4 bit/8 bit
(6800/8080
-series)
Instruction
8
Register
8
Register
Data Output
8
Register
(IR)
Data
(DR)
Address
Counter
Instruction
Decoder
Display
Data RAM
(DDRAM)
256 bits
Timing GeneratorOscillator
8 bits
Shift
Register
80 bits
8
Shift
Register
80 bits
Latch
Circuit
Common
Driver
Segment
Driver
COM1 to
COM8
SEG1 to
SEG80
DD
V
GND
Busy
Flag
Character
Generator
RAM
(CGRAM)
80 bits
5 5
Segment Data Conversion
Character
Generator
ROM
(CGROM)
10,160 bits
Figure 1. Block Diagram
Cursor
and
Blink
Controller
DIRS
LCD Driving
Voltage Selector
Voltage Follower
& Bias Resistor
V0 V1 V2 V3 V4
2
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.5 S6A0031
1
44
60
129
5352136
S6A0031
(+2600, +590)
(-2600, +605)
30
µ
m
30
µ
m
30
µ
m
60
µ
m
30
µ
m
PAD CONFIGURATION
z
130
137
144
Y
(0,0)
X
PAD
DUMMY_PAD
Figure 2. S6A0031 Chip Configuration
Table 1. S6A0031 Pad Dimensions
Item Pad No.
Size
X Y
Chip size - 5430 1410
Pad pitch
1 to 44 90
45 to 144 70
1 to 44 52 92
Bumped pad size
45 to 59 92 42
60 to 129 42 92
130 to 144 92 42
59
45
Unit
µm
Bumped pad height
1 to 144 17 (Typ.)
COG Align Key Coordinate
30µm 30µm 30µm
3
30µm 30µm 30µm
S6A0031 PRELIMINARY SPEC. VER. 0.5 8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
50
COM6
2605
-205
100
SEG46
-385
595
150
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
No. Name X Y No. Name X Y No. Name X Y
1 DUMMY -1935 -595 51 COM7 2605 -135 101 SEG47 -455 595
2 VSS -1845 -595 52 COM8 2605 -65 102 SEG48 -525 595
3 VSS -1755 -595 53 SEG1 2605 5 103 SEG49 -595 595
4 VSS -1665 -595 54 SEG2 2605 75 104 SEG50 -665 595
5 ECKON -1575 -595 55 SEG3 2605 145 105 SEG51 -735 595
6 VDD -1485 -595 56 SEG4 2605 215 106 SEG52 -805 595
7 V4 -1395 -595 57 SEG5 2605 285 107 SEG53 -875 595
8 V3 -1305 -595 58 SEG6 2605 355 108 SEG54 -945 595
9 V2 -1215 -595 59 DUMMY 2605 425 109 SEG55 -1015 595
10 V1 -1125 -595 60 DUMMY 2415 595 110 SEG56 -1085 595
11 CK -1035 -595 61 SEG7 2345 595 111 SEG57 -1155 595
12 VDD -945 -595 62 SEG8 2275 595 112 SEG58 -1225 595
13 VDD -855 -595 63 SEG9 2205 595 113 SEG59 -1295 595
14 VDD -765 -595 64 SEG10 2135 595 114 SEG60 -1365 595
15 V0 -675 -595 65 SEG11 2065 595 115 SEG61 -1435 595
16 V0 -585 -595 66 SEG12 1995 595 116 SEG62 -1505 595
17 VDD -495 -595 67 SEG13 1925 595 117 SEG63 -1575 595
18 VDD -405 -595 68 SEG14 1855 595 118 SEG64 -1645 595
19 VDD -315 -595 69 SEG15 1785 595 119 SEG65 -1715 595
20 RESETB -225 -595 70 SEG16 1715 595 120 SEG66 -1785 595
21 RS -135 -595 71 SEG17 1645 595 121 SEG67 -1855 595
22 RW_WR -45 -595 72 SEG18 1575 595 122 SEG68 -1925 595
23 VSS 45 -595 73 SEG19 1505 595 123 SEG69 -1995 595
24 E_RD 135 -595 74 SEG20 1435 595 124 SEG70 -2065 595
25 VDD 225 -595 75 SEG21 1365 595 125 SEG71 -2135 595
26 DB0 315 -595 76 SEG22 1295 595 126 SEG72 -2205 595
27 DB1 405 -595 77 SEG23 1225 595 127 SEG73 -2275 595
28 DB2 495 -595 78 SEG24 1155 595 128 SEG74 -2345 595
29 DB3 585 -595 79 SEG25 1085 595 129 DUMMY -2415 595
30 DB4 675 -595 80 SEG26 1015 595 130 DUMMY -2605 425
31 DB5 765 -595 81 SEG27 945 595 131 SEG75 -2605 355
32 DB6 855 -595 82 SEG28 875 595 132 SEG76 -2605 285
33 DB7 945 -595 83 SEG29 805 595 133 SEG77 -2605 215
34 CSB 1035 -595 84 SEG30 735 595 134 SEG78 -2605 145
35 VSS 1125 -595 85 SEG31 665 595 135 SEG79 -2605 75
36 MI 1215 -595 86 SEG32 595 595 136 SEG80 -2605 5
37 VDD 1305 -595 87 SEG33 525 595 137 DUMMY -2605 -65
38 TEST 1395 -595 88 SEG34 455 595 138 DUMMY -2605 -135
39 VSS 1485 -595 89 SEG35 385 595 139 DUMMY -2605 -205
40 DIRC 1575 -595 90 SEG36 315 595 140 DUMMY -2605 -275
41 VDD 1665 -595 91 SEG37 245 595 141 DUMMY -2605 -345
42 DIRS 1755 -595 92 SEG38 175 595 142 DUMMY -2605 -415
43 VSS 1845 -595 93 SEG39 105 595 143 DUMMY -2605 -485
44 DUMMY 1935 -595 94 SEG40 35 595 144 DUMMY -2605 -555
45 COM1 2605 -555 95 SEG41 -35 595 145
46 COM2 2605 -485 96 SEG42 -105 595 146
47 COM3 2605 -415 97 SEG43 -175 595 147
48 COM4 2605 -345 98 SEG44 -245 595 148
49 COM5 2605 -275 99 SEG45 -315 595 149
4
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.5 S6A0031
, External clock by CK pin is used as system clock, and internal
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
Name I/O Description
VDD Supply Power supply
VSS Supply Ground
V0 I Bias voltage Input for LCD driving
LCD driving voltage outputs.
Voltages should have the following relationship;
V1
V2
V3
V4
O
V0 ≥ V1 ≥ V2 = V3 ≥ V4 ≥ VSS
These voltages are generated as following table.
LCD bias V1 V2 V3 V4
1/4 bias (3/4) x V0 (2/4) x V0 (1/4) x V0
SYSTEM CONTROL
Table 3. Pin Description (Continued)
Name I/O Description
Clock source selection input
ECKON I
CK I
MI I
DIRC I
DIRS I
When ECKON = "High"
oscillator circuit is turned OFF. When ECKON = "Low", internal oscillator is used.
External clock input (when ECKON = "High")
It must be fixed "High" or "Low" when the internal oscillation circuit is used (When
ECKON = "Low").
MPU interface selection input
MI = "Low", 8080-series MPU
MI = "High", 6800-series MPU
COM direction selection input
When DIRC = "Low"
COM1 → COM2 - - - - → COM7 → COM8
When DIRC = "High"
COM8 → COM7 - - - - → COM2 → COM1
SEG direction selection input
When DIRS = "Low"
SEG1 → SEG2 - - - - → SEG79 → SEG80
When DIRS = "High"
SEG80 → SEG79 - - - - → SEG2 → SEG1
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S6A0031 PRELIMINARY SPEC. VER. 0.5 8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MPU INTERFACE
Table 3. Pin Description (Continued)
Name I/O Description
RESETB I
CSB I
RS I
RW_WR I
E_RD I
DB0 to DB3
DB4 to DB7
I/O
Reset input
Initialization is performed by "Low" level sensing of the RESETB signal.
Chip selection input
S6A0031 is selected while CSB is "Low".
Register selection input
When RS = "Low", instruction register
When RS = "High", data register
In 8080-series MPU interface mode, this pin is connected to WR pin of MPU and is an
active high write signal.
In 6800-series MPU interface mode, this pin is connected to R/W pin of MPU.
When RW_WR = "High", read mode
When RW_WR = "Low", write mode
In 8080-series MPU interface mode, this pin is connected to RD pin of MPU and is a low
enable read signal.
In 6800-series MPU interface mode, this pin is connected to E pin of MPU and enables
read or write command according to RW_WR signal.
When 8-bit interface mode, used as bi-directional data bus DB0 to DB7
During 4-bit bus mode, only DB4 to DB7 are used. In this case DB0 - DB3 pins are
don’ t care (connect to "High", "Low" or open).
LCD DRIVER OUTPUT
Table 3. Pin Description (Continued)
Name I/O Description
COM1 to
COM8
SEG1 to
SEG80
O Common signal output for character display
O Segment signal output for character display
TEST
Table 3. Pin Description (Continued)
Name I/O Description
TEST I
*NOTE: DUMMY – These pins should be opened (floated).
6
Test pin
This pin is not used for normal operation and should be connect to "Low".
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.5 S6A0031
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
S6A0031 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the
DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin.
Table 4. Various Kinds of MPU Interface according to MI and DL Bit
MI DL CSB RS
6800-series
(H)
8080-series
(L)
NOTE: "-" - Don’t care ("High", "Low" or Open)
(H): fixed "High" (VDD)
(L): fixed "Low" (VSS)
MI: "High" = 6800-series MPU, "Low" = 8080-series MPU
DL: "High" = 8-bit mode, "Low" = 4-bit mode
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: Read / Write indicating signal in 6800 mode, active high signal for writing command in 8080 mode.
E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode,
low enable signal for reading command in 8080 mode.
Parallel Interface
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM. Target RAM is
selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code
transferred from MPU. To select DR or IR register, RS input pin is used.
8-bit (H) CSB RS R/W E DB0 to DB3 DB4 to DB7
4-bit (L) CSB RS R/W E - DB4 to DB7
8-bit (H) CSB RS WR RD DB0 to DB3 DB4 to DB7
4-bit (L) CSB RS WR RD - DB4 to DB7
RW_WR
E_RD DB0 to DB3 DB4 to DB7
During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as temporary
data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM address set
instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in the 4-bit bus
mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit bus mode (from
the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate the correct address.
So it is recommended to set address before writing. The instruction read operation is supported for indicating
internal operation is being processed (Busy Flag).
In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits (for
8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and write
transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode.
After RESETB operation, S6A0031 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus
mode.
7
S6A0031 PRELIMINARY SPEC. VER. 0.5 8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Instruction
Data
Busy Flag
Dummy
Valid
Data
Instruction
Data
Busy flag
Dummy
Valid
Data
DL
MI
CSB
RS
RW_WR
E_RD
DB7 to DB0
Valid
Write
Read
Data Read
Data Read
Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)
DL
MI
CSB
RS
RW_WR
E_RD
DB7 to DB0
Write
Read
Data Read
Valid
Data Read
Write
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)
8
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