SAMSUNG S3C2443X User Manual

S3C2443X

USER’S MANUAL

Revision 1.2

REVISION HISTORY

Revision Date Description

1.0 February 7, 2007 First release

1.1 March 6, 2007

1.2 March 22, 2007

IIC Bus Interface update
Overview, Electrical Data update
(Operating voltage of VDD_SDRAM: 1.8V => 1.8V/2.5V/3.3V)

S3C2443X

32-BIT RISC

MICROCONTROLLERS

USER MANUAL

Revision 1.2

Important Notice

The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
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products or product specifications with the intent to
improve function or design at any time and without
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under the patent rights of Samsung or others.

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S3C2443X 32-Bit RISC Microcontrollers
User manual, Revision 1.2
Publication Number:

© 2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.

Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung- gu
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900

TEL: (82)-[phone]
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Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea

21-S3-C2443X-012007

Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BVQ1 Certificate No. 9330). All semiconductor products are
designed and manufactured in accordance with the highest quality standards
and objectives.

Table of Contents

Chapter 1 Product Overview

Introduction ...................................................................................................................................................1-1

Features........................................................................................................................................................1-2

Block Diagram...............................................................................................................................................1-5

Pin Assignments ...........................................................................................................................................1-6

Signal Descriptions .......................................................................................................................................1-26

S3C2443X Operation Mode Description..............................................................................................1-32

S3C2443X Memory MAP and Base Address of Special Registers .....................................................1-33

Chapter 2 System Controller

Overview .......................................................................................................................................................2-1

Feature..........................................................................................................................................................2-1

Block Diagram...............................................................................................................................................2-2

Functional Descriptions.................................................................................................................................2-3

Watchdog Reset...................................................................................................................................2-4

Software Reset.....................................................................................................................................2-5

Wakeup Reset......................................................................................................................................2-5

Clock Management.......................................................................................................................................2-6

Clock Generation Overview..................................................................................................................2-6

Clock Source Selection........................................................................................................................2-6

PLL (Phase-Locked-Loop) ...................................................................................................................2-8

Change PLL Settings in Normal Operation..........................................................................................2-8

System Clock Control...........................................................................................................................2-9

Example for Configuring Clock Regiter to Produce Specific Frequency of AMBA clocks...................2-11

ECLK Control........................................................................................................................................2-12

Power Management......................................................................................................................................2-13

Power Mode State Diagram.................................................................................................................2-13

Power Saving Modes ...........................................................................................................................2-14

Wake-up Event.....................................................................................................................................2-16

Output Port State and Stop and Sleep Mode.......................................................................................2-16

Power Saving Mode Entering/Exiting Condition...................................................................................2-17

Register Descriptions....................................................................................................................................2-18

Address Map ........................................................................................................................................2-18

Individual Register Descriptions....................................................................................................................2-20

Clock Source Control Registers (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON)2-20

Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON).....................2-23

Power Management Registers (PWRMODE and PWRCFG)..............................................................2-27

Reset Control Registers (SWRST and RSTCON)...............................................................................2-29

Usage of PWROFF_SLP......................................................................................................................2-30

System Controller Status Registers (WKUPSTAT and RSTSTAT).....................................................2-31

Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC)....................................................2-32

MISC. (INFORM0~3)............................................................................................................................2-34

USB PHY Control register (PHYctrl) ....................................................................................................2-34

USB PHY POWER Control register (PHYPWR)..................................................................................2-35

USB Reset Control Register (urstcon).................................................................................................2-36

USB Clock Control register (uclkcon)...................................................................................................2-36

S3C2443X MICROCONTROLLER iii

Table of Contents (Continued)

Chapter 3 Bus Matrix & EBI

Overview........................................................................................................................................................3-1

Special Function Registers............................................................................................................................3-2

Matrix Core 0 priority Register (Bpriority0)...........................................................................................3-2

Matrix Core 1 priority Register (Bpriority1)...........................................................................................3-2

EBI Control Register (EBICON) ....................................................................................................................3-3

Chapter 4 Bus Priorities

Overview........................................................................................................................................................4-1

Bus Priority Map ...................................................................................................................................4-1

Chapter 5 Static Memory Controller (SMC)

Overview........................................................................................................................................................5-1

Feature..........................................................................................................................................................5-2

Block Diagram...............................................................................................................................................5-3

Asynchronous Read .............................................................................................................................5-4

Asynchronous Burst Read....................................................................................................................5-6

Synchronous Read/Synchronous Burst Read......................................................................................5-7

Asynchronous Write..............................................................................................................................5-8

Synchronous Write/ Synchronous Burst Write.....................................................................................5-10

Bus Turnaround....................................................................................................................................5-11

Special Registers ..........................................................................................................................................5-13

Bank Idle Cycle Control Registers 0-5..................................................................................................5-13

Bank Read wait State Control Registers 0-5........................................................................................5-13

Bank Write wait State Control Registers 0-5........................................................................................5-14

Bank Output Enable Assertion Delay Control Registers 0-5................................................................5-14

Bank Write Enable Assertion Delay Control Registers 0-5..................................................................5-15

Bank Control Registers 0-5 ..................................................................................................................5-16

Bank Status Registers 0-5....................................................................................................................5-18

Bank Burst Read wait Delay Control Registers 0-5..............................................................................5-18

Bank Onenand Type Selection Register ..............................................................................................5-19

SMC Status Register............................................................................................................................5-19

SMC Control Register...........................................................................................................................5-20

iv S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 6 Mobile DRAM Controller

Overview .......................................................................................................................................................6-1

Block Diagram...............................................................................................................................................6-2

Mobile DRAM Initialization Sequence...........................................................................................................6-3

Mobile DRAM (SDRAM OR DDR) Initialization Sequence..................................................................6-3

Mobile DRAM Configuration Register..................................................................................................6-6

Mobile DRAM Control Register............................................................................................................6-7

Mobile DRAM Timming Control Register.............................................................................................6-8

Mobile DRAM (Extended) Mode Regiter Set Register.........................................................................6-9

Mobile DRAM Refresh Control Register ..............................................................................................6-10

Mobile DRAM Write Buffer Time out Register......................................................................................6-10

Chapter 7 NAND Flash Controller

Overview .......................................................................................................................................................7-1

Features ...............................................................................................................................................7-1

Block Diagram......................................................................................................................................7-2

Boot Loader Function...........................................................................................................................7-2

Pin Configuration Table........................................................................................................................7-3

Nand Flash Memory Timing.................................................................................................................7-4

Software Mode .....................................................................................................................................7-4

2048 Byte SLC ECC Parity Code Assignment Table...........................................................................7-6

16 Byte ECC SLC Parity Code Assignment Table...............................................................................7-6

ECC Module Features..........................................................................................................................7-7

SLC ECC Programming Guide ............................................................................................................7-8

MLC ECC Programming Guide (Encoding) .........................................................................................7-8

MLC ECC Programming Guide (Decoding).........................................................................................7-9

Nand Flash Memory Mapping..............................................................................................................7-10

Nand Flash Controller Special Registers......................................................................................................7-12

Nand Flash Controller Register Map....................................................................................................7-12

Nand Flash Configuration Register......................................................................................................7-13

Control Register ...................................................................................................................................7-14

Command Register ..............................................................................................................................7-16

Address Register..................................................................................................................................7-16

Data Register........................................................................................................................................7-16

Main Data Area ECC Register .............................................................................................................7-17

Spare Area ECC Register....................................................................................................................7-18

Progrmmable Block Address Register.................................................................................................7-19

Nfcon Status Register ..........................................................................................................................7-21

ECC0/1 Status Register.......................................................................................................................7-22

Main Data Area ECC0 Status Register................................................................................................7-24

Spare Area ECC Status Register.........................................................................................................7-25

MLC 4-bit ECC Error Patten Register..................................................................................................7-25

S3C2443X MICROCONTROLLER v

Table of Contents (Continued)

Chapter 8 CF Controller

Overview........................................................................................................................................................8-1

Features....................................................................................................................... .........................8-2

Block Diagram ......................................................................................................................................8-3

Timing Diagram ....................................................................................................................................8-6

Special Function Registers...................................................................................................................8-11

Individual Register Descriptions....................................................................................................................8-14

MUX_REG Register..............................................................................................................................8-14

PCCARD Interrupt Mask & Source Register........................................................................................8-16

PCCARD_Attr Register.........................................................................................................................8-17

PCCARD_I/O Register .........................................................................................................................8-17

PCCARD_COMM Register...................................................................................................................8-18

ATA_Control Register...........................................................................................................................8-19

ATA_Status Register............................................................................................................................8-19

ATA_Command Register......................................................................................................................8-20

ATA_SWRST Register .........................................................................................................................8-21

ATA_IRQ Register................................................................................................................................8-21

ATA_IRQ_Mask Register .....................................................................................................................8-22

ATA_CFG Register...............................................................................................................................8-23

ATA_PIO_Time Register......................................................................................................................8-25

ATA_UDMA_Time Register..................................................................................................................8-25

ATA_XFR_NUM Register.....................................................................................................................8-26

ATA_XFR_CNT Register......................................................................................................................8-26

ATA_TBUF_START Register...............................................................................................................8-26

ATA_TBUF_SIZE Register...................................................................................................................8-27

ATA_SBUF_START Register...............................................................................................................8-27

ATA_SBUF_SIZE Register...................................................................................................................8-27

ATA_CADDR_TBUF Register..............................................................................................................8-28

ATA_CADDR_SBUF Register..............................................................................................................8-28

ATA_PIO_DTR Register.......................................................................................................................8-28

ATA_PIO_FED Register.......................................................................................................................8-29

ATA_PIO_SCR Register.......................................................................................................................8-29

ATA_PIO_LLR Register........................................................................................................................8-29

ATA_PIO_LMR Register.......................................................................................................................8-30

ATA_PIO_LMR Register.......................................................................................................................8-30

ATA_PIO_DVR Register.......................................................................................................................8-30

ATA_PIO_CSD Register.......................................................................................................................8-31

ATA_PIO_DAD Register.......................................................................................................................8-31

ATA_PIO_RDATA Register..................................................................................................................8-31

BUS_FIFO_STATUS Register .............................................................................................................8-32

ATA_FIFO_STATUS Register..............................................................................................................8-32

vi S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 9 DMA Controller

Overview .......................................................................................................................................................9-1

DMA Request Sources .................................................................................................................................9-2

DMA Operation .............................................................................................................................................9-3

External DMA DREQ/DACK Protocol ..................................................................................................9-4

Examples of Possible Cases................................................................................................................9-7

DMA Special Registers.................................................................................................................................9-8

DMA Initial Source Register (DISRC) ..................................................................................................9-8

DMA Initial Source Control Register (DISRCC)...................................................................................9-8

DMA Initial Destination Register (DIDST)............................................................................................9-9

DMA Initial Destination Control Register (DIDSTC).............................................................................9-9

DMA Control Register (DCON) ............................................................................................................9-10

DMA Status Register (DSTAT).............................................................................................................9-12

DMA Current Source Register (DCSRC).............................................................................................9-13

Current Destination Register (DCDST)................................................................................................9-13

DMA Mask Trigger Register (DMASKTRIG)........................................................................................9-14

DMA Requeset Selection Register (DMAREQSEL) ............................................................................9-15

Chapter 10 Interrupt Controller

Overview .......................................................................................................................................................10-1

Interrupt Controller Operation ..............................................................................................................10-2

Interrupt Sources..................................................................................................................................10-3

Interrupt Priority Generating Block.......................................................................................................10-4

Interrupt Priority....................................................................................................................................10-5

Interrupt Controller Special Registers...........................................................................................................10-6

Source Pending (SRCPND) Register...................................................................................................10-6

Interrupt Mode (INTMOD) Register......................................................................................................10-8

Interrupt Mask (INTMSK) Register.......................................................................................................10-10

Priority Register (PRIORITY) ...............................................................................................................10-12

Interrupt Pending (INTPND) Register ..................................................................................................10-14

Interrupt Offset (INTOFFSET) Register ...............................................................................................10-16

Sub Source Pending (SUBSRCPND) Register....................................................................................10-17

Interrupt Sub Mask (INTSUBMSK) Register........................................................................................10-19

Interrupt Sub Mask (INTSUBMSK) Register........................................................................................10-19

S3C2443X MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 11 I/O PORTS

Overview........................................................................................................................................................11-1

S3C2443X Port Configuration..............................................................................................................11-2

Port Control Descriptions ..............................................................................................................................11-8

Port Configuration Register (Gpacon-Gpmcon)...................................................................................11-8

Port Data Register (Gpadat-Gpmdat)...................................................................................................11-8

Port Pull-Up/Down Register (Gpbudp-Gpeudp,Gpgudph,Gphudp,Gpjudp,Gpludp,Gpmudp).............11-8

Miscellaneous Control Register............................................................................................................11-8

External Interrupt Control Register.......................................................................................................11-8

I/O Port Control Register...............................................................................................................................11-9

Port A Control Registers (GPACDL, GPACDH)...................................................................................11-9

GPACDL/GPACDH Setup....................................................................................................................11-11

Port B Control Registers (GPBCON, GPBDAT, GPBUDP)..................................................................11-12

Port C Control Registers (GPCCON, GPCDAT, GPCUDP).................................................................11-14

Port D Control Registers (GPDCON, GPDDAT, GPDUDP).................................................................11-16

Port E Control Registers (GPECON, GPEDAT, GPEUDP)..................................................................11-18

Port F Control Registers (GPFCON, GPFDAT, GPFUDP) ..................................................................11-20

Port G Control Registers (GPGCON, GPGDAT, GPGUDP)................................................................11-21

Port H Control Registers (GPHCON, GPHDAT, GPHUDP).................................................................11-23

Port J Control Registers (GPJCON, GPJDAT, GPJUDP)....................................................................11-25

Port L Control Registers (GPLCON, GPLDAT, GPLUDP)...................................................................11-27

Port M Control Registers (GPMCON, GPMDAT, GPMUDP)...............................................................11-29

Miscellaneous Control Register (MISCCR)..........................................................................................11-30

Dclk Control Registers (DCLKCON).....................................................................................................11-31

EXTINTn (External Interrupt Control Register n).................................................................................11-32

EINTFLTn (External Interrupt Filter Register n) ..................................................................................11-36

EINTMASK (External Interrupt Mask Register)....................................................................................11-37

EINTPEND (External Interrupt Pending Register)................................................................................11-38

GSTATUSn (General Status Registers)...............................................................................................11-39

DSCn (Drive Strength Control).............................................................................................................11-40

MSLCON (Memory Sleep Control Register) ........................................................................................11-43

SDATA / RDATA Pull-Down Control Registers (DATAPDEN).............................................................11-45

Chapter 12 Watchdog Timer

Overview........................................................................................................................................................12-1

Features....................................................................................................................... .........................12-1

Watchdog Timer Operation...........................................................................................................................12-2

Block Diagram ......................................................................................................................................12-2

Wtdat & Wtcnt.......................................................................................................................................12-2

Consideration of Debugging Environment............................................................................................12-2

Watchdog Timer Special Registers...............................................................................................................12-3

Watchdog Timer Control (WTCON) Register.......................................................................................12-3

Watchdog Timer Data (WTDAT) Register............................................................................................12-4

Watchdog Timer Count (WTCNT) Register..........................................................................................12-4

viii S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 13 PWM Timer

Overview .......................................................................................................................................................13-1

Feature.................................................................................................................................................13-1

PWM Timer Operation ..................................................................................................................................13-3

Prescaler & Divider...............................................................................................................................13-3

Basic Timer Operation..........................................................................................................................13-3

Auto Reload & Double Buffering ..........................................................................................................13-4

Timer Initialization Using Manual Update bit and Inverter Bit..............................................................13-5

Timer Operation ...................................................................................................................................13-6

Pulse Width Modulation (PWM) ...........................................................................................................13-7

Output Level Control ............................................................................................................................13-8

Dead Zone Generator ..........................................................................................................................13-9

Dma request mode...............................................................................................................................13-10

PWM Timer Control Registers......................................................................................................................13-11

Timer Configuration Register0 (TCFG0)..............................................................................................13-11

Timer Configuration Register1 (TCFG1)..............................................................................................13-12

Timer Control (TCON) Register ...........................................................................................................13-13

Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)................................13-15

Timer 0 Count Observation Register (TCNTO0)..................................................................................13-15

Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)................................13-16

Timer 1 Count Observation Register (TCNTO1)..................................................................................13-16

Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)................................13-17

Timer 2 Count Observation Register (TCNTO2)..................................................................................13-17

Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)................................13-18

Timer 3 Count Observation Register (TCNTO3)..................................................................................13-18

Timer 4 Count Buffer Register (TCNTB4)............................................................................................13-19

Timer 4 Count Observation Register (TCNTO4)..................................................................................13-19

Chapter 14 Real Time Clock

Overview .......................................................................................................................................................14-1

Features ...............................................................................................................................................14-1

Real Time Clock Operation..................................................................................................................14-2

Leap Year Generator............................................................................................................................14-2

Read/Write Registers...........................................................................................................................14-3

Backup Battery Operation....................................................................................................................14-3

Alarm Function .....................................................................................................................................14-3

Tick time interrupt.................................................................................................................................14-4

32.768kHz X-Tal Connection Example................................................................................................14-5

S3C2443X MICROCONTROLLER ix

Table of Contents (Continued)

Chapter 14 Real Time Clock

Real Time Clock Special Registers...............................................................................................................14-6

Real Time Clock Control (RTCCON) Register.....................................................................................14-6

Tick Time Count (TICNT0) Register 0..................................................................................................14-7

Tick Time Count (TICNT1) Register 1..................................................................................................14-7

RTC Alarm Control (RTCALM) Register ..............................................................................................14-8

Alarm Second Data (ALMSEC) Register..............................................................................................14-9

Alarm Min Data (ALMMIN) Register.....................................................................................................14-9

Alarm Hour Data (ALMHOUR) Register...............................................................................................14-9

Alarm Date Data (ALMDATE) Register................................................................................................14-10

Alarm Mon Data (ALMMON) Register..................................................................................................14-10

Alarm Year Data (ALMYEAR) Register................................................................................................14-10

BCD Second (BCDSEC) Register........................................................................................................14-11

BCD Minute (BCDMIN) Register..........................................................................................................14-11

BCD Hour (BCDHOUR) Register.........................................................................................................14-12

BCD Date (BCDDATE) Register ..........................................................................................................14-12

BCD Day (BCDDAY) Register..............................................................................................................14-12

BCD Month (BCDMON) Register.........................................................................................................14-13

BCD Year (BCDYEAR) Register..........................................................................................................14-13

TICK Counter (tickcnt) Register............................................................................................................14-13

RTC Lowbat Check (RTCLbat) Register..............................................................................................14-14

Chapter 15 UART

Overview........................................................................................................................................................15-1

Features....................................................................................................................... .........................15-1

Block Diagram...............................................................................................................................................15-2

Uart Operation......................................................................................................................................15-3

Uart Special Registers...................................................................................................................................15-10

Uart Line Control Register....................................................................................................................15-10

Uart Control Register............................................................................................................................15-11

Uart Control Register............................................................................................................................15-11

Uart FIFO Control Register...................................................................................................................15-13

Uart Modem Control Register...............................................................................................................15-14

Uart Tx/Rx Status Register...................................................................................................................15-15

Uart Error Status Register ....................................................................................................................15-16

Uart FIFO Status Register....................................................................................................................15-17

Uart Modem Status Register ................................................................................................................15-18

Uart Transmit Buffer Register (Holding Register & FIFO Register) .....................................................15-19

Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................15-19

Uart Baud Rate Divisor Register ..........................................................................................................15-20

x S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 16 USB Host Controller

Overview .......................................................................................................................................................16-1

USB Host Controller Special Registers................................................................................................16-2

Chapter 17 USB 2.0 Function

Overview .......................................................................................................................................................17-1

Feature.................................................................................................................................................17-1

Block Diagram...............................................................................................................................................17-2

To Activate USB Port1 for USB 2.0 Function ...............................................................................................17-3

USB 2.0 Function Controller Special Registers............................................................................................17-4

Registers.......................................................................................................................................................17-6

Index Register (IR)...............................................................................................................................17-6

Endpoint Interrupt Register (EIR).........................................................................................................17-7

Endpoint Interrupt Enable Register (EIER)..........................................................................................17-8

Function Address Register (FAR)........................................................................................................17-9

Frame Number Register (FNR)............................................................................................................17-10

ENdpoint Direction Register (EDR)......................................................................................................17-11

Test Register (TR)................................................................................................................................17-12

System Status Register (SSR).............................................................................................................17-13

System Control Register (SCR) ...........................................................................................................17-15

EP0 Status Register (EP0SR)..............................................................................................................17-17

EP0 Control Register (EP0CR)]...........................................................................................................17-18

Endpoint# Buffer Register (EP#BR)....................................................................................................17-19

Endpoint Status Register (EsR) ...........................................................................................................17-20

Endpoint Control Register (ECR).........................................................................................................17-22

Byte Read Count Register (BRCR)......................................................................................................17-24

Byte Write Count Register (BWCR).....................................................................................................17-25

MAX Packet register (MPR).................................................................................................................17-26

DMA Control register (DCR) ................................................................................................................17-27

DMA Transfer Counter Register (DTCR).............................................................................................17-28

DMA FIFO Counter Register (DFCR) ..................................................................................................17-29

DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)......................................................................17-30

DMA Interface Control Register (DICR)...............................................................................................17-31

Memory Base Address Register (MBAR).............................................................................................17-32

Memory Current Address Register (MCAR) ........................................................................................17-33

Burst FIFO Control Register(FCON)....................................................................................................17-33

Burst FIFO Status Register(FSTAT)....................................................................................................17-33

AHB Master(DMA) Operation Flow Chart............................................................................................17-34

S3C2443X MICROCONTROLLER xi

Table of Contents (Continued)

Chapter 18 IIC-BUS Interface

Overview........................................................................................................................................................18-1

IIC-Bus Interface...................................................................................................................................18-3

Start and Stop Conditions.....................................................................................................................18-3

Data Transfer Format ...........................................................................................................................18-4

ACK Signal Transmission.....................................................................................................................18-5

Read-Write Operation...........................................................................................................................18-6

Bus Arbitration Procedures...................................................................................................................18-6

Abort Conditions...................................................................................................................................18-6

Configuring IIC-Bus ..............................................................................................................................18-6

Flowcharts of Operations in Each Mode ..............................................................................................18-7

IIC-Bus Interface Special Registers ..............................................................................................................18-11

Multi-Master IIC-Bus Control (IICCON) Register..................................................................................18-11

Multi-Master IIC-BUS Control/Status (IICSTAT) Register....................................................................18-12

Multi-Master IIC-BUS Address (IICADD) Register...............................................................................18-13

Multi-Master IIC-BUS Transmit/Receive Data Shift (IICDS) Register..................................................18-13

Multi-Master IIC-BUS Line Control(IICLC) Register.............................................................................18-14

Chapter 19 SPI Interface

Overview........................................................................................................................................................19-1

Features....................................................................................................................... .........................19-1

Block Diagram ......................................................................................................................................19-2

SPI Operation .......................................................................................................................................19-3

Programming Procedure ......................................................................................................................19-3

SPI special registers......................................................................................................................................19-7

SPI Control Register.............................................................................................................................19-7

SPI Status Register ..............................................................................................................................19-9

SPI Pin Control Register.......................................................................................................................19-11

Chapter 20 HS_SPI Controller

Overview........................................................................................................................................................20-1

Features....................................................................................................................... .........................20-1

Block Diagram...............................................................................................................................................20-2

Signal Description .........................................................................................................................................20-3

Operation..............................................................................................................................................20-3

SPI Transfer Format......................................................................................................................................20-4

Sequence of Special Function Register........................................................................................................20-5

Register Descriptions ....................................................................................................................................20-5

xii S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 21 CSTN LCD Display Controller

Overview .......................................................................................................................................................21-1

Common Features................................................................................................................................21-2

External Interface Signal......................................................................................................................21-2

Block Diagram...............................................................................................................................................21-3

STN LCD Controller Operation.....................................................................................................................21-4

Timing Generator (TIMEGEN)..............................................................................................................21-4

Video Operation ...................................................................................................................................21-5

Dithering and Frame Rate Control.......................................................................................................21-7

Memory Data Format (STN, BSWP = 0)..............................................................................................21-9

PAD Muxing ..................................................................................................................................................21-17

LCD Controller Special Registers ........................................................................................................21-18

Chapter 22 TFT LCD

Overview .......................................................................................................................................................22-1

Top block diagram Display Controller...........................................................................................................22-2

Features ...............................................................................................................................................22-3

Functional Description ..................................................................................................................................22-4

Brief of the sub-block............................................................................................................................22-4

Data Flow .............................................................................................................................................22-4

Overview of the Color Data..................................................................................................................22-6

VD Signal Connection..........................................................................................................................22-18

Palette usage........................................................................................................................................22-20

Palette Read/Write ...............................................................................................................................22-22

Window Blending ..........................................................................................................................................22-23

Overview...............................................................................................................................................22-23

Vtime Controller Operation ...........................................................................................................................22-27

RGB Interface case..............................................................................................................................22-27

Virtual Display...............................................................................................................................................22-28

RGB Interface Spec .............................................................................................................................22-29

LCD CPU Interface (i80-system i/f)......................................................................................................22-30

Signals..................................................................................................................................................22-31

PAD Muxing..........................................................................................................................................22-32

Programmer’s Model.....................................................................................................................................22-33

Overview...............................................................................................................................................22-33

S3C2443X MICROCONTROLLER xiii

Table of Contents (Continued)

Chapter 23 CAMERA Interface

Overview........................................................................................................................................................23-1

Features....................................................................................................................... .........................23-2

External Interface ..........................................................................................................................................23-2

Signal Description.................................................................................................................................23-2

Timing Diagram ....................................................................................................................................23-3

External/Internal Connection Guide..............................................................................................................23-5

Camera Interface Operation..........................................................................................................................23-5

Two DMA ports.....................................................................................................................................23-5

Clock Domain .......................................................................................................................................23-7

Frame Memory Hirerarchy....................................................................................................................23-7

Memory Storing Method .......................................................................................................................23-9

Timing Diagram for Register Setting ....................................................................................................23-10

MSDMA Feature...................................................................................................................................23-13

Software Interface .........................................................................................................................................23-14

Camera Interface Special Registers .............................................................................................................23-14

Source Format Register........................................................................................................................23-14

Window Option Register.......................................................................................................................23-15

Global Control Register ........................................................................................................................23-17

Window Option Register 2....................................................................................................................23-18

Y1 Start Address Register....................................................................................................................23-18

Y2 Start Address Register....................................................................................................................23-18

Y3 Start Address Register....................................................................................................................23-19

Y4 Start Address Register....................................................................................................................23-19

CB1 Start Address Register .................................................................................................................23-19

Cb2 Start Address Register..................................................................................................................23-20

CB3 Start Address Register .................................................................................................................23-20

CB4 Start Address Register .................................................................................................................23-20

Cr1 Start Address Register...................................................................................................................23-20

Cr2 Start Address Register...................................................................................................................23-21

Cr3 Start Address Register...................................................................................................................23-21

Cr4 Start Address Register...................................................................................................................23-21

Codec Target Format Register.............................................................................................................23-22

Codec DMA Control Register...............................................................................................................23-24

Register Setting Guide for Codec Scaler and Preview Scaler.............................................................23-25

Codec Pre-Scaler Control Register 1...................................................................................................23-28

Codec Pre-Scaler Control Register 2...................................................................................................23-28

Codec Main-Scaler Control Register....................................................................................................23-29

Codec DMA Target Area Register........................................................................................................23-29

Codec Status Register..........................................................................................................................23-30

RGB1 Start Address Register...............................................................................................................23-30

RGB2 Start Address Register...............................................................................................................23-31

RGB3 Start Address Register...............................................................................................................23-31

RGB4 Start Address Register...............................................................................................................23-31

xiv S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 23 CAMERA Interface

Preview Target Format Register ..........................................................................................................23-32

Preview DMA Control Register ............................................................................................................23-33

Preview Pre-Scaler Control Register 1 ................................................................................................23-34

Preview Pre-Scaler Control Register 2 ................................................................................................23-34

Preview Main-Scaler Control Register.................................................................................................23-35

Preview DMA Target Area Register.....................................................................................................23-35

Preview Status Register.......................................................................................................................23-36

Image Capture Enable Register...........................................................................................................23-37

Codec Capture Sequence Register .....................................................................................................23-38

Codec Scan Line Offset Register.........................................................................................................23-39

Image Effects Register.........................................................................................................................23-40

Msdma Y Start Address Register.........................................................................................................23-41

Msdma Cb Start Address Register.......................................................................................................23-41

Msdma Cr Start Address Register .......................................................................................................23-41

Msdma Y End Address Register..........................................................................................................23-41

Msdma Cb End Address Register........................................................................................................23-42

Msdma Cr End Address Register.........................................................................................................23-42

Msdma Y Offset Register.....................................................................................................................23-42

Msdma Cb Offset Register...................................................................................................................23-43

Msdma Cr Offset Register....................................................................................................................23-43

Msdma Source Image Width Register .................................................................................................23-43

Msdma Control Register.......................................................................................................................23-45

Chapter 24 ADC & Touch Screen Interface

Overview .......................................................................................................................................................24-1

Features ...............................................................................................................................................24-1

ADC & Touch Screen Interface Operation....................................................................................................24-2

Block Diagram......................................................................................................................................24-2

Function Descriptions...........................................................................................................................24-3

ADC and Touch Screen Interface Special Registers....................................................................................24-6

ADC Control (ADCCON) Register........................................................................................................24-6

ADC Touch Screen Control (ADCTSC) Register.................................................................................24-7

ADC Start Delay (Adcdly) Register ......................................................................................................24-8

ADC Conversion Data (ADCDAT0) Register.......................................................................................24-9

ADC Conversion Data (ADCDAT1) Register.......................................................................................24-10

ADC Touch Screen Up-Down Int Check Register (Adcupdn)..............................................................24-10

ADC Channel Mux Register (ADCMUX)..............................................................................................24-11

S3C2443X MICROCONTROLLER xv

Table of Contents (Continued)

Chapter 25 IIS-BUS Interface

Overview........................................................................................................................................................25-1

Features....................................................................................................................... .........................25-1

IIS Controller Operation.................................................................................................................................25-2

Block Diagram ......................................................................................................................................25-2

Master/Slave mode...............................................................................................................................25-3

Sampling Frequency and Master Clock ...............................................................................................25-6

IIS Clock Mapping Table.......................................................................................................................25-6

IIS-BUS Interface Special Registers .............................................................................................................25-7

IIS Control Register (I2scon) ................................................................................................................25-7

IIS Mode Register (I2smod)..................................................................................................................25-9

IIS FIFO Control Register (i2sfic) .........................................................................................................25-10

IIS Prescaler Control Register (i2sfic) ..................................................................................................25-11

IIS Transmit Data Register (i2stxd) ......................................................................................................25-11

IIS Receive Data Register (i2srxd).......................................................................................................25-11

Chapter 26 AC97 Controller

Overview........................................................................................................................................................26-1

Features....................................................................................................................... .........................26-1

AC97 Controller Operation............................................................................................................................26-2

Block Diagram ......................................................................................................................................26-2

Internal Data Path.................................................................................................................................26-3

Operation Flow Chart............................................................................................................................26-4

AC-LINK Digital Interface Protocol.......................................................................................................26-5

AC-link Output Frame (SDATA_OUT)..................................................................................................26-6

AC-link Input Frame (SDATA_IN).........................................................................................................26-6

Powering Down the AC-link..................................................................................................................26-7

Waking up the AC-link - Wake up Triggered by the AC97 Controller ..................................................26-7

Cold AC97 Reset..................................................................................................................................26-8

WARM AC97 Reset..............................................................................................................................26-8

AC97 Controller Special Registers................................................................................................................26-9

AC97 Global Control Register (AC_GLBCTRL)...................................................................................26-9

AC97 Global Status Register (AC_GLBSTAT).....................................................................................26-10

AC97 CODEC Command Register (AC_CODEC_CMD).....................................................................26-10

AC97 CODEC Status Register (AC_CODEC_STAT)..........................................................................26-11

AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................26-11

AC97 MIC in Channel FIFO Address Register (AC_MICADDR) .........................................................26-12

AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)......................................................26-12

AC97 MIC in Channel FIFO Data RegisteR (AC_MICDATA) ..............................................................26-12

xvi S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 27 MMC/SD/SDIO Controller

Features........................................................................................................................................................27-1

Block Diagram...............................................................................................................................................27-1

SD Operation ................................................................................................................................................27-2

SDIO Operation.............................................................................................................................................27-3

SDI Special Registers...................................................................................................................................27-4

SDI Control Register (SDICON)...........................................................................................................27-4

SDI Baud Rate Prescaler Register (SDIPRE)......................................................................................27-4

SDI Command Argument Register (SDICmdArg)................................................................................27-5

SDI Command Control Register (SDICmdCon)...................................................................................27-5

SDI Command Status Register (SDICmdSta)......................................................................................27-6

SDI Response Register 0 (SDIRSP0)..................................................................................................27-6

SDI Response Register 1 (SDIRSP1)..................................................................................................27-6

SDI Response Register 2 (SDIRSP2)..................................................................................................27-7

SDI Response Register 3 (SDIRSP3)..................................................................................................27-7

SDI Data / Busy Timer Register (SDIDTimer)......................................................................................27-7

SDI Block Size Register (SDIBSize) ....................................................................................................27-7

SDI Data Control Register (SDIDatCon)..............................................................................................27-8

SDI Data Remain Counter Register (ADIDatCnt)................................................................................27-9

SDI Data Status Register (ADIDatSta).................................................................................................27-9

SDI Fifo Status Register (SDIFSTA)....................................................................................................27-10

SDI Interrupt Mask Register (SDIIntMsk).............................................................................................27-11

SDI Data Register (SDIDAT)................................................................................................................27-12

Chapter 28 High-Speed MMC Controller

Overview .......................................................................................................................................................28-1

Features........................................................................................................................................................28-1

Block Diagram...............................................................................................................................................28-2

SDI Special Registers...................................................................................................................................28-3

Configuration Register Types...............................................................................................................28-3

System Address Register.....................................................................................................................28-4

Block Size Register ..............................................................................................................................28-5

Block Count Register............................................................................................................................28-6

Argument Register ...............................................................................................................................28-7

Transfer mode Register........................................................................................................................28-7

Command Register ..............................................................................................................................28-9

Response Register...............................................................................................................................28-12

Buffer Data Port Register.....................................................................................................................28-13

Present State Register.........................................................................................................................28-13

Host Control Register...........................................................................................................................28-21

Power Control Register........................................................................................................................28-22

Block Gap Control Register..................................................................................................................28-23

Wakeup Control Register.....................................................................................................................28-25

S3C2443X MICROCONTROLLER xvii

Table of Contents (Concluded)

Chapter 28 High-Speed MMC Controller

Clock Control Register..........................................................................................................................28-26

Timeout Control Register......................................................................................................................28-28

Software Reset Register.......................................................................................................................28-29

Normal Interrupt Status Register..........................................................................................................28-30

Error Interrupt Status Register..............................................................................................................28-34

Normal Interrupt Status Enable Register..............................................................................................28-36

Error Interrupt Status Enable Register .................................................................................................28-38

Normal Interrupt Signal Enable Register..............................................................................................28-39

Error Interrupt Signal Enable Register..................................................................................................28-41

Autocmd12 Error Status Register.........................................................................................................28-42

Capabilities Register.............................................................................................................................28-44

Maximum Current Capabilities Register...............................................................................................28-46

Control Register 2.................................................................................................................................28-47

Control Register 3 Register ..................................................................................................................28-49

Host Controller Version Register..........................................................................................................28-50

Chapter 29 Electrical Data

Absolute Maximum Ratings...........................................................................................................................29-1

Recommended Operating Conditions...........................................................................................................29-2

D.C. Electrical Characteristics.......................................................................................................................29-4

A.C. Electrical Characteristics.......................................................................................................................29-6

Chapter 30 Mechanical Data

Package Deimensions...................................................................................................................................30-1

xviii S3C2443X MICROCONTROLLER

List of Figures

Figure Title Page
Number Number

1-1 S3C2443X Block Diagram..................................................................................................1-5

1-2 S3C2443X Pin Assignments (400-FBGA) Top view...........................................................1-6

1-3 Memory Map.......................................................................................................................1-33

2-1 System controller block diagram.........................................................................................2-2

2-2 Power-on reset sequence...................................................................................................2-4

2-3 Clock generator block diagram...........................................................................................2-6

2-4 PLL(Phase-Locked Loop) Block Diagram ..........................................................................2-8

2-5 The case that changes slow clock by setting PMS value

2-6 The clock distribution block diagram...................................................................................2-9

2-7 MPLL Based clock domain .................................................................................................2-10

2-8 EPLL Based clock domain..................................................................................................2-12

2-9 Power mode state diagram.................................................................................................2-13

2-10 Entering STOP mode and exiting STOP mode (wake-up).................................................2-15

note2

.............................................2-8

3-1 The configuration of MATRIX and Memory sub-system of S3C2443.................................3-1

5-1 SMC Block Diagram............................................................................................................5-3

5-2 SMC Core Block Diagram...................................................................................................5-3

5-3 External Memory Two Output Enable Delay State Read ...................................................5-4

5-4 Read Timing diagram (DRnCS = 1, DRnOWE = 0)............................................................5-4

5-5 Read Timing Diagram (DRnCS = 1, DRnOWE = 1)...........................................................5-5

5-6 External burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read .............5-6

5-7 External Synchronous Fixed Length Four Transfer Burst Read.........................................5-7

5-8 External Memory Two Write Enable Delay State Write......................................................5-8

5-9 Write Timing Diagram (DRnCS = 1, DRnOWE = 0) ...........................................................5-9

5-10 Write Timing Diagram (DRnCS = 1, DRnOWE = 1) ...........................................................5-9

5-11 Synchronous Two Wait State Write....................................................................................5-10

5-12 Read, then wo Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)............5-11

5-13 Memory Interface with 8-bit SRAM (512KB).......................................................................5-12

5-14 Memory Interface with 16-bit SRAM (1MB)........................................................................5-12

6-1 Mobile DRAM Controller Block Diagram.............................................................................6-2

6-2 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ....................................................6-4

6-3 Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks)...........................................6-4

6-4 Memory Interface with 16-bit Mobile DDR..........................................................................6-5

7-1 NAND Flash Controller Block Diagram...............................................................................7-2

7-2 NAND Flash Controller Boot Loader Block Diagram..........................................................7-2

7-3 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0)................................................7-4

7-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0).................................................................7-4

7-5 NAND Flash Memory Mapping...........................................................................................7-10

7-6 A 8-bit NAND Flash Memory Interface ...............................................................................7-11

7-7 Two 8-bit NAND Flash Memory Interface...........................................................................7-11

7-8 A 16-bit NAND Flash Memory Interface .............................................................................7-11

S3C2443X MICROCONTROLLER xix

List of Figures (Continued)

Figure Title Page
Number Number

8-1 CF Controller Top Block Diagram.......................................................................................8-3

8-2 PC Card Controller Top Block Diagram..............................................................................8-4

8-3 ATA Controller Top Block Diagram.....................................................................................8-5

8-4 PC Card State Definition.....................................................................................................8-6

8-5 PIO Mode Waveform...........................................................................................................8-7

8-6 UDMA - In operation (terminated by device).......................................................................8-8

8-7 UDMA - In Operation (terminated by host)..........................................................................8-8

8-8 UDMA - Out Operation (terminated by device)...................................................................8-9

8-9 UDMA - Out Operation (terminated by host).......................................................................8-9

8-10 Memory Map Diagram.........................................................................................................8-11

9-1 Basic DMA Timing Diagram................................................................................................9-4

9-2 Demand/Handshake Mode Comparison.............................................................................9-5

9-3 Burst 4 Transfer size...........................................................................................................9-6

9-4 Single service, Demand Mode, Single Transfer Size..........................................................9-7

9-5 Single service, Handshake Mode, Single Transfer Size.....................................................9-7

9-6 Whole service, Handshake Mode, Single Transfer Size.....................................................9-7

10-1 Interrupt Process Diagram ..................................................................................................10-1

10-2 Priority Generating Block.....................................................................................................10-4

12-1 Watchdog Timer Block Diagram .........................................................................................12-2

13-1 16-bit PWM Timer Block Diagram.......................................................................................13-2

13-2 Timer Operations.................................................................................................................13-3

13-3 Example of Double Buffering Function................................................................................13-4

13-4 Example of a Timer Operation ............................................................................................13-6

13-5 Example of PWM.................................................................................................................13-7

13-6 Inverter On/Off.....................................................................................................................13-8

13-7 The Wave Form When a Dead Zone Feature is Enabled...................................................13-9

13-8 Timer4 DMA Mode Operation .............................................................................................13-10

14-1 Real Time Clock Block Diagram .........................................................................................14-2

14-2 RTC tick interrupt clock scheme .........................................................................................14-5

14-3 Main Oscillator Circuit Example..........................................................................................14-5

15-1 UART Block Diagram (with FIFO).......................................................................................15-2

15-2 UART AFC interface............................................................................................................15-4

15-3 Example showing UART Receiving 5 Characters with 2 Errors.........................................15-6

15-4 IrDA Function Block Diagram..............................................................................................15-8

15-5 Serial I/O Frame Timing Diagram (Normal UART) .............................................................15-9

15-6 Infrared Transmit Mode Frame Timing Diagram.................................................................15-9

15-7 Infrared Receive Mode Frame Timing Diagram..................................................................15-9

15-8 nCTS and Delta CTS Timing Diagram................................................................................15-18

xx S3C2443X MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

16-1 USB Host Controller Block Diagram...................................................................................16-1

17-1 USB2.0 Block Diagram.......................................................................................................17-2

17-2 USB2.0 Function Block Diagram ........................................................................................17-3

17-3 OUT Transfer Operation Flow ............................................................................................17-34

17-4 IN Transfer Operation Flow.................................................................................................17-35

18-1 IIC-Bus Block Diagram........................................................................................................18-2

18-2 Start and Stop Condition.....................................................................................................18-3

18-3 IIC-Bus Interface Data Format............................................................................................18-4

18-4 Data Transfer on the IIC-Bus..............................................................................................18-5

18-5 Acknowledge on the IIC-Bus...............................................................................................18-5

18-6 Operations for Master/Transmitter Mode............................................................................18-7

18-7 Operations for Master/Receiver Mode................................................................................18-8

18-8 Operations for Slave/Transmitter Mode..............................................................................18-9

18-9 Operations for Slave/Receiver Mode..................................................................................18-10

19-1 SPI Block Diagram..............................................................................................................19-2

19-2 SPI Transfer Format ...........................................................................................................19-4

19-3 SPI Slave Rx mode with Format B (1-Byte Buffer mode)...................................................19-6

20-1 HS-SPI Interface block diagram .........................................................................................20-2

20-2 HS-SPI Transfer Format.....................................................................................................20-4

21-1 LCD Controller Block Diagram............................................................................................21-3

21-2 Monochrome Display Types (STN).....................................................................................21-12

21-3 Color Display Types (STN).................................................................................................21-13

21-4 8-bit Single Scan Display Type STN LCD Timing ..............................................................21-15

21-7 Example of Scrolling in Virtual Display (Single Scan) ........................................................21-16

22-1 Top block diagram Display Controller.................................................................................22-2

22-2 Block diagram of the Data Flow..........................................................................................22-5

22-3 16BPP(5:6:5) Display Types...............................................................................................22-22

22-4 Blending Diagram ...............................................................................................................22-25

22-5 Color-key function configurations .......................................................................................22-26

22-6 Example of Scrolling in Virtual Display ...............................................................................22-28

22-7 LCD RGB interface Timing .................................................................................................22-29

22-8 WRITE Cycle Timing...........................................................................................................22-30

S3C2443X MICROCONTROLLER xxi

List of Figures (Continued)

Figure Title Page
Number Number

23-1 Camera interface overview .................................................................................................23-1

23-2 ITU-R BT 601 Input timing diagram ....................................................................................23-3

23-3 ITU-R BT 656 Input timing diagram ....................................................................................23-3

23-4 Sync signal timing diagram .................................................................................................23-4

23-5 IO connection guide ............................................................................................................23-5

23-6 Two DMA ports....................................................................................................................23-6

23-7 CAMIF clock generation......................................................................................................23-7

23-8 Ping-pong Memory Hierarchy .............................................................................................23-8

23-9 Memory storing style...........................................................................................................23-9

23-10 Timing diagram for register setting......................................................................................23-11

23-11 iming diagram for last IRQ...................................................................................................23-13

23-12 MSDMA or External Camera interface (only CAMIFpreview path).....................................23-13

23-13 Window offset scheme (WinHorOfst2 & WinVerOfst2 are assigned in the

CIWDOFST2 register).........................................................................................................23-15

23-14 Interrupt generation scheme ...............................................................................................23-17

23-16 Scaling scheme...................................................................................................................23-26

23-17 Preview image mirror and rotation......................................................................................23-32

23-18 Capture codec dma frame control.......................................................................................23-38

23-19 Scan line offset....................................................................................................................23-39

23-20 Image effect result...............................................................................................................23-40

23-21 ENVID_MS SFR setting when DMA start to read memory data.........................................23-46

23-22 SFR & Operation (related each DMA when selected MSDMA input path).........................23-46

24-1 ADC and Touch Screen Interface Block Diagram...............................................................24-2

24-2 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode................................24-5

25-1 IIS-Bus Block Diagram........................................................................................................25-2

25-2 IIS Clock Control Block Diragram........................................................................................25-3

25-3 IIS Audio Serial Data Formats.............................................................................................25-5

26-1 AC97 Block Diagram...........................................................................................................26-2

26-2 Internal Data Path ...............................................................................................................26-3

26-3 AC97 Operation Flow Chart................................................................................................26-4

26-4 Bi-directional AC-link Frame with Slot Assignments...........................................................26-5

26-5 AC-link Output Frame..........................................................................................................26-6

26-6 AC-link Input Frame ............................................................................................................26-6

26-7 AC97 Powerdown Timing....................................................................................................26-7

26-8 AC97 Power down/Power up Flow......................................................................................26-8

27-1 SD Interface block diagram.................................................................................................27-1

xxii S3C2443X MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

28-1 HSMMC block diagram.......................................................................................................28-2

28-2 Card Detect State ...............................................................................................................28-18

28-3 Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer..........28-19

28-4 Timing of Command Inhibit (DAT) for the case of response with busy..............................28-19

28-5 Timing of Command Inhibit (CMD) for the case of no response command .......................28-19

29-1 XTIpll Clock Timing.............................................................................................................29-6

29-2 EXTCLK Clock Input Timing...............................................................................................29-6

29-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL ..........................................29-6

29-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used .........................................................29-7

29-5 Manual Reset Input Timing.................................................................................................29-7

29-6 Power-On Oscillation Setting Timing..................................................................................29-8

29-7 Sleep Mode Return Oscillation Setting Timing...................................................................29-9

29-8 SMC Synchronous Read Timing ........................................................................................29-10

29-9 SMC Asynchronous Read Timing.......................................................................................29-10

29-10 SMC Asynchronous Write Timing.......................................................................................29-11

29-11 SMC Synchronous Write Timing.........................................................................................29-11

29-12 SMC Wait Timing................................................................................................................29-12

29-13 Nand Flash Timing..............................................................................................................29-13

29-14 SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit).........................29-14

29-15 SDRAM MRS Timing ..........................................................................................................29-15

29-16 SDRAM Auto Refresh Timing (Trp = 2, Trc = 4).................................................................29-16

29-17 External DMA Timing (Handshake, Single transfer)...........................................................29-17

29-18 TFT LCD Controller Timing.................................................................................................29-17

29-19 IIS Interface Timing (I2S Master Mode Only) .....................................................................29-18

29-20 IIS Interface Timing (I2S Slave Mode Only) .......................................................................29-18

29-21 IIC Interface Timing.............................................................................................................29-18

29-22 SD/MMC Interface Timing...................................................................................................29-19

29-23 SPI Interface Timing (CPHA = 1, CPOL = 1)......................................................................29-20

29-24 High Speed SPI Interface Timing (CPHA = 0, CPOL = 0)..................................................29-20

29-25 USB Timing (Data signal rise/fall time)...............................................................................29-21

29-26 High Speed SDMMC Interface Timing................................................................................29-21

30-1 400-FBGA-1313 Package Dimension 1(Top View)............................................................30-1

30-2 400-FBGA-1313 Package Dimension 1(Bottom View).......................................................30-2

S3C2443X MICROCONTROLLER xxiii

List of Tables

Table Title Page
Number Number

1-1 400-Pin FBGA Pin Assignments – Pin Number Order (1/4) ...............................................1-7

1-2 S3C2443X 400-Pin FBGA Pin Assignments (Sheet 1 of 12,TBD) .....................................1-11

1-3 S3C2443X Signal Descriptions...........................................................................................1-26

1-4 S3C2443X Operation Mode Description.............................................................................1-32

1-5 S3C2443X Special Registers..............................................................................................1-35

2-1 Registers & GPIO status in RESET (R: reset, S: sustain previous value)..........................2-5

2-2 Clock source selection for the main PLL and clock generation logic

2-3 Clock source selection for the EPLL...................................................................................2-7

2-4 Clock division ratio of MPLL region.....................................................................................2-10

2-5 ECLK Control ......................................................................................................................2-12

2-6 The status of PLL and ARMCLK after wake-up..................................................................2-16

2-7 Power saving mode entering/exiting condition....................................................................2-17

2-8 System Controller Address Map .........................................................................................2-18

8-1 Timing Parameter Each PIO Mode.....................................................................................8-7

8-2 Timing Parameter Each UDMA Mode.................................................................................8-10

8-3 Memory Map Table .............................................................................................................8-12

9-1 DMA request sources for each channel..............................................................................9-2

11-1 S3C2443X Port Configuration.............................................................................................11-2

15-1 Interrupts in Connection with FIFO .....................................................................................15-5

15-2 Recommended value table of DIVSLOTn register..............................................................15-20

16-1 OHCI Registers for USB Host Controller ............................................................................16-2

17-1 Non-Indexed Registers........................................................................................................17-4

17-2 Indexed Registers ...............................................................................................................17-5

20-1 External signals description ................................................................................................20-3

21-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60MHz)..........................................21-5

21-2 Dither Duty Cycle Examples................................................................................................21-7

21-3 LCDCNTL (STN) / DISPCON (TFT) Port Muxing Table.....................................................21-17

21-4 MV Value for Each Display Mode .......................................................................................21-29

22-1 25(A:8:8:8) Palette Data Format .........................................................................................22-20

22-2 19BPP (A:6:6:6) Palette Data Format.................................................................................22-21

22-3 16BPP(A:5:5:5) Palette Data Format..................................................................................22-21

22-4 Relation between VCLK and CLKVAL (TFT, Freq. of Video Clock Source=60MHz).........22-27

22-5 LCD RGB I/F signals...........................................................................................................22-31

22-6 CPU I/F (i80-System Interface)...........................................................................................22-31

22-7 LCDCNTL (STN) / DISPCON (TFT) Port Muxing Table.....................................................22-32

note1

............................2-6

xxiv S3C2443X MICROCONTROLLER

List of Tables (Continued)

Table Title Page
Number Number

23-1 Camera interface signal description ...................................................................................23-2

23-2 Video timing reference codes of ITU-656 format................................................................23-4

23-3 Sync signal timing requirement...........................................................................................23-4

25-1 CODEC clock (CODECLK = 256, 384, 512 or 768fs) ........................................................25-6

25-2 IIS clock mapping table.......................................................................................................25-6

28-1 Determination of Transfer Type..........................................................................................28-8

28-2 Relation Between Parameters and the Name of Response Type......................................28-11

28-3 Response Bit Definition for Each Response Type..............................................................28-12

28-4 The relation between Command CRC Error and Command Timeout Error.......................28-34

28-5 The relation between Command CRC Error and Command Timeout Error.......................28-42

28-6 Maximum Current Value Definition.....................................................................................28-45

29-1 Absolute Maximum Rating..................................................................................................29-1

29-2 Recommended Operating Conditions.................................................................................29-2

29-3 Normal I/O PAD DC Electrical Characteristics ...................................................................29-4

29-4 Special Memory DDR I/O PAD DC Electrical Characteristics............................................29-5

29-5 USB DC Electrical Characteristics......................................................................................29-5

29-6 RTC OSC DC Electrical Characteristics.............................................................................29-5

29-12 Clock Timing Constants......................................................................................................29-22

29-13 SSMC Timing Constants.....................................................................................................29-23

29-14 NFCON Bus Timing Constants...........................................................................................29-23

29-15 Memory Interface Timing Constants (SDRAM) ..................................................................29-24

29-16 DMA Controller Module Signal Timing Constants ..............................................................29-25

29-17 TFT LCD Controller Module Signal Timing Constants .......................................................29-25

29-18 IIS Controller Module Signal Timing Constants(I2S Master Mode Only) ...........................29-25

29-19 IIS Controller Module Signal Timing Constants(I2S Slave Mode Only) .............................29-26

29-20 IIC BUS Controller Module Signal Timing...........................................................................29-26

29-21 SD/MMC Interface Transmit/Receive Timing Constants....................................................29-27

29-22 SPI Interface Transmit/Receive Timing Constants.............................................................29-27

29-23 High Speed SPI Interface Transmit/Receive Timing Constants.........................................29-27

29-24 USB Electrical Specifications..............................................................................................29-28

29-25 USB Full Speed Output Buffer Electrical Characteristics ...................................................29-29

29-26 USB High Speed Output Buffer Electrical Characteristics..................................................29-29

29-27 High Speed SDMMC Interface Transmit/Receive Timing Constants.................................29-29

S3C2443X MICROCONTROLLER xxv

NOTES

xxvi S3C2443X MICROCONTROLLER

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2443X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2443X
is designed to provide hand-held devices and general applications with low-power, and high-performance micro­controller solution in small die size. To reduce total system cost, the S3C2443X includes the following
components.

The S3C2443X is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low­power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2443X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2443X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in
this document include:

• Around 400MHz @ 1.3V, 533MHz @ 1.375V Core, 1.8V/2.5V/3.3V ROM/SRAM, 1.8V/2.5V/3.3V SDRAM,

3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU

• External memory controller (SDRAM Control and Chip Select logic) and CF/ATA I/F controller

• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA

• 6-ch DMA controllers with external request pins

• 4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 2-ch SPls (1-ch High Speed SPI)

• IIC bus interface (multi-master support)

• IIS Audio CODEC interface & AC97 CODEC Interface

• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible

• High-Speed MMC Protocol version 4.0 compatible

• 2-ch USB Host controller (ver 1.1 Complaint)/1-ch USB Device controller (ver 2.0 Complaint)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 10-ch 10-bit ADC and Touch screen interface

• RTC with calendar function

• Camera interface (Max. 8M pixels input support. 2M pixel input support for scaling)

• 147 General Purpose I/O ports / 24-ch external interrupt source

• Power control: Normal, Idle, Stop and Sleep mode

• On-chip clock generator with PLL

1-1

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

FEATURES

Architecture

• Integrated system for hand-held devices and
general embedded applications.

• 16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core.

• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.

• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.

• ARM920T CPU core supports the ARM debug
architecture.

• Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).

System Manager

• Little/Big Endian support.

• Two independent memory bus - one for the

ROM/SRAM bus (ROM Bank0~Bank5) and one
for the DRAM bus (SDRAM Bank0~Bank1)

• Address space: 64M bytes for Rom bank0 ~
bank5, 128M bytes for SDRAM bank0 ~ bank1.

• Supports programmable 8/16-bit data bus width
for ROM/SRAM bank and programmable 16/32­bit data bus width for DRAM bank

• Fixed bank start address from Rom bank 0 to
bank 5 and SDRAM bank 0 to bank1.

• Eight memory banks:

– Six memory banks for ROM, SRAM, and

others (NAND/CF etc.).

– Two memory banks for Synchronous DRAM.

• Complete Programmable access cycles for all
memory banks.

NAND Flash Boot Loader

• Supports booting from NAND flash memory.
(Only 8bit boot support)

• 4KB internal buffer for booting.

• Supports storage memory for NAND flash

memory after booting.

• Supports Advanced NAND flash

Cache Memory

• 64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).

• 8words length per line with one valid bit and two
dirty bits per line.

• Pseudo random or round robin replacement
algorithm.

• Write-through or write-back cache operation to
update the main memory.

• The write buffer can hold 16 words of data and
four addresses.

Clock & Power Manager

• On-chip MPLL and EPLL:
EPLL generates the clock to operate USB Host,
IIS, UART, etc.
MPLL generates the clock to operate MCU at
maximum 533Mhz @ 1.375V.

• Clock can be fed selectively to each function
block by software.

• Power mode: Normal, Idle, STOP and Sleep
mode
Normal mode: Normal operating mode
Idle mode: The clock for only CPU is stopped.
STOP mode: All clocks are stopped.
Sleep mode: The Core power including all
peripherals is shut down.

• Supports external wait signals to expand the bus
cycle.

• Supports self-refresh mode in SDRAM for

• Woken up by EINT[15:0] or RTC alarm & tick

interrupt from Sleep mode and STOP mode.

power-down.

• Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, OneNAND and
others).

1-2

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

FEATURES (Continued)

Interrupt Controller

• 69 Interrupt sources
(One Watch dog timer, 5 timers, 12 UARTs, 24
external interrupts, 6 DMA, 2 RTC, 2 ADC, 1 IIC,
2 SPI, 2 SDI, 2 USB, 4 LCD, 1 Battery Fault, 1
NAND, 1 CF, 1 AC97 and 2 CAM I/F)

• Level/Edge mode on external interrupt source

• Programmable polarity of edge and level

• Supports Fast Interrupt request (FIQ) for very

urgent interrupt request

Timer with Pulse Width Modulation (PWM)

• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based
operation

• Programmable duty cycle, frequency, and
polarity

• Dead-zone generation

• Supports external clock sources

RTC (Real Time Clock)

• Full clock feature: msec, second, minute, hour,
date, day, month, and year

• 32.768 KHz operation

• Alarm interrupt

• Time tick interrupt

LCD Controller STN LCD Displays Feature

• Supports 3 types of STN LCD panels: 4-bit dual
scan, 4-bit single scan, 8-bit single scan display
type

• Supports monochrome mode, 4 gray levels, 16
gray levels, 256 colors and 4096 colors for STN
LCD

• Supports multiple screen size
– Typical actual screen size: 640x480,

320x240,
160x160, and others.
– Maximum frame buffer size is 4 Mbytes.
– Maximum virtual screen size in 256 color
mode: 4096x1024, 2048x2048, 1024x4096
and others

TFT(Thin Film Transistor) Color Displays Feature

• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette
color displays for color TFT

• Supports 16, 24 bpp non-palette true-color
displays for color TFT

• Supports maximum 16M color TFT at 24 bpp
mode

• Supports multiple screen size
– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4Mbytes.
– Maximum virtual screen size in 64K color
mode: 2048x2048, and others

General Purpose Input/Output Ports

• 24 external interrupt ports

• 147 Multiplexed input/output ports

DMA Controller

• 6-ch DMA controller

• Supports memory to memory, IO to memory,

memory to IO, and IO to IO transfers

• Burst transfer mode to enhance the transfer rate

1-3

• Support 2 overlay windows for TFT

UART

• 4-channel UART with DMA-based or interrupt-
based operation

• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive (Tx/Rx)

• Supports external clocks for the UART operation
(UEXTCLK)

• Programmable baud rate

• Supports IrDA 1.0

• Loopback mode for testing

• Each channel has internal 64-byte Tx FIFO and

64-byte Rx FIFO.

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

FEATURES (Continued)

A/D Converter & Touch Screen Interface

• 10-ch multiplexed ADC

• Max. 500KSPS and 10-bit Resolution

• Internal FET for direct Touch screen interface

Watchdog Timer

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

IIC-Bus Interface

• 1-ch Multi-Master IIC-Bus

• Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.

IIS-Bus Interface

• 1-ch IIS-bus for audio interface with DMA-based
operation

• Serial, 8-/16-bit per channel data transfers

• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx

• Supports IIS format and MSB-justified data

format

AC97 Audio Interface

• 1-ch AC97 for audio interface with DMA-based
operation

• 16-bit Stereo Audio

USB Host

• 2-port USB Host

• Complies with OHCI Rev. 1.0

• Compatible with USB Specification version 1.1

USB Device

• 1-port USB Device

• 9 Endpoints for USB Device

• Compatible with USB Specification version 2.0

SD/MMC Host Interface

• Normal, Interrupt and DMA data transfer mode
(byte, halfword, word transfer)

• DMA burst4 access support (only word transfer)

• Compatible with SD Memory Card Protocol

version 1.0

• Compatible with SDIO Card Protocol version 1.0

• 64 Bytes FIFO for Tx/Rx

• One Compatible with Multimedia Card Protocol

version 2.11, the other with version 4.0 (HS­MMC)

SPI Interface

• Compatible with 2-ch Serial Peripheral Interface
Protocol version 2.11 (1ch. High speed SPI
interface)

• 2x8 bits Shift register for Tx/Rx

• DMA-based or interrupt-based operation

Camera Interface

• ITU-R BT 601/656 8-bit mode support

• DZI (Digital Zoom In) capability

• Programmable polarity of video sync signals

• Max. 16M pixels input support (8M pixel input

support for scaling)

• Image mirror and rotation (X-axis mirror, Y-axis
mirror, and 180° rotation)

• Camera output format (RGB 16/24-bit and
YCbCr 4:2:0/4:2:2 format)

Operating Voltage Range

• Core: 1.3 V for 400MHz

1.375 V for 533MHz
ROM/SRAM: 1.8V/ 2.5V/3.0V/3.3V

SDRAM: 1.8V/ 2.5V/ 3.3V

• I/O: 1.8V/2.5V/3.3V(refer to electrical data)

Operating Frequency

• Fclk Up to 533MHz

• Hclk Up to 133MHz

• Pclk Up to 67MHz

Package

• 400 FBGA 13x13

1-4

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

BLOCK DIAGRAM

ARM920T

Trace

interface

Port

Interrupt Cont.

Power Management

External Master SMC

External

coprocessor

interface

JTAG

Instruction

Cache

(16KB)

R13

IVA[31:0]

ARM9TDMI

Processor core

(Internal Embedded ICE)
DVA[31:0]

R13

Data Cache

(16KB)

DD[31:0]

DMVA[31:0]

Multi-AHB Bus

Instruction

IMVA[31:0]

ID[31:0]

Data

MMU

DINDEX[31:0]

USB Device 2.0

MMU

CP15

USB Host 1.1

IPA[31:0]

Write

Buffer

DPA[31:0]

Write Back

PA TAG RAM

AMBA

bus

interface

WBPA[31:0]

ASB

TFT LCD Controller

CSTN LCD Controller

Camera Interface

HS-MMC

UART 0,1,2,3

SD/MMC

Watchdog Timer

I2C

PWM 0,1,2,3

Timer 4

Figure 1-1. S3C2443X Block Diagram

Bridge & DMA ( 6 Ch)

APB Bus

CF

NFCON

DRAMC

SPI 0,1(SPI0 => HSSPI)

I2S

GPIO

RTC

TSADC

EBI

Memory
Port 0

Memory
Port 1

1-5

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

23

22

21

20

19

18

17

16

15

14

121311

10

9

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC

Bottom View

Figure 1-2. S3C2443X Pin Assignments (400-FBGA) Top view

1-6

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 400-Pin FBGA Pin Assignments – Pin Number Order (1/4)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

1 VDD_SRAM C3 35 RDATA2 K3 69 VSSiarm R1
2 RSMCLK/GPA13 B2 36 RDATA1 K8 70 VD1/GPC9 P7
3 VSS_SRAM D4 37 RDATA0 J1 71 VSS_LCD R2
4 RSMVAD/GPA14 C2 38 CAMVSYNC/GPJ9 K7 72 VDD_LCD P8
5 RSMBWAIT/GPM0 B1 39 CAMHREF/GPJ10 K2 73 VD2/GPC10 T1
6 nRCS3 C1 40 VSSi L4 74 VD3/GPC11 P9
7 nRCS4 C4 41 VDDi L3 75 VD4/GPC12 R3
8 nRCS5/GPA12 E4 42 CAMPCLK/GPJ8 K9 76 VD5/GPC13 T2

9 nWAIT D2 43 CAMDATA0/GPJ0 K1 77 VD6/GPC14 T3
10 FCLE F3 44 CAMDATA1/GPJ1 L8 78 VD7/GPC15 R7
11 FALE D3 45 CAMDATA2/GPJ2 L2 79 VD8/GPD0 U1
12 VDDi D1 46 CAMDATA3/GPJ3 L7 80 VD9/GPD1 R8
13 VSSi E2 47 VDD_CAM M4 81 VDDiarm U4
14 nFWE G4 48 VSS_CAM L1 82 VSSiarm U2
15 nFRE E1 49 CAMDATA4/GPJ4 M2 83 VD10/GPD2 V1
16 nFCE F4 50 CAMDATA5/GPJ5 L9 84 VD11/GPD3 T7
17 FRnB/GPM1 F2 51 CAMDATA6/GPJ6 M3 85 VD12/GPD4 U3
18 VDD_SRAM F1 52 CAMDATA7/GPJ7 M8 86 VD13/GPD5 T8
19 VSS_SRAM E3 53 VDDiarm M1 87 VD14/GPD6 V2
20 RDATA15 H4 54 VSSiarm N4 88 VD15/GPD7 V3
21 RDATA14 G2 55 CAMPCLKOUT/GPJ11 N3 89 VD16/GPD8 W1
22 RDATA13 G3 56 CAMRESET/GPJ12 M7 90 VD17/GPD9 W3
23 RDATA12 G1 57 LEND/GPC0 N1 91 VD18/GPD10 W2
24 RDATA11 H7 58 VDDiarm P4 92 VDDiarm V4
25 RDATA10 H2 59 VSSiarm N2 93 VDDiarm Y1
26 RDATA9 J8 60 VCLK/GPC1 M9 94 VSSiarm Y2
27 RDATA8 H3 61 VLINE/GPC2 R4 95 VDD_LCD W4
28 RDATA7 J4 62 VM/GPC4 N7 96 VSS_LCD AA1
29 RDATA6 J3 63 VFRAME/GPC3 P3 97 VD19/GPD11 Y3
30 RDATA5 H1 64 LCDVF0/GPC5 N8 98 VD20/GPD12 Y4
31 VDD_SRAM J2 65 LCDVF1/GPC6 P1 99 VD21/GPD13 AB1
32 VSS_SRAM J9 66 LCDVF2/GPC7 N9 100 VD22/GPD14 AB2
33 RDATA4 K4 67 VD0/GPC8 P2 101 VD23/GPD15 AA2
34 RDATA3 J7 68 VDDiarm T4 102 TOUT0/GPB0 AC1

1-7

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-1. 400-Pin FBGA Pin Assignments – Pin Number Order (2/4)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

103 TOUT1/GPB1 AC2 137 VSS_OP2 Y9 171 VSSi Y15
104 TOUT2/GPB2 AB3 138

105 TOUT3/GPB3 AA3 139
106 VDDiarm AC3 140
107 VSSiarm AB4 141

EINT20/GPG12/
EINT21/GPG13/
EINT22/GPG14/
EINT23/GPG15/

nINPACK

nREG_CF

RESET_CF

CF_PWREN

R10 172 VDDi T15

AC10 173 SD0_CMD/GPL8 AB15

T11 174 SD0_DAT[0]/GPL0 AC16

AA10 175 SD0_DAT[1]/GPL1 AA15

108 TCLK/GPB4 AA4 142 VDDiarm AB11 176 SD0_DAT[2]/GPL2 U15
109 nXBACK/GPB5 AC4 143 VSSiarm Y10 177 SD0_DAT[3]/GPL3 AA16
110 nXBREQ/GPB6 Y5 144 IICSCL/GPE14 U11 178 SD0_DAT[4]/GPL4 R15
111 VDD_OP2 AB5 145 IICSDA/GPE15 AC11 179 SD0_DAT[5]/GPL5 AB16

112 VSS_OP2 U7 146
113 nXDACK1/GPB7 AC5 147
114 nXDREQ1/GPB8 AA5 148
115 nXDACK0/GPB9 AB6 149
116 nXDREQ0/GPB10 U8 150

I2SLRCK/GPE0/

AC_nRESET

I2SSCLK/GPE1/

AC_SYNC

I2SCDCLK/GPE2/

AC_BIT_CLK

I2SSDI/GPE3/

AC_SDI

I2SSDO/GPE4/

AC_SDO

117 VDDiarm Y6 151 SPIMISO0/GPE11 AC12 185
118 VSSiarm Y7 152 SPIMOSI0/GPE12 U12 186
119

EXTUARTCLK/

GPH12

AC6 153 SPICLK0/GPE13 AB12 187
120 nCTS0/GPH8 AB7 154 VDDi Y12 188
121 nRTS0/GPH9 AA6 155 VSSi Y13 189

AA11 180 SD0_DAT[6]/GPL6 U16

Y11 181 SD0_DAT[7]/GPL7 AC17

R11 182 VDD_SD AA17

AA12 183 VSS_SD AB17

T12 184

SD1_CLK/GPE5/

AC_BIT_CLK

SD1_CMD/GPE6/

AC_SDI

SD1_DAT[0]/GPE7

/AC_SDO

SD1_DAT[1]/GPE8

/AC_SYNC

SD1_DAT[2]/GPE9

/AC_nRESET
SD1_DAT[3]/

GPE10

Y16

AC18

Y17
AB18
AA18
AC19

122 TXD0/GPH0 AC7 156 VSS_SD R12 190 VSSA_MPLL AB19
123 RXD0/GPH1 AA7 157 VDD_SD AC13 191 MPLLCAP Y18
124 nCTS1/GPH10 T9 158 TXD2/GPH4 T13 192 VDDA_MPLL AC20
125 nRTS1/GPH11 AB8 159 RXD2/GPH5 AB13 193 VSSA_EPLL AC21
126 TXD1/GPH2 U9 160 TXD3/GPH6/nRTS2 U13 194 EPLLCAP AC22
127 RXD1/GPH3 AA8 161 RXD3/GPH7/nCTS2 AA13 195 VDDA_EPLL AA19
128 EINT16/GPG8 R9 162 SS[1]/GPL14 R13 196 VSSA_ADC AB20
129 EINT17/GPG9 AB9 163 SS[0]/GPL13 AC14 197 AIN9 AA20
130 VDDiarm AC8 164 SPIMISO1/GPL12 Y14 198 AIN8 Y19
131 VSSiarm Y8 165 SPIMOSI1/GPL11 AB14 199 AIN7 AC23
132 EINT18/GPG10 T10 166 SPICLK1/GPL10 T14 200 AIN6 AB21

133

EINT19/GPG11/

nIREQ_CF

AA9 167 SD0_nWP/GPJ15 AC15 201 AIN5 AB22

134 VDD_OP2 U10 168 SD0_nCD/GPJ14 U14 202 AIN4 AA22
135 CLKOUT0/GPH13 AC9 169 SD0_LED/GPJ13 AA14 203 AIN3 AB23
136 CLKOUT1/GPH14 AB10 170 SD0_CLK/GPL9 R14 204 AIN2 AA21

1-8

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 400-Pin FBGA Pin Assignments – Pin Number Order (3/4)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

205 AIN1 AA23 239 TDI P17 273 SDATA30 K15
206 AIN0 Y22 240 TCK P20 274 SDATA29 H23
207 Vref W20 241 nTRST N15 275 SDATA28 J17
208 VDDA_ADC Y21 242 EINT8/GPG0 N22 276 VDD_SDRAM H20
209 VDD_RTC Y23 243 EINT9/GPG1 N16 277 VSS_SDRAM J16
210 Xtortc V20 244 EINT10/GPG2 N23 278 SDATA27 H22
211 Xtirtc W22 245 EINT11/GPG3 P21 279 SDATA26 H21

212 OM[4] Y20 246

EINT12/GPG4/

LCD_PWREN

N20 280 VDDi G23

213 OM[3] U17 247 EINT13/GPG5 N17 281 VSSi H17
214 OM[2] W23 248 EINT14/GPG6 N21 282 SDATA25 G21
215 OM[1] V23 249 EINT15/GPG7 M15 283 SDATA24 F21
216 OM[0] V22 250 VDD_OP1 M20 284 SDATA23 G22
217 VDDi T16 251 DP M23 285 SDATA22 F23
218 VSSi W21 252 DN L23 286 SDATA21 E23
219 VSS_OP1 T17 253 VSS_OP1 M21 287 VDD_SDRAM E20
220 EXTCLK V21 254 nRSTOUT M16 288 VSS_SDRAM F22
221 VDD_OP1 U22 255 VDDalive M22 289 SDATA20 F20
222 VDDalive U20 256 VSSalive M17 290 SDATA19 E21
223 XTIpll R16 257 VDDalive L20 291 SDATA18 G20
224 XTOpll U23 258 XI_UDEV L21 292 SDATA17 D23
225 VSSalive U21 259 XO_UDEV L15 293 SDATA16 E22
226 EINT0/GPF0 T22 260 VSSA33C L22 294 SDATA15 D21
227 EINT1/GPF1 T20 261 VDDA33C L16 295 SDATA14 C23
228 EINT2/GPF2 R17 262 REXT K23 296 VDD_SDRAM C22
229 EINT3/GPF3 T23 263 VDDA33T1 K20 297 VSS_SDRAM D22
230 EINT4/GPF4 P15 264 VSSA33T2 K22 298 SDATA13 B23
231 EINT5/GPF5 R22 265 DM_UDEV L17 299 SDATA12 A23
232 EINT6/GPF6 P16 266 VSSA33T2 K21 300 SDATA11 C21
233 EINT7/GPF7 T21 267 DP_UDEV K17 301 SDATA10 B22
234 PWR_EN R23 268 VSSA33T2 J20 302 SDATA9 B21
235 BATT_FLT R20 269 VDDA33T1 K16 303 SDATA8 B20
236 NRESET P22 270 VDDI_UDEV J23 304 SDATA7 A22
237 TDO P23 271 VSSI_UDEV J21 305 SDATA6 A21
238 TMS R21 272 SDATA31 J22 306 SDATA5 D20

1-9

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-1. 400-Pin FBGA Pin Assignments – Pin Number Order (4/4)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

307 VDD_SDRAM C20 341 SADDR3 D15 375 RADDR14 B9
308 VSS_SDRAM D19 342 SADDR4 B13 376 RADDR13 D8
309 SDATA4 A20 343 VDD_SDRAM C13 377 RADDR12 A8
310 SDATA3 B19 344 VSS_SDRAM J13 378 RADDR11 C8
311 VSSi C19 345 SADDR5 A13 379 RADDR10 B8
312 VDDi A19 346 SADDR6 H13 380 VDDi H8
313 SDATA2 B18 347 SADDR7 D14 381 VSSi D7
314 SDATA1 D18 348 SADDR8 G12 382 RADDR9 A7
315 SDATA0 C18 349 SADDR9 B12 383 RADDR8 C7
316 VDD_SDRAM G17 350 SADDR10 C12 384 RADDR7 B7
317 VSS_SDRAM A18 351 SADDR11 A12 385 RADDR6 A6
318 DQS1 B17 352 SADDR12 H12 386 RADDR5 G8
319 DQS0 C17 353 VDD_SDRAM D13 387 VDD_SRAM C6
320 DQM3 G16 354 VSS_SDRAM J12 388 VSS_SRAM G7
321 DQM2 C16 355 SADDR13 D12 389 RADDR4 B6
322 DQM1 H16 356 SADDR14 G11 390 RADDR3 A5
323 DQM0 A17 357 SADDR15 D11 391 RADDR2 B5
324 nSCS[0] H15 358 VDDi C11 392 RADDR1 D6
325 nSCS[1] D17 359 VSSi A11 393 RADDR0/GPA0 C5
326 nSWE B16 360 nWE_CF/GPA15 B11 394 nRBE1 D5
327 VDD_SDRAM C15 361 nOE_CF/GPA11 H11 395 nRBE0 A4

328 VSS_SDRAM G15 362

RADDR25/RDATA

_OEN

D10 396 nROE B4

329 SCLK A16 363 RADDR24/GPA9 C10 397 nRWE A3
330 VDD_SDRAM J15 364 RADDR23/GPA8 J11 398 nRCS0 A2
331 nSCLK B15 365 RADDR22/GPA7 A10 399 nRCS1 A1
332 VSS_SDRAM J14 366 RADDR21/GPA6 G10 400 nRCS2 B3
333 SCKE A15 367 RADDR20/GPA5 B10
334 VSSi D16 368 VDD_SRAM H10
335 VDDi B14 369 VSS_SRAM D9
336 nSRAS G14 370 RADDR19/GPA4 J10
337 nSCAS C14 371 RADDR18/GPA3 C9
338 SADDR0 H14 372 RADDR17/GPA2 G9
339 SADDR1 A14 373 RADDR16/GPA1 A9
340 SADDR2 G13 374 RADDR15 H9

1-10

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 1 of 12,TBD)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

1 VDD_SRAM VDD_SRAM
2 RSMCLK/GPA13 RSMCLK
3 VSS_SRAM VSS_SRAM
4 RSMVAD/GPA14 RSMVAD
5 RSMBWAIT/GPM0 RSMBWAIT
6 nRCS3 nRCS3
7 nRCS4 nRCS4
8 nRCS5/GPA12 nRCS5

9 nWAIT nWAIT
10 FCLE FCLE
11 FALE FALE
12 VDDi VDDi
13 VSSi VSSi
14 nFWE nFWE
15 nFRE nFRE
16 nFCE nFCE
17 FRnB/GPM1 FRnB
18 VDD_SRAM VDD_SRAM
19 VSS_SRAM VSS_SRAM
20 RDATA15 RDATA15
21 RDATA14 RDATA14
22 RDATA13 RDATA13
23 RDATA12 RDATA12
24 RDATA11 RDATA11
25 RDATA10 RDATA10
26 RDATA9 RDATA9
27 RDATA8 RDATA8
28 RDATA7 RDATA7
29 RDATA6 RDATA6
30 RDATA5 RDATA5
31 VDD_SRAM VDD_SRAM
32 VSS_SRAM VSS_SRAM
33 RDATA4 RDATA4
34 RDATA3 RDATA3

I/O State

@nRESET

I/O

Type

- P vdd33oph_hvt

-/- O(L) pvbsdct16cdrt_hvt

- P vssoh_hvt

-/- O(H) pvot16cdrt_hvt

-/- I pvisudcrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

-/- O(H) pvot16cdrt_hvt

- I pvisudcrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- P vdd12ih_hvt

- P vssiph_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- I pvisudcrt_hvt

- P vdd33oph_hvt

- P vssoh_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- P vdd33oph_hvt

- P vssoh_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

1-11

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 2 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

35 RDATA2 RDATA2
36 RDATA1 RDATA1
37 RDATA0 RDATA0
38 CAMVSYNC/GPJ9 GPJ9
39 CAMHREF/GPJ10 GPJ10
40 VSSi VSSi
41 VDDi VDDi
42 CAMPCLK/GPJ8 GPJ8
43 CAMDATA0/GPJ0 GPJ0
44 CAMDATA1/GPJ1 GPJ1
45 CAMDATA2/GPJ2 GPJ2
46 CAMDATA3/GPJ3 GPJ3
47 VDD_CAM VDD_CAM
48 VSS_CAM VSS_CAM
49 CAMDATA4/GPJ4 GPJ4
50 CAMDATA5/GPJ5 GPJ5
51 CAMDATA6/GPJ6 GPJ6
52 CAMDATA7/GPJ7 GPJ7
53 VDDiarm VDDiarm
54 VSSiarm VSSiarm
55 CAMPCLKOUT/GPJ11 GPJ11
56 CAMRESET/GPJ12 GPJ12
57 LEND/GPC0 GPC0
58 VDDiarm VDDiarm
59 VSSiarm VSSiarm
60 VCLK/GPC1 GPC1
61 VLINE/GPC2 GPC2
62 VM/GPC4 GPC4
63 VFRAME/GPC3 GPC3
64 LCDVF0/GPC5 GPC5
65 LCDVF1/GPC6 GPC6
66 LCDVF2/GPC7 GPC7
67 VD0/GPC8 GPC8
68 VDDiarm VDDiarm

I/O State

@nRESET

I/O

Type

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

- Hi-z pvbsdct16cdrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vssiph_hvt

- P vdd12ih_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd33oph_hvt

- P vssoh_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

1-12

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 3 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

69 VSSiarm VSSiarm
70 VD1/GPC9 GPC9
71 VSS_LCD VSS_LCD
72 VDD_LCD VDD_LCD
73 VD2/GPC10 GPC10
74 VD3/GPC11 GPC11
75 VD4/GPC12 GPC12
76 VD5/GPC13 GPC13
77 VD6/GPC14 GPC14
78 VD7/GPC15 GPC15
79 VD8/GPD0 GPD0
80 VD9/GPD1 GPD1
81 VDDiarm VDDiarm
82 VSSiarm VSSiarm
83 VD10/GPD2 GPD2
84 VD11/GPD3 GPD3
85 VD12/GPD4 GPD4
86 VD13/GPD5 GPD5
87 VD14/GPD6 GPD6
88 VD15/GPD7 GPD7
89 VD16/GPD8 GPD8
90 VD17/GPD9 GPD9
91 VD18/GPD10 GPD10
92 VDDiarm VDDiarm
93 VDDiarm VDDiarm
94 VSSiarm VSSiarm
95 VDD_LCD VDD_LCD
96 VSS_LCD VSS_LCD
97 VD19/GPD11 GPD11
98 VD20/GPD12 GPD12

99 VD21/GPD13 GPD13
100 VD22/GPD14 GPD14
101 VD23/GPD15 GPD15
102 TOUT0/GPB0 GPB0

I/O State

@Sleep

I/O State

@nRESET

I/O

Type

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

- P vssoh_hvt

- P vdd33oph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

- P vdd33oph_hvt

- P vssoh_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

1-13

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 4 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

103 TOUT1/GPB1 GPB1
104 TOUT2/GPB2 GPB2
105 TOUT3/GPB3 GPB3
106 VDDiarm VDDiarm
107 VSSiarm VSSiarm
108 TCLK/GPB4 GPB4
109 nXBACK/GPB5 GPB5
110 nXBREQ/BPG6 BPG6
111 VDD_OP2 VDD_OP2
112 VSS_OP2 VSS_OP2
113 nXDACK1/GPB7 GPB7
114 nXDREQ1/GPB8 GPB8
115 nXDACK0/GPB9 GPB9
116 nXDREQ0/GPB10 GPB10
117 VDDiarm VDDiarm
118 VSSiarm VSSiarm
119 EXTUARTCLK/GPH12 GPH12
120 nCTS0/GPH8 GPH8
121 nRTS0/GPH9 GPH9
122 TXD0/GPH0 GPH0
123 RXD0/GPH1 GPH1
124 nCTS1/GPH10 GPH10
125 nRTS1/GPH11 GPH11
126 TXD1/GPH2 GPH2
127 RXD1/GPH3 GPH3
128 EINT16/GPG8 GPG8
129 EINT17/GPG9 GPG9
130 VDDiarm VDDiarm
131 VSSiarm VSSiarm
132 EINT18/GPG10 GPG10
133 EINT19/nIREQ_CF/GPG11 GPG11

-/-/- I pvbsudct8smrt_hvt
134 VDD_OP2 VDD_OP2
135 CLKOUT0/GPH13 GPH13
136 CLKOUT1/GPH14 GPH14

I/O State

@nRESET

I/O

Type

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd33oph_hvt

- P vssoh_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

- P vdd33oph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

1-14

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 5 of 12) (Continued)

Pin

Number

137 VSS_OP2 VSS_OP2
138 EINT20/nINPACK/GPG12 GPG12
139 EINT21/nREG_CF/GPG13 GPG13
140 EINT22/RESET_CF/GPG14 GPG14
141 EINT23/CF_PWREN/GPG15 GPG15
142 VDDiarm VDDiarm
143 VSSiarm VSSiarm
144 IICSCL/GPE14 GPE14
145 IICSDA/GPE15 GPE15

146
147 I2SSCLK/GPE1/AC_SYNC GPE1
148

I2SCDCLK/GPE2/

149 I2SSDI/GPE3/AC_SDI0 GPE3
150 I2SSDO/GPE4/AC_SDO0 GPE4
151 SPIMISO0/GPE11 GPE11
152 SPIMOSI0/GPE12 GPE12
153 SPICLK0/GPE13 GPE13
154 VDDi VDDi
155 VSSi VSSi
156 VSS_SD VSS_SD
157 VDD_SD VDD_SD
158 TXD2/GPH4 GPH4
159 RXD2/GPH5 GPH5
160 TXD3/GPH6/nRTS2 GPH6
161 RXD3/GPH7/nCTS2 GPH7
162 SS[1]/GPL14 GPL14
163 SS[0]/GPL13 GPL13
164 SPIMISO1/GPL12 GPL12
165 SPIMOSI1/GPL11 GPL11
166 SPICLK1/GPL10 GPL10
167 SD0_nWP/GPJ15 GPJ15
168 SD0_nCD/GPJ14 GPJ14
169 SD0_LED/GPJ13 GPJ13
170 SD0_CLK/GPL9 GPL9

Pin

Name

I2SLRCK/GPE0/

AC_nRESET

AC_BIT_CLK0

Default

Function

GPE0

GPE2

I/O State

@Sleep

- P vssoh_hvt

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

- P vdd12ih_core_hvt

- P vssiph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/-/- I

-/-/- I pvbsudct8smrt_hvt

-/-/- I

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

- P vdd12ih_hvt

- P vssiph_hvt

- P vssoh_hvt

- P vdd33oph_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

I/O State

@nRESET

I/O

Type

pvbsudct8smrt_hvt

pvbsudct8smrt_hvt

1-15

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 6 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

171 VSSi VSSi
172 VDDi VDDi
173 SD0_CMD/GPL8 GPL8
174 SD0_DAT[0]/GPL0 GPL0
175 SD0_DAT[1]/GPL1 GPL1
176 SD0_DAT[2]/GPL2 GPL2
177 SD0_DAT[3]/GPL3 GPL3
178 SD0_DAT[4]/GPL4 GPL4
179 SD0_DAT[5]/GPL5 GPL5
180 SD0_DAT[6]/GPL6 GPL6
181 SD0_DAT[7]/GPL7 GPL7

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt

-/- I pvbsudct8smrt_hvt
182 VDD_SD VDD_SD
183 VSS_SD VSS_SD

184

SD1_CLK/GPE5/AC_BIT_CL

K

GPE5

185 SD1_CMD/GPE6/AC_SDI GPE6
186 SD1_DAT[0]/GPE7/AC_SDO GPE7

187
188

SD1_DAT[1]/GPE8/

AC_SYNC

SD1_DAT[2]/GPE9/

AC_RESET

GPE8
GPE9

189 SD1_DAT[3]/GPE10 GPE10

-/-/- I

-/-/- I pvbsudct8smrt_hvt

-/-/- I pvbsudct8smrt_hvt

-/-/- I

-/-/- I

-/- I pvbsudct8smrt_hvt
190 VSSA_MPLL VSSA_MPLL
191 MPLLCAP MPLLCAP
192 VDDA_MPLL VDDA_MPLL
193 VSSA_EPLL VSSA_EPLL
194 UPLLCAP UPLLCAP
195 VDDA_EPLL VDDA_EPLL
196 VSSA_ADC VSSA_ADC
197 AIN9(XP) AIN9
198 AIN8(XM) AIN8
199 AIN7(YP) AIN7
200 AIN6(YM) AIN6
201 AIN5 AIN5
202 AIN4 AIN4
203 AIN3 AIN3
204 AIN2 AIN2

I/O State

@nRESET

I/O

Type

- P vssiph_hvt

- P vdd12ih_hvt

- P vdd33oph_hvt

- P vssoh_hvt
pvbsudct8smrt_hvt

pvbsudct8smrt_hvt
pvbsudct8smrt_hvt

- P vssbb_abb

- AI poar50_pll_abb

- P vdd12t_abb

- P vssbb_abb

- AI poar50_pll_abb

- P vdd12t_abb

- P vssbbh_abb

AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

- AI phiar10_abb

1-16

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 7 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

205 AIN1 AIN1
206 AIN0 AIN0
207 Vref Vref

208 VDDA_ADC

VDDA_AD

C

209 VDD_RTC VDD_RTC
210 Xtortc Xtortc
211 Xtirtc Xtirtc
212 OM[4] OM[4]
213 OM[3] OM[3]
214 OM[2] OM[2]
215 OM[1] OM[1]
216 OM[0] OM[0]
217 VDDi VDDi
218 VSSi VSSi
219 VSS_OP1 VSS_OP1
220 EXTCLK EXTCLK
221 VDD_OP1 VDD_OP1
222 VDDalive VDDalive
223 XTIpll XTIpll
224 XTOpll XTOpll
225 VSSalive VSSalive
226 EINT0/GPF0 GPF0
227 EINT1/GPF1 GPF1
228 EINT2/GPF2 GPF2
229 EINT3/GPF3 GPF3
230 EINT4/GPF4 GPF4
231 EINT5/GPF5 GPF5
232 EINT6/GPF6 GPF6
233 EINT7/GPF7 GPF7
234 PWR_EN PWR_EN

O(L) O(H) pvob8sm_hvt
235 BATT_FLT BATT_FLT
236 nRESET nRESET
237 TDO TDO
238 TMS TMS

I/O State

@nRESET

I/O

Type

- AI phiar10_abb

- AI phiar10_abb

- AI phia_abb

- P

vdd33th_abb

- P vdd30th_rtc

- AO rtc_osc

- AI rtc_osc

- I pvis_hvt

- I pvis_hvt

- I pvis_hvt

- I pvis_hvt

- I pvis_hvt

- P vdd12ih_hvt

- P vssiph_hvt

- P vssoh_hvt

- I pvis_hvt

- P vdd33oph_hvt

- P vdd12ih_hvt

- AI pvsoscm26_hvt

- AO pvsoscm26_hvt

- P vssiph_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

- I pvis_hvt

- I pvis_hvt

- O pvot8sm_hvt

- I pvisu_hvt

1-17

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 8 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

239 TDI TDI
240 TCK TCK
241 nTRST nTRST
242 EINT8/GPG0 GPG0
243 EINT9/GPG1 GPG1
244 EINT10/GPG2 GPG2
245 EINT11/GPG3 GPG3

246

EINT12/GPG4/

LCD_PWREN

GPG4

247 EINT13/GPG5 GPG5
248 EINT14/GPG6 GPG6
249 EINT15/GPG7 GPG7
250 VDD_OP1 VDD_OP1
251 DP DP
252 DN DN
253 VSS_OP1 VSS_OP1
254 nRSTOUT nRSTOUT
255 VDDalive VDDalive
256 VSSalive VSSalive
257 VDDalive VDDalive
258 XI_UDEV XI_UDEV
259 XO_UDEV XO_UDEV
260 VSSA33C VSSA33C
261 VDDA33C VDDA33C
262 REXT REXT
263 VDDA33T1 VDDA33T1
264 VSSA33T2 VSSA33T2
265 DM_UDEV DM_UDEV
266 VSSA33T2 VSSA33T2
267 DP_UDEV DP_UDEV
268 VSSA33T2 VSSA33T2
269 VDDA33T1 VDDA33T1
270 VDDI_UDEV VDDI_UDEV
271 VSSI_UDEV VSSIP_UDEV
272 SDATA31 SDATA31

@Sleep

I/O State

@nRESET

I/O

Type

- I pvisu_hvt

- I pvisu_hvt

- I pvis_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/-/- I

pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

-/- I pvbsudct8sm_hvt

- P vdd33oph_hvt

- AI pbusb1

- AI pbusb1

- P vssoh_hvt

O(H) O(L) pvob8sm_hvt

- P vdd12ih_hvt

- P vssiph_hvt

- P vdd12ih_core_hvt

- I phia_abb

- I phia_abb

- P vssbbh_abb

- P vdd33th_abb

- phoarext_abb

- P vdd33th_abb

- P vssbbh_abb
Hi-z phtoa_abb

- P vssbbh_abb

- Hi-z phtoa_abb

- P vssbbh_abb

- P vdd33th_abb

- P vdd12ih_core_hvt

- P vssiph_hvt

- Hi-z phnbsud100ct12cd_ddrret

1-18

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 9 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

273 SDATA30 SDATA30
274 SDATA29 SDATA29
275 SDATA28 SDATA28
276 VDD_SDRAM VDD_SDRAM
277 VSS_SDRAM VSS_SDRAM
278 SDATA27 SDATA27
279 SDATA26 SDATA26
280 VDDi VDDi
281 VSSi VSSi
282 SDATA25 SDATA25
283 SDATA24 SDATA24
284 SDATA23 SDATA23
285 SDATA22 SDATA22
286 SDATA21 SDATA21
287 VDD_SDRAM VDD_SDRAM
288 VSS_SDRAM VSS_SDRAM
289 SDATA20 SDATA20
290 SDATA19 SDATA19
291 SDATA18 SDATA18
292 SDATA17 SDATA17
293 SDATA16 SDATA16
294 SDATA15 SDATA15
295 SDATA14 SDATA14
296 VDD_SDRAM VDD_SDRAM
297 VSS_SDRAM VSS_SDRAM
298 SDATA13 SDATA13
299 SDATA12 SDATA12
300 SDATA11 SDATA11
301 SDATA10 SDATA10
302 SDATA9 SDATA9
303 SDATA8 SDATA8
304 SDATA7 SDATA7
305 SDATA6 SDATA6
306 SDATA5 SDATA5

I/O State

@Sleep

I/O State

@nRESET

I/O

Type

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- P vdd12i_ddr

- P vssip_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z vdd18op_ddr

- Hi-z vsso_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

1-19

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 10 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

307 VDD_SDRAM VDD_SDRAM
308 VSS_SDRAM VSS_SDRAM
309 SDATA4 SDATA4
310 SDATA3 SDATA3
311 VSSi VSSi
312 VDDi VDDi
313 SDATA2 SDATA2
314 SDATA1 SDATA1
315 SDATA0 SDATA0
316 VDD_SDRAM VDD_SDRAM
317 VSS_SDRAM VSS_SDRAM
318 DQS1 DQS1
319 DQS0 DQS0
320 DQM3 DQM3
321 DQM2 DQM2
322 DQM1 DQM1
323 DQM0 DQM0
324 nSCS[0] nSCS[0]
325 nSCS[1] nSCS[1]
326 nSWE nSWE
327 VDD_SDRAM VDD_SDRAM
328 VSS_SDRAM VSS_SDRAM
329 SCLK SCLK
330 VDD_SDRAM VDD_SDRAM
331 nSCLK nSCLK
332 VSS_SDRAM VSS_SDRAM
333 SCKE SCKE
334 VSSi VSSi
335 VDDi VDDi
336 nSRAS nSRAS
337 nSCAS nSCAS
338 SADDR0 SADDR0
339 SADDR1 SADDR1
340 SADDR2 SADDR2

I/O State

@Sleep

I/O State

@nRESET

I/O

Type

- P vdd18op_ddr

- P vsso_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- P vssip_ddr

- P vdd12i_ddr

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- Hi-z phnbsud100ct12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr
O(L) Hi-z phnbsud100ct12cd_ddrret
O(L) Hi-z phnbsud100ct12cd_ddrret

O(H)- O(L) phnot12cd_ddrret

O(H) O(L) phnot12cd_ddrret
O(H) O(L) phnot12cd_ddrret
O(H) O(L) phnot12cd_ddrret
O(H) O(H) phnot12cd_ddrret
O(H) O(H) phnot12cd_ddrret
O(H) O(H) phnot12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr
O(L) O(SCLK) phnbsud100ct12cd_ddrret

- P vdd18op_ddr

O(H) O(nSCLK) phnot12cd_ddrret

P vsso_ddr

O(L) O(L) phnoud100ct12cd_ddrret

- P vssip_ddr

- P vdd12i_ddr

O(H) O(H) phnot12cd_ddrret
O(H) O(H) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

1-20

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 11 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

341 SADDR3 SADDR3
342 SADDR4 SADDR4
343 VDD_SDRAM VDD_SDRAM
344 VSS_SDRAM VSS_SDRAM
345 SADDR5 SADDR5
346 SADDR6 SADDR6
347 SADDR7 SADDR7
348 SADDR8 SADDR8
349 SADDR9 SADDR9
350 SADDR10 SADDR10
351 SADDR11 SADDR11
352 SADDR12 SADDR12
353 VDD_SDRAM VDD_SDRAM
354 VSS_SDRAM VSS_SDRAM
355 SADDR13 SADDR13
356 SADDR14 SADDR14
357 SADDR15 SADDR15
358 VDDi VDDi
359 VSSi VSSi
360 nWE_CF/GPA15 nWE_CF
361 nOE_CF/GPA11 nOE_CF
362 RADDR25/RDATA_OEN RADDR25
363 RADDR24/GPA9 RADDR24
364 RADDR23/GPA8 RADDR23
365 RADDR22/GPA7 RADDR22
366 RADDR21/GPA6 RADDR21
367 RADDR20/GPA5 RADDR20
368 VDD_SRAM VDD_SRAM
369 VSS_SRAM VSS_SRAM
370 RADDR19/GPA4 RADDR19
371 RADDR18/GPA3 RADDR18
372 RADDR17/GPA2 RADDR17
373 RADDR16/GPA1 RADDR16
374 RADDR15 RADDR15

I/O State

@Sleep

I/O State

@nRESET

I/O

Type

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- P vdd18op_ddr

- P vsso_ddr

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- O(L) phnot12cd_ddrret

- P vdd12i_ddr

- P vssip_ddr

-/- O(H) pvot16cdrt_hvt

-/- O(H) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

- P vdd33oph_hvt

- P vssoh_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

1-21

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-2. S3C2443X 400-Pin FBGA Pin Assignments (Sheet 12 of 12) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@Sleep

375 RADDR14 RADDR14
376 RADDR13 RADDR13
377 RADDR12 RADDR12
378 RADDR11 RADDR11
379 RADDR10 RADDR10
380 VDDi VDDi
381 VSSi VSSi
382 RADDR9 RADDR9
383 RADDR8 RADDR8
384 RADDR7 RADDR7
385 RADDR6 RADDR6
386 RADDR5 RADDR5

387 VDD_SRAM

388 VSS_SRAM

VDD_SRA

M

VSS_SRA

M

389 RADDR4 RADDR4
390 RADDR3 RADDR3
391 RADDR2 RADDR2
392 RADDR1 RADDR1
393 RADDR0/GPA0 RADDR0
394 nRBE1 nRBE1
395 nRBE0 nRBE0
396 nROE nROE
397 nRWE nRWE
398 nRCS0 nRCS0
399 nRCS1 nRCS1
400 nRCS2 nRCS2

I/O State

@nRESET

I/O

Type

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- P vdd12ih_hvt

- P vssiph_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- P

- P

vdd33oph_hvt

vssoh_hvt

- O(L) pvot16cdrt_vt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

- O(L) pvot16cdrt_hvt

-/- O(L) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

- O(H) pvot16cdrt_hvt

1-22

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

NOTES:

1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.

2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.

3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.

4. AI/AO means analog input/analog output.

5. P, I, and O mean power, input and output respectively.

6. The I/O state @nRESET shows the pin status in the @nRESET duration below.

nRESET

EXTCLK

4 OSCin

@nRESET > 10 cycle

1-23

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS

IO Type Description

vdd33oph_hvt Power for IO(1.8V/2.5V/3.3V)

pvbsdct16cdrt_hvt

1.8V/2.5V/3.3V interface, bi-directional, schmitt triggered, pull-down
controllerable, tri-state, retention(4/8/12/16m driver controllable)

vssoh_hvt Ground for IO

pvot16cdrt_hvt

pvisudcrt_hvt

1.8V/2.5V/3.3V interface, output, tri-state, retention(4/8/12/16m driver
controllable)

1.8V/2.5V/3.3V interface, input, schmitt triggered, pull-up/pull-down
controllable, retention

vdd12ih_hvt Power for internal logic(1.2V)

vssiph_hvt Ground for internal logic

pvbsudct8smrt_hvt

1.8V/2.5V/3.3V interface, bi-directional, schmitt triggered, pull-up/pull­down controllable, tri-state, retention(8m driver)

vdd12ih_core_hvt Power for internal logic(1.2V)

vssbb_abb Ground for analog circuit

poar50_pll_abb 1.2V interface, output, analog for PMPLLCAP/PEPLLCAP

vdd12t_abb Power for analog circuit(1.2V)

vssbbh_abb Ground for analog circuit

phiar10_abb 3.3V interface, input, analog for AIN[9:0]

phia_abb 3.3V interface, input, analog for Vref

vdd33th_abb Power for analog circuit(3.3V)

vdd30th_rtc Power for rtc circuit(3.0V)

rtc_osc 3.0V interface, Oscillator for RTC

pvis_hvt 2.5V/3.3V interface, input, Schmitt triggered

pvsoscm26_hvt 2.5V/3.3V interface, oscillator, Schmitt triggered,

pvbsudct8sm_hvt

1.8V/2.5V/3.3V interface, bi-directional, schmitt triggered, pull-up/pull­down controllable, tri-state(8m driver)

pvob8sm_hvt 2.5V/3.3V interface, output, normal buffer

pvot8sm_hvt 2.5V/3.3V interface, output, tri-state buffer

pvisu_hvt 2.5V/3.3V interface, input, Schmitt triggered, pull-up

pbusb1 USB host Pad (DP/DN)

phoa_abb 3.3V interface, output, analog for

phoarext_abb 3.3V interface, output, analog for REXT

1-24

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

phtoa_abb USB 3.3V interface, bi-directional, alalog for DP_UDEV, DM_UDEV

phnbsud100ct12cd_ddrret

1.8V/2.5V/3.3V interface, bi-directional, Schmitt triggered, tri-state,
retention(6/8/10/12m driver controllable)

vdd18op_ddr 1.8V/2.5V/3.3V IO Power for DRAM Interface

vsso_ddr IO Ground for DRAM Interface

vdd12i_ddr 1.2V Power for internal logic

vssip_ddr Ground for Internal logic

phnot12cd_ddrret

1.8V/2.5V/3.3V interface, output, tri-state, retention(6/8/10/12m driver
controllable)

1-25

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

SIGNAL DESCRIPTIONS

Table 1-3. S3C2443X Signal Descriptions

Signal In/Out Description

Reset, Clock & Power

XTIpll AI Crystal input signals for internal osc circuit.

When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.
If it isn't used, it has to be Low (0V)

XTOpll AO Crystal output signals for internal osc circuit.

When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.

If it isn't used, it has to be float
MPLLCAP AI Loop filter capacitor for Main PLL.
EPLLCAP AI Loop filter capacitor for Extra PLL
XTIrtc AI 32.768 kHz crystal input for RTC. If it isn’t used, it has to be High

(VDD_RTC=3.3V).
XTOrtc AO 32.768 kHz crystal output for RTC. If it isn’t used, it has to be float.
CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR(GPIO register) register

configures the clock output mode among the MPLL_CLK, EPLL CLK,

ARMCLK, HCLK, PCLK.
nRESET ST nRESET suspends any operation in progress and places S3C2443X into a

known reset state. For a reset, nRESET must be held to L level for at least 4

OSCin after the processor power has been stabilized.
nRSTOUT O For external device reset control (nRSTOUT = nRESET & nWDTRST &

SW_RESET) *SW_RESET = nRSTCON of GPIO MISCCR
PWREN O core power on-off control signal
nBATT_FLT I Probe for battery state (Does not wake up at Sleep mode in case of low

battery state). If it isn’t used, it has to be High (3.3V).
OM[4:0] I

OM[4:0] set operating modes of S3C2443X

Refer to “S3C2443 OPERATION MODE DESCRIPTION TABLE”
EXTCLK I Ex t e rnal clock source.

When OM[0] = 1, EXTCLK is used for MPLL and EPLL CLK source.

If it isn't used, it has to be Low (0V).
Memory Interface (ROM/SRAM/NAND/CF)

RADDR[25:0]

O

RADDR[25:0] (Address Bus) outputs the memory address of the

corresponding bank .
RDATA[15:0]

IO

RDATA[15:0] (Data Bus) inputs data during memory read and outputs data

during memory write. The bus width is programmable among 8/16-bit.
nRCS[5:0]

O

nRCS[5:0] (Chip Select) are activated when the address of a memory is within

the address region of each bank. The number of access cycles and the bank

size can be programmed.
nRWE

nROE
nRBE[1:0]
nWAIT

O nRWE (Write Enable) indicates that the current bus cycle is a write cycle.
O nOE (Output Enable) indicates that the current bus cycle is a read cycle.
O Upper byte/lower byte enable (In case of 16-bit SRAM)

I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the

current bus cycle cannot be completed. If nWAIT signal isn’t used in your

system, nWAIT signal must be tied on pull-up resistor.

1-26

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Signal In/Out Description

SDRAM I/F

SADDR[15:0] O SDRAM/DDR Address bus
SDATA[31:0] IO SDRAM/DDR Data Bus
nSRAS O SDRAM/DDR row address strobe
nSCAS O SDRAM/DDRcolumn address strobe
nSCS[1:0] O SDRAM/DDR chip select
DQM[3:0] O SDRAM/DDR data mask
DQS[1:0] O DDR Data Strobe
SCLK O SDRAM/DDR clock
nSCLK O DDR Conversion clock
SCKE O SDRAM/DDR clock enable
NAND Flash
FCLE O Command latch enable
FALE O Address latch enable
nFCE O Nand flash chip enable
nFRE O Nand flash read enable
nFWE O Nand flash write enable
FRnB I Nand flash ready/busy
SMC/OneNAND
RSMCLK I/O SMC Clock
RSMVAD O SMC Address Valid
RSMBWAIT O SMC Burst Wait
CF I/F
nOE_CF O CF Output Enable Strobe
nWE_CF O CF Write Enable Strobe
nIREQ_CF I Interrupt request from CF card
nINPACK_CF I Input acknowledge in I/O mode
CardPWR_CF O Card Power Enable
nREG_CF O Register in CF card strobe
RESET_CF O CF card reset

1-27

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Signal In/Out Description

LCD Control Unit

VD[23:0] O STN/TFT/SEC TFT: LCD data bus
LCD_PWREN O STN/TFT/SEC TFT: LCD panel power enable control signal
VCLK O STN/TFT: LCD clock signal
VFRAME O STN: VFRAM signal

TFT: VSYNC signal
VLINE O STN: VLINE signal

TFT: HSYNC signal
VM O STN: VM alternates the polarity of the row and column voltage

TFT: VDEN enable data signals
LEND O TFT: Line end signal
LCDVF[2:0] O SEC TFT: Timing control signal for specific TFT LCD(OE/REV/REVB)
CAMERA Interface
CAMRESET O Camera interface reset
CAMCLKOUT O Camera interface master clock
CAMPCLK I Camera interface pixel clock
CAMHREF I Camera interface horizontal sync
CAMVSYNC I Camera interface horizontal sync
CAMDATA[7:0] I Camera interface data
Interrupt Control Unit
EINT[23:0] I External interrupt request
External I/F
nXDREQ[1:0] I External DMA request
nXDACK[1:0] O External DMA acknowledge
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of

the local bus. nXBACK active indicates that bus control has been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2443X has

surrendered control of the local bus to another bus master.
UART
RXD[3:0] I UART receives data input (ch. 0/1/2)
TXD[3:0] O UART transmits data output (ch. 0/1/2)
nCTS[2:0] I UART clear to send input signal (ch. 0/1)
nRTS[2:0] O UART request to send output signal (ch. 0/1)
EXTUARTCLK I External clock input for UART

1-28

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Signal In/Out Description

TSADC

AIN[9:0] AI ADC input[9:0]. If it isn’t used pin, it has to be low (ground).

When touch screen device is used, A[6], A[7] , A[8] and A[9] are used as YM,

YP, XM and XP, respectively.
Vref AI ADC Vref
IIC-Bus
IICSDA IO IIC-bus data
IICSCL IO IIC-bus clock
IIS-Bus
I2SLRCK IO IIS-bus channel select clock
I2SSCLK IO IIS-bus serial clock
I2SCDCLK O CODEC system clock
I2SSDI I IIS-bus serial data input
I2SSDO O IIS-bus serial data output
AC’97
AC_nRESET
AC_SYNC
AC_BIT_CLK0
AC_SDI0
AC_SDO0

IO AC’97 Master H/W Reset
IO 12.288MHz serial data clock
O

48kHz fixed rate sample sync

I Serial, time division multiplexed, AC’97 input stream

O Serial, time division multiplexed, AC’97 output stream
USB Host
DN IO
DP IO

DATA(–) from USB host. (Need to 15kΩ pull-down)

DATA(+) from USB host. (Need to 15kΩ pull-down)
USB Device
DM_UDEV IO DATA(–) for USB peripheral.
DP_UDEV IO DATA(+) for USB peripheral.
REXT O External Resist ( 3.4Kohm +/- 1%)
XO_UDEV OSC Crystal output
XI_UDEV OSC Crystal input

1-29

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Signal In/Out Description

SPI

SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role.
* SPIMISO[0] is for the High Speed SPI Interface.

SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role.
* SPIMOSI[0] is for the High Speed SPI Interface.

SPICLK[1:0] IO SPI clock

* SPICLK[0] is for the High Speed SPI Interface.

nSS[1:0] I SPI chip select (only for slave mode)

*nSS[0] is for the High Speed SPI Interface.
SDMMC Interface
SD0_DAT[7:0] IO SD0 receive/transmit data
SD0_CMD IO SD0 receive response/ transmit command
SD0_CLK O SD0 clock
SD0_nWP O SD0 Write Protect
SD0_nCD O SD0 Card Detect
SD0_nLED O SD0 LED
SD1_DAT[3:0] IO SD1 receive/transmit data
SD1_CMD IO SD1 receive response/ transmit command
SD1_CLK O SD1 clock
General Port
GPn[147:0] IO

General input/output ports, which are multiplexed with other function pins (some ports

are output only).

TIMMER/PWM
TOUT[3:0] O Timer output[3:0]
TCLK I External timer clock input
JTAG TEST LOGIC
nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.

If debugger is used, A 10K pull-up resistor has to be connected.

If debugger (black ICE) is not used, nTRST pin must be issued by a low active

pulse (Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP

controller's states.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and

data.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and

data.

1-30

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Signal In/Out Description

Power

VDDalive P S3C2443X reset block and port status register VDD.

It should be always supplied whether in normal mode or in Sleep mode.
VDDiarm P S3C2443X core logic VDD for ARM core.
VDDi P S3C2443X core logic VDD for Internal block.
VSSi/VSSiarm P S3C2443X core logic VSS
VDDA_MPLL P S3C2443X MPLL analog and digital VDD.
VSSA_MPLL P S3C2443X MPLL analog and digital VSS.
VDD_RTC P RTC VDD (3.0V, Input range: 2.5 ~ 3.6V)

This pin must be connected to power properly if RTC isn't used.
VDDA_EPLL P S3C2443X EPLL analog and digital VDD
VSSA_EPLL G S3C2443X EPLL analog and digital VSS
VDD_OP1 P S3C2443X System I/O Power (2.5 ~ 3.3V)
VDD_OP2 P S3C2443X System I/O Power 2 ( 1.8 ~ 3.3V)
VDD_CAM P S3C2443X Camera I/O Power (1.8 ~ 3.3V)
VDD_LCD P S3C2443X LCD I/O Power (2.5 ~ 3.3V)
VDD_SD P S3C2443X SD/MMC I/O Power (1.8 ~ 3.3V)
VDD_SDRAM P S3C2443X SDRAM/DDR I/O Power (1.8V/ 2.5V/ 3.3V)
VDD_SRAM P S3C2443X ROM/SRAM I/O Power
VSS_OP1 G S3C2443X System I/O Ground
VSS_OP2 G S3C2443X System I/O Ground
VSS_CAM G S3C2443X Camera I/O Ground
VSS_LCD G S3C2443X LCD I/O Ground
VSS_SD G S3C2443X SD/MMC I/O Ground
VSS_SDRAM G S3C2443X SDRAM/DDR I/O Ground
VSS_SRAM G S3C2443X ROM/SRAM I/O Ground
VDDA_ADC P S3C2443X ADC VDD(3.3V)
VSSA_ADC P S3C2443X ADC VSS
VDDI_UDEV P USB 2.0 Phy Power ( 1.2V)
VSSI_UDEV G USB 2.0 Phy Ground
VDDA33C/VDDA33T1 P USB 2.0 Phy Power ( 3.3V)
VSSA33C/VSSA33T2 G USB 2.0 Phy Ground

NOTES:

1. I/O means Input/Output.

2. AI/AO means analog input/analog output.

3. ST means schmitt-trigger.

4. P means power.

1-31

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

S3C2443X OPERATION MODE DESCRIPTION

Table 1-4. S3C2443X Operation Mode Description

OM[4] OM[3] OM[2] OM[1] OM[0] OM[4] OM[3] OM[2] OM[1] OM[0]

0

0

1

0

0

1

1

0

0

0

1

1

0

1

1

0

0

1

1 0

0

1

1

0 OSC

1

0 OSC

1

0 OSC

1

0 OSC

1

0 OSC

1

N

A
N
D

0 OSC
1
0 OSC
1

A

d
v
a
n
c
e
d

N

o

r

m

a

l

-

page(2K)

-

page(512)

0 OSC
1

addr(4)

EXT

addr(5)

EXT

addr(4)

EXT

addr(5)

EXT

addr(3)

EXT

addr(4)

EXT

addr(3)

EXT

addr(4)

EXT
0 OSC
1 EXT
0 OSC
1
0 OSC

OneNAND/

ROM

1
0 OSC
1

One

NAND

ROM

16-bit

EXT

8-bit

EXT

16-bit

EXT

Operation

OneNAND

OneNAND

(Demuxed)

* OM[0] selects the clock source of MPLL/EPLL
( You can select different EPLL clock source with that of MPLL by software setting – refer to SYSCON)
* addr(x) means the number of address cycle during NAND Flash operation.

Mode

NAND

(Muxed)

ROM/

1-32

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

S3C2443X MEMORY MAP AND BASE ADDRESS OF SPECIAL REGISTERS
Memory Map

0x40000_0000

0x3800_0000

0x3000_0000
0x2840_0000
0x2800_0000
0x2040_0000
0x2000_0000
0x1840_0000
0x1800_0000
0x1040_0000
0x1000_0000
0x0840_0000
0x0800_0000

0x0400_0000

0x0000_0000

[ Not using NAND flash for boot ROM ] [ Using NAND flash for boot ROM ]

SRAM (4KB)

SDRAM
(nSCS1)

SDRAM
(nSCS0)

SROM

(nRCS5)

SROM

(nRCS4)

SROM

(nRCS3)

SROM

(nRCS2)

SROM

(nRCS1)

SROM

(nRCS0)

OM[4] = 0 OM[4] = 1

MPORT

1

MPORT

0

SDRAM

(nSCS1)

SDRAM

(nSCS0)

SROM

(nRCS5)

SROM

(nRCS4)

SROM

(nRCS3)

SROM

(nRCS2)

SROM

(nRCS1)

Boot Internal

SRAM (4KB)

Figure 1-3. Memory Map

2MB/4MB/8MB/16MB

/32MB/64MB/128MB

2MB/4MB/8MB/16MB

/32MB/64MB/128MB

64MB

64MB
64MB

64MB
64MB

64MB
64MB

64MB
64MB

64MB

HADDR[29:0]

Accessible

Region

1GB

1-33

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Base Address of Special Registers

Address Module Address Module

0x5100_0000 PWM 0x5B00_0000 AC97
0x5000_0000 UART 0x5A00_0000 SDI
0x4F80_0000 TIC

0x5900_0000 SPI

0x4F00_0000 SSMC
0x4E80_0000 MATRIX

0x5800_0000 TSADC

0x4E00_0000 NFCON

0x4D80_0000 CAM I/F

0x5700_0000 RTC

0x4D00_0000 STN-LCD
0x4C80_0000 TFT-LCD

0x5600_0000 IO Port

0x4C00_0000 SYSCON
0x4B80_0000 CF Card

0x5500_0000 IIS

0x4B00_0000 DMA
0x4A80_0000 HS-MMC

0x5400_0000 IIC

0x4A00_0000 INTC

0x4980_0000 USB Device

0x5300_0000 WDT

0x4900_0000 USB HOST
0x4880_0000 EBI

0x5200_0000 HS-SPI

0x4800_0000 SDRAM

1-34

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

DRAM Controller

BANKCFG 0x48000000
BANKCON1 0x48000004
BANKCON2 0x48000008
BANKCON3 0x4800000C
REFRESH 0x48000010
TIMEOUT 0x48000014

←

W R/W Mobile DRAM configuration register

Mobile DRAM control register
Mobile DRAM timing control register
Mobile DRAM (E)MRS Register
Mobile DRAM refresh control register

Write Buffer Time out control register
MATRIX & EBI
BPRIORITY0 0X4E800000
BPRIORITY1 0X4E800004
EBICON 0X4E800008

R/W Matrix Core 0 priority control register

R/W Matrix Core 1 priority control register

R/W EBI control register
Memory Controllers ( SSMC )
SMBIDCYR0 0x4F000000 W R/W Bank0 idle cycle control register
SMBIDCYR1 0x4F000020 R/W Bank1 idle cycle control register
SMBIDCYR2 0x4F000040 R/W Bank2 idle cycle control register
SMBIDCYR3 0x4F000060 R/W Bank3 idle cycle control register
SMBIDCYR4 0x4F000080 R/W Bank4 idle cycle control register
SMBIDCYR5 0x4F0000A0 R/W Bank5 idle cycle control register
SMBWSTRDR0 0x4F000004
SMBWSTRDR1 0x4F000024
SMBWSTRDR2 0x4F000044
SMBWSTRDR3 0x4F000064
SMBWSTRDR4 0x4F000084
SMBWSTRDR5 0x4F0000A4
SMBWSTWRR0 0x4F000008
SMBWSTWRR1 0x4F000028
SMBWSTWRR2 0x4F000048
SMBWSTWRR3 0x4F000068
SMBWSTWRR4 0x4F000088
SMBWSTWRR5 0x4F0000A8

SMBWSTOENR0 0x4F00000C

SMBWSTOENR1 0x4F00002C

R/W Bank0 read wait state control register
R/W Bank1 read wait state control register
R/W Bank2 read wait state control register
R/W Bank3 read wait state control register
R/W Bank4 read wait state control register
R/W Bank5 read wait state control register
R/W Bank0 write wait state control register
R/W Bank1 write wait state control register
R/W Bank2 write wait state control register
R/W Bank3 write wait state control register
R/W Bank4 write wait state control register
R/W Bank5 write wait state control register

R/W

R/W

Bank0 output enable assertion delay
control register

Bank1 output enable assertion delay
control register

1-35

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

SMBWSTOENR2 0x4F00004C

SMBWSTOENR3 0x4F00006C

SMBWSTOENR4 0x4F00008C

SMBWSTOENR5 0x4F0000AC

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

R/W

R/W

R/W

R/W

Function

Bank2 output enable assertion delay
control register

Bank3 output enable assertion delay
control register

Bank4 output enable assertion delay
control register

Bank5 output enable assertion delay
control register

SMBWSTWENR0 0x4F000010 R/W Bank0 write enable assertion delay

control register

SMBWSTWENR1 0x4F000030 R/W Bank1 write enable assertion delay

control register

SMBWSTWENR2 0x4F000050 R/W Bank2 write enable assertion delay

control register

SMBWSTWENR3 0x4F000070 R/W Bank3 write enable assertion delay

control register

SMBWSTWENR4 0x4F000090 R/W Bank4 write enable assertion delay

control register

SMBWSTWENR5 0x4F0000B0 R/W Bank5 write enable assertion delay

control register
SMBCR0 0x4F000014
SMBCR1 0x4F000034
SMBCR2 0x4F000054
SMBCR3 0x4F000074
SMBCR4 0x4F000094
SMBCR5 0x4F0000B4
SMBSR0 0x4F000018
SMBSR1 0x4F000038
SMBSR2 0x4F000058
SMBSR3 0x4F000078
SMBSR4 0x4F000098
SMBSR5 0x4F0000B8

SMBWSTBRDR0 0x4F00001C

SMBWSTBRDR1 0x4F00003C

R/W Bank0 control register
R/W Bank1 control register
R/W Bank2 control register
R/W Bank3 control register
R/W Bank4 control register
R/W Bank5 control register
R/W Bank0 status register
R/W Bank1 status register
R/W Bank2 status register
R/W Bank3 status register
R/W Bank4 status register
R/W Bank5 status register

R/W

R/W

Bank0 burst read wait delay control

register

Bank1 burst read wait delay control

register

1-36

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

SMBWSTBRDR2 0x4F00005C

SMBWSTBRDR3 0x4F00007C

SMBWSTBRDR4 0x4F00009C

SMBWSTBRDR5 0x4F0000BC

Address

(B. Endian)

Address

Acc.

(L. Endian)

Unit

Read/

Write

R/W

R/W

R/W

R/W

Function

Bank2 burst read wait delay control
register

Bank3 burst read wait delay control
register

Bank4 burst read wait delay control
register

Bank5 burst read wait delay control
register

SMBONETYPER 0x4F000100 R/W SMC Bank OneNAND TYPE

SELECTION REGISTER
SMCSR 0x4F000200
SMCCR 0x4F000204

R/W SMC status register
R/W SMC Control register

1-37

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

CF Controller

MUX_REG 0x4B801800 R/W Top level control & configuration

register

PCCARD_

0x4B801820 PC card configuration & status register
CNFG&STATUS
PCCARD_
INTMSK&SRC

0x4B801824 PC card interrupt mask & source

regiseter

PCCARD_ATTR 0x4B801828 PC card attribute memory area

operation timing config regiseter

PCCARD_I/O 0x4B80182C PC card I/O area operation timing

config regiseter

PCCARD_COMM 0x4B801830 PC card common memory area

operation timing config regiseter
ATA_CONTROL 0x4B801900
ATA_STATUS 0x4B801904
ATA_COMMAND 0x4B801908
ATA_SWRST 0x4B80190C
ATA_IRQ 0x4B801910
ATA_IRQ_MASK 0x4B801914
ATA_CFG 0x4B801918
ATA_PIO_TIME 0x4B80192C
ATA_UDMA_TIME 0x4B801930
ATA_XFR_NUM 0x4B801934
ATA_XFR_CNT 0x4B801938
ATA_TBUF_START 0x4B80193C
ATA_TBUF_SIZE 0x4B801940
ATA_SBUF_

0x4B801944

START
ATA_SBUF_SIZE 0x4B801948
ATA_SBUF_

0x4B801944

START
ATA_SBUF_SIZE 0x4B801948
ATA_CADR_TBUF 0x4B80194C

ATA_CADR_SBUF 0x4B801950

ATA_PIO_DTR 0x4B801954

ATA enable and clock down status
ATA status
ATA command

ATA software reset
ATA interrupt sources
ATA interrut mask
ATA configuration for ATA interface
ATA PIO timing
ATA UDMA timing
ATA transfer number
ATA current transfer count
ATA start address of track buffer
ATA size of track buffer

ATA start address of source buffer

ATA size of source buffer

ATA start address of source buffer

ATA size of source buffer

ATA current write address of track
buffer

ATA current read address of source
buffer

ATA PIO device data register

1-38

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

(L. Endian)

ATA_PIO_FED 0x4B801958
ATA_PIO_SCR 0x4B80195C
ATA_PIO_LLR 0x4B801960
ATA_PIO_LMR 0x4B801964
ATA_PIO_LHR 0x4B801968
ATA_PIO_DVR 0x4B80196C
ATA_PIO_CSD 0x4B801970

ATA_PIO_DAD
ATA_PIO_READY

0x4B801974
0x4B801978

ATA_PIO_RDATA 0x4B80197C

BUS_FIFO_

0x4B801990

STATUS
ATA_FIFO_

0x4B801994

STATUS

Address

Acc.

Unit

Read/

Function

Write

ATA PIO device Feature/Error register
ATA PIO sector count register
ATA PIO device LBA low register
ATA PIO device LBA middle register
ATA PIO device LBA high register
ATA PIO device register

ATA PIO device command/status
register

ATA PIO device control/alternate status
register

ATA PIO read data from device data
register

ATA internal AHB FIFO status

ATA internal ATA FIFO status

1-39

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

USB Host Controller

HcRevision 0x49000000
HcControl 0x49000004
HcCommonStatus 0x49000008
HcInterruptStatus 0x4900000C
HcInterruptEnable 0x49000010
HcInterruptDisable 0x49000014
HcHCCA 0x49000018
HcPeriodCuttentED 0x4900001C
HcControlHeadED 0x49000020
HcControlCurrent

0x49000024

←

W R/W Control and status group

R/W
R/W
R/W
R/W
R/W
R/W Memory pointer group
R/W
R/W
R/W

ED
HcBulkHeadED 0x49000028
HcBulkCurrentED 0x4900002C
HcDoneHead 0x49000030

R/W
R/W

R/W Frame counter group
HcRmInterval 0x49000034 R/W
HcFmRemaining 0x49000038 R/W
HcFmNumber 0x4900003C R/W
HcPeriodicStart 0x49000040 R/W
HcLSThreshold 0x49000044 R/W
HcRhDescriptorA 0x49000048 R/W Root hub group
HcRhDescriptorB 0x4900004C R/W
HcRhStatus 0x49000050 R/W
HcRhPortStatus1 0x49000054 R/W
HcRhPortStatus2 0x49000058 R/W
Interrupt Controller
SRCPND 0X4A000000

←

W R/W Interrupt request status
INTMOD 0X4A000004 R/W Interrupt mode control
INTMSK 0X4A000008 R/W Interrupt mask control
PRIORITY 0X4A00000C R/W IRQ priority control
INTPND 0X4A000010 R/W Interrupt request status
INTOFFSET 0X4A000014 R Interrupt request source offset
SUBSRCPND 0X4A000018 R/W Sub source pending
INTSUBMSK 0X4A00001C R/W Interrupt sub mask

1-40

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

DMA

DISRC0 0x4B000000 ← W R/W DMA 0 initial source
DISRCC0 0x4B000004
DIDST0 0x4B000008
DIDSTC0 0x4B00000C
DCON0 0x4B000010
DSTAT0 0x4B000014
DCSRC0 0x4B000018
DCDST0 0x4B00001C
DMASKTRIG0 0x4B000020
DMAREQSEL0 0x4B000024

R/W DMA 0 initial source control
R/W DMA 0 initial destination
R/W DMA 0 initial destination control
R/W DMA 0 control
R DMA 0 count
R DMA 0 current source
R DMA 0 current destination
R/W DMA 0 mask trigger

R/W DMA0 Request Selection Register
DISRC1 0x4B000100 ← W R/W DMA 1 initial source
DISRCC1 0x4B000104
DIDST1 0x4B000108
DIDSTC1 0x4B00010C
DCON1 0x4B000110
DSTAT1 0x4B000114
DCSRC1 0x4B000118
DCDST1 0x4B00011C
DMASKTRIG1 0x4B000120
DMAREQSEL1 0x4B000124

R/W DMA 1 initial source control

R/W DMA 1 initial destination

R/W DMA 1 initial destination control

R/W DMA 1 control

R DMA 1 count

R DMA 1 current source

R DMA 1 current destination

R/W DMA 1 mask trigger

R/W DMA1 Request Selection Register
DISRC2 0x4B000200 ← W R/W DMA 2 initial source
DISRCC2 0x4B000204
DIDST2 0x4B000208
DIDSTC2 0x4B00020C
DCON2 0x4B000210
DSTAT2 0x4B000214
DCSRC2 0x4B000218
DCDST2 0x4B00021C
DMASKTRIG2 0x4B000220
DMAREQSEL2 0x4B000224

R/W DMA 2 initial source control

R/W DMA 2 initial destination

R/W DMA 2 initial destination control

R/W DMA 2 control

R DMA 2 count

R DMA 2 current source

R DMA 2 current destination

R/W DMA 2 mask trigger

R/W DMA2 Request Selection Register

1-41

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

DISRC3 0x4B000300 ← W R/W DMA 3 initial source
DISRCC3 0x4B000304
DIDST3 0x4B000308
DIDSTC3 0x4B00030C
DCON3 0x4B000310
DSTAT3 0x4B000314
DCSRC3 0x4B000318
DCDST3 0x4B00031C
DMASKTRIG3 0x4B000320
DMAREQSEL3 0x4B000324

R/W DMA 3 initial source control
R/W DMA 3 initial destination
R/W DMA 3 initial destination control
R/W DMA 3 control
R DMA 3 count
R DMA 3 current source
R DMA 3 current destination
R/W DMA 3 mask trigger

R/W DMA3 Request Selection Register
DISRC4 0x4B000400 ← W R/W DMA 4 initial source
DISRCC4 0x4B000404
DIDST4 0x4B000408
DIDSTC4 0x4B00040C
DCON4 0x4B000410
DSTAT4 0x4B000414
DCSRC4 0x4B000418
DCDST4 0x4B00041C
DMASKTRIG4 0x4B000420
DMAREQSEL4 0x4B000424
DISRC5 0x4B000500
DISRCC5 0x4B000504
DIDST5 0x4B000508
DIDSTC5 0x4B00050C
DCON5 0x4B000510
DSTAT5 0x4B000514
DCSRC5 0x4B000518
DCDST5 0x4B00051C
DMASKTRIG5 0x4B000520
DMAREQSEL5 0x4B000524

←

R/W DMA 4 initial source control

R/W DMA 4 initial destination

R/W DMA 4 initial destination control

R/W DMA 4 control

R DMA 4 count

R DMA 4 current source

R DMA 4 current destination

R/W DMA 4 mask trigger

R/W DMA4 Request Selection Register

W R/W DMA 5 initial source

R/W DMA 5 initial source control

R/W DMA 5 initial destination

R/W DMA 5 initial destination control

R/W DMA 5 control

R DMA 5 count

R DMA 5 current source

R DMA 5 current destination

R/W DMA 5 mask trigger

R/W DMA5 Request Selection Register

1-42

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Syscon

LOCKCON0 0x4C00_0000

←

W R/W MPLL lock time count register
LOCKCON1 0x4C00_0004 EPLL lock time count register
OSCSET 0x4C00_0008 Oscillator stabilization control register
Reserved 0x4C00_000C Reserved
MPLLCON 0x4C00_0010 MPLL configuration register
RESERVED 0x4C00_0014 RESERVED
EPLLCON 0x4C00_0018 EPLL configuration register
CLKSRC 0x4C00_0020 Clock source control register
CLKDIV0 0x4C00_0024 Clock divider ratio control register0
CLKDIV1 0x4C00_0028 Clock divider ratio control register1
HCLKCON 0x4C00_0030 HCLK enable register
PCLKCON 0x4C00_0034 PCLK enable register
SCLKCON 0x4C00_0038 Special clock enable register
RESERVED 0x4C00_003C Reserved
PWRMODE 0x4C00_0040 Power mode control register
SWRST 0x4C00_0044 Software reset control register
BUSPRI0 0x4C00_0050 Bus priority control register 0
SYSID 0x4C00_005C R System ID register

PWRCFG 0x4C00_0060

R/W Power management configuration

register
RSTCON 0x4C00_0064 Reset control register
RSTSTAT 0x4C00_0068 R Reset status register
WKUPSTAT 0x4C00_006C R/W Wake-up status register
INFORM0 0x4C00_0070 SLEEP mode information register 0
INFORM1 0x4C00_0074 SLEEP mode information register 1
INFORM2 0x4C00_0078 SLEEP mode information register 2
INFORM3 0x4C00_007C SLEEP mode information register 3
PHYCTRL 0x4C00_0080 usb phy control register
PHYPWR 0x4C00_0084 usb phy power control register
URSTCON 0x4C00_0088 usb phy reset control register
UCLKCON 0x4C00_008C usb phy clock control register

1-43

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/
Write

Function

TFT LCD Controller

VIDCON0 0x4C80_0000 R/W Video control 0 register
VIDCON1 0x4C80_0004 Video control 1 register
VIDTCON0 0x4C80_0008 Video time control 0 register
VIDTCON1 0x4C80_000C Video time control 1 register
VIDTCON2 0x4C80_0010 Video time control 2 register
WINCON0 0x4C80_0014 Window control 0 register
WINCON1 0x4C80_0018 Window control 1 register
VIDOSD0A 0x4C80_0028 Video Window 0’s position control

register

VIDOSD0B 0x4C80_002C Video Window 0’s position control

register

VIDOSD0C 0x4C80_0030 Video Window 0’s position control

register

VIDOSD1A 0x4C80_0034 Video Window 1’s position control

register

VIDOSD1B 0x4C80_0038 Video Window 1’s position control

register

VIDOSD1C 0x4C80_003C Video Window 1’s position control

register

VIDW00ADD0B0 0x4C80_0064 Window 0’s buffer start address

register, buffer 0

VIDW00ADD0B1 0x4C80_0068 Window 0’s buffer start address

register, buffer 1

VIDW01ADD0 0x4C80_006C Window 1’s buffer start address

register

VIDW00ADD1B0 0x4C80_007C Window 0’s buffer end address

register, buffer 0

VIDW00ADD1B1 0x4C80_0080 Window 0’s buffer end address

register, buffer 1

VIDW01ADD1 0x4C80_0084 Window 1’s buffer end address

register

VIDW00ADD2B0 0x4C80_0094 Window 0’s buffer size register, buffer

0

VIDW00ADD2B1 0x4C80_0098 Window 0’s buffer size register, buffer

1

VIDW01ADD2 0x4C80_009C Window 1’s buffer size register

1-44

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

VIDINTCON 0x4C80_00AC Indicate the Video interrupt control

register
W1KEYCON0 0x4C80_00B0 Color key control register
W1KEYCON1 0x4C80_00B4 Color key value (transparent value)

register
W2KEYCON0 0x4C80_00B8 Color key control register
W2KEYCON1 0x4C80_00BC Color key value (transparent value)

register
W3KEYCON0 0x4C80_00C0 Color key control register
W3KEYCON1 0x4C80_00C4 Color key value (transparent value)

register
W4KEYCON0 0x4C80_00C8 Color key control register
W4KEYCON1 0x4C80_00CC Color key value (transparent value)

register
WIN0MAP 0x4C80_00D0 Window color control
WIN1MAP 0x4C80_00D4 Window color control
WPALCON 0x4C80_00E4 Window Palette control register
SYSIFCON0 0x4C80_0130 System Interface control for Main LDI
SYSIFCON1 0x4C80_0134 System Interface control for Sub LDI
DITHMODE1 0x4C80_0138 Dithering mode register.
rSIFCCON0 0x4C80_013C System interface command control
rSIFCCON1 0x4C80_0140 SYS IF command data write control
rSIFCCON2 0x4C80_0144 SYS IF command data read control
rCPUTRIGCON1 0x4C80_015C CPU trigger source mask
rCPUTRIGCON2 0x4C80_0160 Software based trigger control
rVIDW00ADD0B1 0x4C80_0068 Window 0’s buffer start ADDR
rVIDW01ADD0 0x4C80_006C Window 1’s buffer start ADDR

1-45

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

CSTN LCD Controller

LCDCON1 0X4D000000
LCDCON2 0X4D000004
LCDCON3 0X4D000008
LCDCON4 0X4D00000C
LCDCON5 0X4D000010
LCDSADDR1 0X4D000014

LCDSADDR2 0X4D000018

LCDSADDR3 0X4D00001C
REDLUT 0X4D000020
GREENLUT 0X4D000024
BLUELUT 0X4D000028
DITHMODE 0X4D00004C
LCDINTPND 0X4D000054

LCDSRCPND 0X4D000058

LCDINTMSK 0X4D00005C

←

←

Acc.

Unit

Read/
Write

Function

W R/W LCD control 1 register

R/W LCD control 2 register
R/W LCD control 3 register
R/W LCD control 4 register
R/W LCD control 5 register

W R/W STN/TFT: Frame buffer start address 1

register

R/W STN/TFT: Frame buffer start address 2

register
R/W STN/TFT: Virtual screen address set
R/W STN: Red lookup table register
R/W STN: Green lookup table register
R/W STN: Blue lookup table register
R/W Dithering Mode Register
Indicate the LCD interrupt pending

register
Indicate the LCD interrupt source

pending register
Determine which interrupt source is

masked.

The masked interrupt source will not

be serviced.

1-46

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

NAND Flash

NFCONF 0x4E000000
NFCONT 0x4E000004
NFCMMD 0x4E000008
NFADDR 0x4E00000C
NFDATA 0x4E000010
NFMECCD0 0x4E000014
NFMECCD1 0x4E000018
NFSECCD 0x4E00001C
NFSBLK 0x4E000020

NFEBLK 0x4E000024

NFSTAT 0x4E000028
NFECCERR0 0x4E00002C
NFECCERR1 0x4E000030
NFMECC0 0x4E000034
NFMECC1 0x4E000038
NFSECC 0x4E00003C

NFMLCBITPT 0x4E000040

←

Acc.

Unit

Read/

Write

Function

W R/W Configuration register

Control register
Command register
Address register
Data register
1st and 2nd main ECC data register
3rd and 4th main ECC data register
Spare ECC read register
Programmable start block address

register

Programmable end block address

register
R NAND status registet
R ECC error status0 register
R ECC error status1 register
R Generated ECC status0 register
R Generated ECC status1 register
R Generated Spare area ECC status

register
R 4-bit ECC error bit pattern register

1-47

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Camera Interface

CISRCFMT 0x4D80_0000
CIWDOFST 0x4D80_0004
CIGCTRL 0x4D80_0008

←

W RW Input source format

Window offset register

Global control register
CIDOWSFT2 0x4D80_0014 Window option register 2
CICOYSA1 0x4D80_0018

Y 1st frame start address for codec

DMA

CICOYSA2 0x4D80_001C

Y 2nd frame start address for codec

DMA

CICOYSA3 0x4D80_0020

Y 3rd frame start address for codec

DMA

CICOYSA4 0x4D80_0024

Y 4th frame start address for codec

DMA

CICOCBSA1 0x4D80_0028

Cb 1st frame start address for codec

DMA

CICOCBSA2 0x4D80_002C

Cb 2nd frame start address for codec

DMA

CICOCBSA3 0x4D80_0030

Cb 3rd frame start address for codec

DMA

CICOCBSA4 0x4D80_0034

Cb 4th frame start address for codec

DMA

CICOCRSA1 0x4D80_0038

Cr 1st frame start address for codec

DMA

CICOCRSA2 0x4D80_003C

Cr 2nd frame start address for codec

DMA

CICOCRSA3 0x4D80_0040

Cr 3rd frame start address for codec

DMA

CICOCRSA4 0x4D80_0044

Cr 4th frame start address for codec

DMA
CICOTRGFMT 0x4D80_0048
CICOCTRL 0x4D80_004C
CICOSC

0x4D80_0050

Target image format of codec DMA
Codec DMA control related
Codec pre-scaler ratio control

PRERATIO
CICOSCPREDST 0x4D80_0054
CICOSCCTRL 0x4D80_0058
CICOTAREA 0x4D80_005C
CICOSTATUS 0x4D80_0064

Codec pre-scaler destination format
Codec main-scaler control
Codec scaler target area

Codec path status

1-48

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

CIPRCLRSA1 0x4D80_006C

Address

(B. Endian)

Address

(L.Endian)

Acc.
Unit

Read/
Write

Function

RGB 1st frame start address for

preview DMA

CIPRCLRSA2 0x4D80_0070

RGB 2nd frame start address for

preview DMA

CIPRCLRSA3 0x4D80_0074

RGB 3rd frame start address for

preview DMA

CIPRCLRSA4 0x4D80_0078

RGB 4th frame start address for

preview DMA
CIPRTRGFMT 0x4D80_007C
CIPRCTRL 0x4D80_0080
CIPRSCPRERATIO 0x4D80_0084
CIPRSCPREDST 0x4D80_0088
CIPRSCCTRL 0x4D80_008C
CIPRTAREA 0x4D80_0090
CIPRSTATUS 0x4D80_0098

Target image format of preview DMA
Preview DMA control related
Preview pre-scaler ratio control
Preview pre-scaler destination format
Preview main-scaler control
Preview scaler target area

Preview path status
CIIMGCPT 0x4D80_00A0 Image capture enable command
CICOCPTSEQ 0x4D80_00A4
CICOSCOS 0x4D80_00A8

Codec dma capture sequence related

Codec scan line offset related
CIIMGEFF 0x4D80_00B0 Image Effects related
CIMSYSA 0x4D80_00B4 MSDMA Y start address related
CIMSCBSA 0x4D80_00B8
CIMSCRSA 0x4D80_00BC
CIMSYEND 0x4D80_00C0
CIMSCBEND 0x4D80_00C4
CIMSCREND 0x4D80_00C8
CIMSYOFF 0x4D80_00CC
CIMSCBOFF 0x4D80_00D0
CIMSCROFF 0x4D80_00D4
CIMSWIDTH 0x4D80_00D8
CIMSCTRL 0x4D80_00DC

MSDMA Cb start address related

MSDMA Cr start address related

MSDMA Y end address related

MSDMA Cb end address related

MSDMA Cr end address related

MSDMA Y offset related

MSDMA Cb offset related

MSDMA Cr offset related

MSDMA source image width related

MSDMA control register

1-49

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

UART

ULCON0 0x50000000

←

W R/W UART 0 line control
UCON0 0x50000004 UART 0 control
UFCON0 0x50000008
UMCON0 0x5000000C
UTRSTAT0 0x50000010
UERSTAT0 0x50000014
UFSTAT0 0x50000018

UART 0 FIFO control
UART 0 modem control
R UART 0 Tx/Rx status
UART 0 Rx error status

UART 0 FIFO status
UMSTAT0 0x5000001C UART 0 modem status
UTXH0 0x50000023 0x50000020 B W UART 0 transmission hold
URXH0 0x50000027 0x50000024 R UART 0 receive buffer
UBRDIV0 0x50000028
UDIVSLOT0 0x5000002C

←

W R/W UART 0 baud rate divisor

Baud rate divisior(decimal place)

register 0

ULCON1 0x50004000

UART 1 line control
UCON1 0x50004004 UART 1 control
UFCON1 0x50004008
UMCON1 0x5000400C
UTRSTAT1 0x50004010
UERSTAT1 0x50004014
UFSTAT1 0x50004018

UART 1 FIFO control

UART 1 modem control
R UART 1 Tx/Rx status
UART 1 Rx error status

UART 1 FIFO status
UMSTAT1 0x5000401C UART 1 modem status
UTXH1 0x50004023 0x50004020 B W UART 1 transmission hold
URXH1 0x50004027 0x50004024 R UART 1 receive buffer
UBRDIV1 0x50004028
UDIVSLOT1 0x500402C

←

W R/W UART 1 baud rate divisor

Baud rate divisior(decimal place)

register 1
ULCON2 0x50008000
UCON2 0x50008004
UFCON2 0x50008008

UART 2 line control
UART 2 control

UART 2 FIFO control
UTRSTAT2 0x50008010 R UART 2 Tx/Rx status
UERSTAT2 0x50008014 UART 2 Rx error status
UFSTAT2 0x50008018

UART 2 FIFO status
UTXH2 0x50008023 0x50008020 B W UART 2 transmission hold
URXH2 0x50008027 0x50008024 R UART 2 receive buffer

1-50

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

UBRDIV2 0x50008028
UDIVSLOT2 0x500802C

Address

(B. Endian)

Address

(L. Endian)

←

Acc.

Unit

Read/

Write

Function

W R/W UART 2 baud rate divisor

Baud rate divisior(decimal place)

register 2

ULCON3 0x5000C000

UART 3 line control
UCON3 0x5000C004 UART 3 control
UFCON3 0x5000C008 UART 3 FIFO control
UTRSTAT3 0x5000C010 R UART 3 Tx/Rx status
UERSTAT3 0x5000C014 UART 3 Rx error status
UFSTAT3 0x5000C018

UART 3 FIFO status
UTXH3 0x5000C023 0x5000C020 B W UART 3 transmission hold
URXH3 0x5000C027 0x5000C024 R UART 3 receive buffer
UBRDIV3 0x5000C028
UDIVSLOT3 0x500C02C

←

W R/W UART 3 baud rate divisor

Baud rate divisior(decimal place)

register 3
PWM Timer
TCFG0 0x51000000 ← W R/W Timer configuration
TCFG1 0x51000004
TCON 0x51000008
TCNTB0 0x5100000C
TCMPB0 0x51000010
TCNTO0 0x51000014
TCNTB1 0x51000018
TCMPB1 0x5100001C
TCNTO1 0x51000020
TCNTB2 0x51000024
TCMPB2 0x51000028
TCNTO2 0x5100002C
TCNTB3 0x51000030

Timer configuration
Timer control
Timer count buffer 0
Timer compare buffer 0
R Timer count observation 0
R/W Timer count buffer 1
Timer compare buffer 1
R Timer count observation 1
R/W Timer count buffer 2
Timer compare buffer 2
R Timer count observation 2

R/W Timer count buffer 3
TCMPB3 0x51000034 Timer compare buffer 3
TCNTO3 0x51000038
TCNTB4 0x5100003C
TCNTO4 0x51000040

R Timer count observation 3

R/W Timer count buffer 4

R Timer count observation 4

1-51

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/
Write

Function

USB Device

IR 0x4980_0000 R/W Index Register
EIR 0x4980_0004 R/W Endpoint Interrupt Register
EIER 0x4980_0008 R/W Endpoint Interrupt Enable Register
FAR 0x4980_000C R Function Address Register
FNR 0x4980_0010 R Frame Number Register
EDR 0x4980_0014 R/W Endpoint Direction Register
TR 0x4980_0018 R/W Test Register
SSR 0x4980_001C R/W System Status Register
SCR 0x4980_0020 R/W System Control Register
EP0SR 0x4980_0024 R/W EP0 Status Register
EP0CR 0x4980_0028 R/W EP0 Control Register
EP0BR 0x4980_0060 R/W EP0 Buffer Register
EP1BR 0x4980_0064 R/W EP1 Buffer Register
EP2BR 0x4980_0068 R/W EP2 Buffer Register
EP3BR 0x4980_006C R/W EP3 Buffer Register
EP4BR 0x4980_0070 R/W EP4 Buffer Register
EP5BR 0x4980_0074 R/W EP5 Buffer Register
EP6BR 0x4980_0078 R/W EP6 Buffer Register
EP7BR 0x4980_007C R/W EP7 Buffer Register
EP8BR 0x4980_0080 R/W EP8 Buffer Register
FCON 0x4980_0100 R/W Burst FIFO-DMA Control
FSTAT 0x4980_0104 R Burst FIFO status
ESR 0x4980_002C R/W Endpoints Status Register
ECR 0x4980_0030 R/W Endpoints Control Register
BRCR 0x4980_0034 R Byte Read Count Register
BWCR 0x4980_0038 R/W Byte Write Count Register
MPR 0x4980_003C R/W Max Packet Register
DCR 0x4980_0040 R/W DMA Control Register
DTCR 0x4980_0044 R/W DMA Transfer Counter Register
DFCR 0x4980_0048 R/W DMA FIFO Counter Register
DTTCR1 0x4980_004C R/W DMA Total Transfer Counter1 Register
DTTCR2 0x4980_0050 R/W DMA Total Transfer Counter2 Register
MICR 0x4980_0084 R/W Master Interface Control Register
MBAR 0x4980_0088 R/W Memory Base Address Register
MCAR 0x4980_008C R Memory Current Address Register

1-52

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Watchdog Timer

WTCON 0x53000000

←

W R/W Watchdog timer mode
WTDAT 0x53000004 Watchdog timer data
WTCNT 0x53000008 Watchdog timer count
IIC
IICCON 0x54000000
IICSTAT 0x54000004
IICADD 0x54000008

←

W R/W IIC control

IIC status

IIC address
IICDS 0x5400000C IIC data shift
IICLC 0x54000010 IIC multi-master line control
IIS
IISCON 0x55000000 W R/W IIS control
IISMOD 0x55000004 IIS mode
I2SFIC 0x55000008 I2S interface FIFO control register
I2SPSR 0x5500000C I2S interface clock divider control

register
I2STXD 0x55000010 W I2S interface transmit data register
I2SRXD 0x55000014 R I2S interface receive data register

1-53

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/
Write

Function

I/O port

GPACDL 0x56000000
GPACDH 0x56000004
GPBCON 0x56000010

←

W R/W Port A control & Data
Port A control & Data
Port B control

GPBDAT 0x56000014 Port B data
GPBUDP 0x56000018
GPCCON 0x56000020

Pull-up/down control B
Port C control

GPCDAT 0x56000024 Port C data
GPCUDP 0x56000028
GPDCON 0x56000030

Pull-up/down control C
Port D control

GPDDAT 0x56000034 Port D data
GPDUDP 0x56000038
GPECON 0x56000040

Pull-up/down control D
Port E control

GPEDAT 0x56000044 Port E data
GPEUDP 0x56000048
GPFCON 0x56000050

Pull-up/down control E
Port F control

GPFDAT 0x56000054 Port F data
GPGCON 0x56000060
GPGDAT 0x56000064
GPGUDP 0x56000068
GPHCON 0x56000070

Port G control
Port G data
Pull-up/down control G
Port H control

GPHDAT 0x56000074 Port H data
GPHUDP 0x56000078

Pull-up/down control H

GPJCON 0x560000D0 Port J control
GPJDAT 0x560000D4 Port J data
GPJUDP 0x560000D8 Pull-up/down control J

- 0x560000E0

- 0x560000E4
DATAPDEN 0x560000E8
GPLCON 0x560000F0

-

-

- - -

- - ­ Pull-up/down control SDATA/RDATA
Port L control

GPLDAT 0x560000F4 Port L data
GPLUDP 0x560000F8 Pull-up/down control L
GPMCON 0x56000100
GPMDAT 0x56000104

Port M control
Port M data

1-54

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

GPMUDP 0x56000108
MISCCR 0x56000080
DCLKCON 0x56000084
EXTINT0 0x56000088
EXTINT1 0x5600008C
EXTINT2 0x56000090
EINTFLT2 0x5600009c
EINTFLT3 0x4c6000a0
EINTMASK 0x4c6000a4
EINTPEND 0x560000a8

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Pull-up/down control M
Miscellaneous control
DCLK0/1 control
External interrupt control register 0
External interrupt control register 1
External interrupt control register 2
External interrupt control register 2
External interrupt control register 3
External interrupt mask register

External interrupt pending register
GSTATUS0 0x560000ac External pin status
GSTATUS1 0x560000b0 Chip ID
DSC0 0x560000c0 Strength control register 0
DSC1 0x560000c4 Strength control register 1
DSC2 0x560000c8 Strength control register 2
MSLCON 0x560000cc Memory I/F HiZ control register
DATAPEN 0x560000e8 Pull down control for S/RDATA
RTC
RTCCON 0x57000043 0x57000040 B R/W RTC control
TICNT0 0x57000047 0x57000044 Tick time count register 0
TICNT1 0x5700004F 0x5700004C Tick time count register 1
RTCALM 0x57000053 0x57000050 RTC alarm control
ALMSEC 0x57000057 0x57000054 Alarm second
ALMMIN 0x5700005B 0x57000058 Alarm minute
ALMHOUR 0x5700005F 0x5700005C Alarm hour
ALMDATE 0x57000063 0x57000060 Alarm day
ALMMON 0x57000067 0x57000064 Alarm month
ALMYEAR 0x5700006B 0x57000068 Alarm year
BCDSEC 0x57000073 0x57000070 BCD second
BCDMIN 0x57000077 0x57000074 BCD minute
BCDHOUR 0x5700007B 0x57000078 BCD hour
BCDDATE 0x5700007F 0x5700007C BCD day
BCDDAY 0x57000083 0x57000080 BCD date
BCDMON 0x57000087 0x57000084 BCD month
BCDYEAR 0x5700008B 0x57000088 BCD year
TICKCNT 0x57000090 W R Internal tick time counter
RTCLBAT 0x57000097 0x57000094 B R/W RTC LOW battery check

1-55

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/
Write

Function

A/D Converter

ADCCON 0x58000000
ADCTSC 0x58000004

←

W R/W ADC control

ADC touch screen control
ADCDLY 0x58000008 ADC start or interval delay
ADCDAT0 0x5800000C R ADC conversion data
ADCDAT1 0x58000010 ADC conversion data
ADCUPDN 0x58000014 R/W Stylus up or down interrupt status
ADCMUX 0x58000018 R/W Analog input channel select
SPI(SPI Channel 1)
SPCON1 0x59000000

←

W R/W SPI Channel 1 control
SPSTA1 0x59000004 R SPI Channel 1 status
SPPIN1 0x59000008 R/W SPI Channel 1 pin control
SPPRE1 0x5900000C SPI Channel 1 baud rate prescaler
SPTDAT1 0x59000010 SPI Channel 1 Tx data
SPRDAT1 0x59000014 R SPI Channel 1 Rx data
SPTXFIFO1 0x59000018 W SPI Channel 1 Tx FIFO Register
SPRXFIFO1 0x5900001C R SPI Channel 1 Rx FIFO Register
SPRDATB1 0x59000020 R SPI Channel 1 Rx Data Register
SPFIC1 0x59000024 R/W SPI Channel 1 FIFO Interrupt and

DMA control Register

SPTOV1 0x59000028 R/W SPI Channel 1 Rx FIFO Timeout Value

Register
SD/MMC Interface (SD/MMC Channel 1)
SDICON 0x5A000000

←

W R/W SDI control
SDIPRE 0x5A000004 SDI baud rate prescaler
SDICARG 0x5A000008 SDI command argument
SDICCON 0x5A00000C SDI command control
SDICSTA 0x5A000010 R/(C) SDI command status
SDIRSP0 0x5A000014 R SDI response
SDIRSP1 0x5A000018 SDI response
SDIRSP2 0x5A00001C SDI response
SDIRSP3 0x5A000020 SDI response
SDIDTIMER 0x5A000024 R/W SDI data / busy timer
SDIBSIZE 0x5A000028 SDI block size
SDIDCON 0x5A00002C

SDI data control
SDIDCNT 0x5A000030 R SDI data remain counter
SDIDSTA 0x5A000034 R/(C) SDI data status
SDIFSTA 0x5A000038 R SDI FIFO status
SDIIMSK 0x5A00003C

←

W SDI interrupt mask

SDIDAT 0x5A000043 0x5A000040 B R/W SDI data

1-56

S3C2443X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

HSSPI(SPI Channel 0)

CH_CFG 0x52000000 R/W SPI configuration register
Clk_CFG 0x52000004 Clock configuration register
MODE_CFG 0x52000008 SPI FIFO control register
Slave_slection_reg 0x5200000C Slave selection signal
SPI_INT_EN 0x52000010 SPI Interrupt Enable register
SPI_STATUS 0x52000014 SPI status register
SPI_TX_DATA 0x52000018 SPI TX DATA register
SPI_RX_DATA 0x5200001C SPI RX DATA register
Packet_Count_reg 0x52000020 Count how many data master gets
Pending_clr_reg 0x52000024 Pending clear register
HSMMC(SD/MMC Channel 0)
SYSAD 0x4A800000

←

R/W SDI control register

BLKSIZE 0x4A800004 Host DMA Buffer Boundary and

Transfer Block Size Register
BLKCNT 0x4A800006 Blocks Count For Current Transfer
ARGUMENT 0x4A800008 Command Argument Register
TRNMOD 0x4A80000C Transfer Mode Setting Register
CMDREG 0x4A80000E Command Register
RSPREG0 0x4A800010 Response Register 0
RSPREG1 0x4A800014 Response Register 1
RSPREG2 0x4A800018 Response Register 2
RSPREG3 0x4A80001C Response Register 3
BDATA 0x4A800020 Buffer Data Register
PRNSTS 0x4A800024 Present State Register
HOSTCTL 0x4A800028 Present State Register
PWRCON 0x4A800029 Present State Register
BLKGAP 0x4A80002A Block Gap Control Register
WAKCON 0x4A80002B Wakeup Control Register
CLKCON 0x4A80002C Command Register
TIMEOUTCON 0x4A80002E Timeout Control Register
SWRST 0x4A80002F Software Reset Register
NORINTSTS 0x4A800030 Normal Interrupt Status Register
ERRINTSTS 0x4A800032 Error Interrupt Status Register

1-57

PRODUCT OVERVIEW S3C2443X RISC MICROPROCESSOR

Table 1-5. S3C2443X Special Registers (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/
Write

Function

NORINTSTSEN 0x4A800034 Normal Interrupt Status Enable

Register
ERRINTSTSEN 0x4A800036 Error Interrupt Status Enable Register
NORINTSIGEN 0x4A800038 Normal Interrupt Signal Enable

Register
ERRINTSIGEN 0x4A80003A Error Interrupt Signal Enable Register
ACMD12ERRSTS 0x4A80003C Auto CMD12 Error Status Register
CAPAREG 0x4A800040 Capabilities Register
MAXCURR 0x4A800048 Maximum Current Capabilities

Register
CONTROL2 0x4A800080 Control register 2

CONTROL3 0x4A800084

FIFO Interrupt Control (Control

Register 3)
HCVER 0x4A8000FE Host Controller Version Register
AC97 Audio-CODEC Interface
AC_GLBCTRL 0x5B000000

←

W R/W AC97 global control register
AC_GLBSTAT 0x5B000004 R AC97 global status register
AC_CODEC_CMD 0x5B000008 R/W AC97 codec command register
AC_CODEC_STAT 0x5B00000C R AC97 codec status register

AC_PCMADDR 0x5B000010

AC_MICADDR 0x5B000014

AC_PCMDATA 0x5B000018

AC_MICDATA 0x5B00001C

AC97 PCM out/in channel FIFO

address register

AC97 mic in channel FIFO address

register

R/W AC97 PCM out/in channel FIFO data

register

AC97 MIC in channel FIFO data

register

Cautions on S3C2443X Special Registers

1. In the little endian mode ‘L’, endian address must be used. In the big endian mode ‘B’ endian address must be
used.

2. The special registers have to be accessed for each recommended access unit.

3. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32-bit)
in little/big endian.

4. Make sure that the ADC registers, RTC registers and UART registers be read/write by the specified access
unit and the specified address. Moreover, one must carefully consider which endian mode is used.

5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer (int *).
HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer (short int *).
B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer (char int *).

1-58

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

2 SYSTEM CONTROLLER

OVERVIEW

The system controller consists of three parts; reset control, system clock control, and system power-management
control. The system clock control logic in S3C2443X can generate the required system clock signals which are the
inputs of ARM920T, several AHB blocks, and APB blocks. There are two PLLs in S3C2443X to generate internal
clocks. One is for general functional blocks, which include ARM, AHB, and APB. The other is for the special
functional clocks which are the USB, I2S and camera interface clock. Software program control the operating
frequency of the PLLs, internal clock sources and enabled or disabled the clocks to reduce the power
consumption.

S3C2443X has various power-down modes to keep optimal power consumption for a given task. The power-down
modes consists of four modes; NORMAL mode, IDLE mode, STOP mode, and SLEEP mode. In NORMAL mode,
the input clock of each block is enabled or disabled according to the software to eliminate the power consumption
of unused blocks for a certain application. For example, if an UART is not needed, the software can disable the
input clock independently. The major power dissipation of S3C2443X is due to ARM core, since the operating
speed is relative higher than that of the other blocks. Typically, the operating frequency of the ARM core is
533MHz, while the AHB blocks and the APB blocks operate on 133MHz and 66MHz, respectively. Thus, the
power control of the ARM core is major issue to reduce the overall power dissipation in S3C2443X, and IDLE
mode is supported for this purpose. In IDLE mode, the ARM core is not operated until the external interrupts or
internal interrupts. The STOP mode freezes all clocks to all peripherals as well as the ARM core by disabling
PLLs. The power consumption is only due to the leakage current and the minimized alive block in S3C2443X.
SLEEP mode is intended to disconnect the internal power. So, the power consumption due to the ARM core and
the internal logic except the wake-up logic will be nearly zero in the SLEEP mode. In order to use the SLEEP
mode two indenpendent power sources are required. One of the two power soruces supplies the power for the
wake-up logic. The other one supplies the normal functional blocks including the ARM core. It should be controlled
in order to turn ON/OFF with a special pin in S3C2443X. The detailed description of the power-saving modes such
as the entering sequence to the specific power-down mode or the wake-up sequence from a power-down mode is
given in the following Power Management section.

FEATURE

• Include two on-chip PLLs called main PLL(MPLL), extra PLL(EPLL)

• MPLL generates the system reference clock

• EPLL generates the clocks for the special functional blocks

• Independent clock ON/OFF control to reduce power consumption

• Support three power-down modes, IDLE, STOP, and SLEEP, to optimize the power dissipation

• Wake-up by one of external Interrupt, RTC alarm, Tick interrupt and BATT_FLT.(Stop and Sleep mode)

• Control internal bus arbitration priority

2-1

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

BLOCK DIAGRAM

off-part alive-part

Clocks

Clock

Generator

AHB

Glue

Power Management

Register

Signal

Masking

Power Management

Glue

Register

Reset

Control

Reset

Power
ON/OFF

Figure 2-1. System controller block diagram

Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are
the OFF block and the ON block. Since the system controller must be alive when the external power supply is
disabled. The ALIVE-part is supplied by an auxiliary power source and waits until external/internal interrupts.
However, the OFF-part is disabled when the power-down mode is SLEEP. The clock generator makes all internal
clocks, which include ARMCLK for the ARM core, HCLK for the AHB blocks, PCLK for the APB block, and other
special clocks. The special functional registers (SFR) are located at the register blocks, and their values are
configured through AHB interface. If a software want to change into a power-down mode, then the power
management blocks detect the values within the SFR and change the mode. In addition, they assert the external
power ON/OFF signal if required. All reset signals are generated at the reset control block.

The detailed explanations for each block will be described in the following sections.

2-2

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

FUNCTIONAL DESCRIPTIONS

The system controller for S3C2443X has three functions, which include the reset management, the clock
generation, and the power management. In this section, the behavior will be described.

Reset Management

When S3C2443X is power-on, the external device must assert reset to initialize internal states.

Reset Types

S3C2443X has four types of resets and reset controller in system controller can place the system into the
predefined states with one of the following four resets.

• Hardware Reset – It is generated when nRESET pin is asserted. It is an uncompromised, unmaskable, and
complete reset, which is used when you need no information in system any more.

• Watchdog Reset – The watchdog timer monitors the device state and generates the watchdog reset when the
state is abnormal.

• Software Reset – Software can initialize the internal state by writing the special control register (SWRST).

• Wakeup Reset – When the system wakes up from SLEEP mode, it generates reset signals.

Hardware Reset

Hardware reset is invoked when the nRESET pin is asserted and all units in the system (except RTC) are
initialized to known states. During the hardware reset, the following actions will occur:

• All internal registers and ARM920T core goes into their pre-defined initial state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted while the reset is progressed.

When the unmaskable nRESET pin is asserted as low, the internal hardware reset signal is generated. Upon
assertion of nRESET, S3C2443X enters into reset state regardless of the previous state. To enter hardware reset
state, nRESET must be held long enough to allow internal stabilization and propagation of the reset state.

Caution: An external power source, regulator, for S3C2443X must be stable prior to the deassertion of nRESET.
Otherwise, it damages to S3C2443X and its operation will not be guaranteed.

Figure 2-2 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation
within several milliseconds after the power source supplies enough power-level to S3C2443X. Initially, two internal
PLLs (MPLL and EPLL) stop. The nRESET pin should be released after the fully settle-down of the power supply­level. S3C2443X requires a hazard-free system clock (SYSCLK, ARMCLK, HCLK, and PCLK) to operate properly
when the system reset is released. Since the PLL does not work initially, the PLL input clock (F
SYSCLK instead of the PLL output clock (F

). Software must configure MPLLCON and EPLLCON register to

OUT

) is directly fed to

IN

use each PLL. The PLL begins the lockup sequence toward the new frequency only after the S/W configures the
PLL with a new frequency-value. The PLL output is immediately fed to SYSCLK after lock time.

You should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the
power-up sequence and the crystal oscillation must be settle-down during this period. However, S3C2443X will
explicitly add the crystal oscillator settle-down time (XTALWAIT) when it wakes up from the STOP mode.

2-3

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

The EPLL output clock is directly fed to some special clocks for TFT Controller, I2S, HS-MMC, USB host and
UART. Since the EPLL input clock is initially fed to the input clocks for them, software must configure EPLLCON
register to use the EPLL.

POWER

nRESET
EXTCLK

or XTIpll

PLL is configured by S/W first time

Clock

disable

Lock time

VCO is adapte to new clock frequency

.

VCO

output

SYSCLK

The logic is operarted by
EXTCLK or XTIpll

SYSCLK is FOUT

Figure 2-2. Power-on reset sequence

WATCHDOG RESET

Watchdog reset is invoked when software fails to prevent the watchdog timer from timing out.
During the watchdog reset, the following actions occur :

• All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted during watchdog reset.

Watchdog reset can be activated in normal and idle mode because watchdog timer can expire with clock.
Watchdog reset is invoked when watchdog timer and reset are enabled (WTCON[5] = 1, WT CON[0]=1) and

watchdog timer is expired. Watchdog reset is invoked then, the following sequence occurs. :

1. Watchdog reset source asserts.

2. Internal reset signals and nRSTOUT are asserted and reset counter is activated.

3. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.

2-4

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

SOFTWARE RESET

Software can initialize the device state itself when it writes “0x533C_2443” to SWRST register.
During the software reset, the following actions occur :

• All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted during software reset.

Software reset is invoked then, the following sequence occurs. :

1. User write “0x533C_2443” to SWRST register.

2. System controller request bus controller to finish current transactions.

3. Bus controller send acknowledge to system controller after completed bu s transactions.

4. System controller request memory controller to enter into self refresh mode.

5. System controller wait for self refresh acknowledge from memory controller.

6. Internal reset signals and nRSTOUT are asserted and reset counter is activated.

7. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.

WAKEUP RESET

When S3C2443X is woken up from SLEEP mode by wakeup event, the wakeup reset is invoked. The detail
description will be explained in the power management mode section.

Table 2-1 lists alive registers which are not influenced various reset sources except nRESET. With the exception
of below registers(in table 2-1), All S3C2443X’s internal registers are reset by above-mentioned reset sources.

Table 2-1. Registers & GPIO status in RESET (R: reset, S: sustain previous value)

Region Registers

Wakeup

SYSCON

GPIO

OSCSET , PWRCFG, RSTCON, RSTSTAT, WKUPSTAT, INFORM0,
INFORM1, INFORM2, INFORM3

GPFCON, GPFUDP, GPFDAT, GPGCON[7:0], GPGUDP,
GPGDAT[7:0], EXTINT0 ~ EXTINT15

Software

S S S R

R S R R

Watchdog

nRESET

2-5

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

CLOCK MANAGEMENT

CLOCK GENERATION OVERVIEW

Figure 2-3 shows the block diagram of the clock generation module. The main clock source comes from an
external crystal (XTI) or external clock (EXTCLK). The clock generator consists of two PLLs (Phase-Locked-Loop)
which generate the high-frequency clock signals required in S3C2443X.

OM[0]

XTI

EXTCLK

XTI

EXTCLK

OM[0]&

CLKSRC

CLOCK SOURCE SELECTION

MPLL

ExtClk Div

EPLL

SYSCLK

ECLK

Figure 2-3. Clock generator block diagram

ARMCLK
HCLK
PCLK
DDRCLK

Clock

Divider &

Mux

USBHOST

CAMCLK
LCDCLK

I2SCLK

UARTCLK

Table 2-2 and 2-3 show the relationship between the combination of mode control pins OM[0] and the selection of
source clock for S3C2443X.

Table 2-2. Clock source selection for the main PLL and clock generation logic

OM[0]

MPLL Reference Clock

(Main clock source)

note1

0 XTI
1 EXTCLK

2-6

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

Table 2-3. Clock source selection for the EPLL

CLKSRC[8] (register)

0
0
1
1

CLKSRC[7] (register)

X
X
0 X
1 X

PLL & Clock Generator generally uses the following conditions.

Loop filter capacitance

CLF

MPLLCAP :Typ. :150pF(142 ~ 175pF)

EPLLCAP :Typ: 700pF(630 ~ 770pF)

Fin

Fout

External capacitance used for X-tal

- MPLL: 10 – 30 MHz

MPLL: 300 – 1100 MHz

C

15 – 22 pF

EXT

Main Oscillator circuit examples

OM[0] EPLL Reference Clock

0 XTI
1 EXTCLK

XTI

EXTCLK

EPLL: 10 – 40 MHz

EPLL: 20 – 100 MHz

EXTCLK

C EXT

XTIpll

C EXT

XTOpll

a) X-TAL O scillation (O M [0]=0) b) External Clock Source (O M [0]=1)

External

OSC

EXTCLK

XTIpll

XTOpll

2-7

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

PLL (PHASE-LOCKED-LOOP)

The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The
PLL provides frequency multiplication capabilities.

MPLL generates the clock sources for ARMCLK, HCLK, PCLK, DDRCLK and SSMCCLK and EPLL generates
clock sources for USBHOSTCLK, CAMCLK and so forth.

The following sections describe the operation of the PLL, that includes the phase difference detector, charge
pump, VCO (Voltage controlled oscillator), and loop filter.

Refer to MPLLCON and EPLLCON registers to change PLL output frequency.

Off-chip loop filter

Fin Pre-Divider

PFD

Charge

Pump

Main

Divider

VCO

Post

Scaler

Fout

Figure 2-4. PLL(Phase-Locked Loop) Block Diagram

CHANGE PLL SETTINGS IN NORMAL OPERATION

During the operation of S3C2443X in NORMAL mode, if the user wants to change the frequency by writing the
PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the
internal blocks in S3C2443X. The timing diagram is as follow.

MPLL_clk

PMS setting

PLL Locktime

SYSCLK

It changes to LOW value during

lock time automatically

It changes to new PLL clock
after lock time automatically

Figure 2-5. The case that changes slow clock by setting PMS value

2-8

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

SYSTEM CLOCK CONTROL

The ARMCLK is used for ARM920T core, the main CPU of S3C2443X. The HCLK is the reference clock for
internal AHB bus and peripherals such as the memory controller, the interrupt controller, LCD controller, the DMA,
USB host block, System Controller, Power down controller and etc. The PCLK is used for internal APB bus and
peripherals such as WDT, IIS, I2C, PWM timer, ADC, UART, GPIO, RTC and SPI etc. DDRCLK is the data strobe
clock for DDR memories. CAMclk is used for camera interface block.

EXTCLK

XTI

System

Controller

MPLL

PLL3000X

EPLL

PLL2126X

ARM920T

ARMCLK

HCLK part

PCLK part

EPLLclk

TIC

DMA
(6ch)

MEMC

CAMIF

LCD Con

(STN)

FIMD
(TFT)

INTC

HS-MMC

USB dev

(V2.0)

USB host

(V1.1)

EXT_CLK

(mpll)

usb_phy

AC97

TSADC

SD-MMC

(SDI)

PWM

UART

SPI 2.0

SPI_0
SPI_1

I2C

GPIO

WDT

RTC

gpio

I2S

Figure 2-6. The clock distribution block diagram

2-9

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

XTI

EXTCLK

Divider

(1 ~ 15)

PLL3000X

(300 ~ 1100Mhz)

MSysClk

ARM-DIVIDER

1/1 ~ 1/16

PRE-DIVIDER

1/1 ~ 1/4

MSysClkPreDiv

1/

1/

1/

2 DI

4 DI

8 DI

0

1

DVS

0
1
2

Hx2_MHCLK_M

V

V

V

0
1

0

Hx1_2_M PCLK _M
1
2
3

0
1
2
3

ARMCLK

(533Mhz)

HCLK

(133Mhz)

DDRCLK

(266Mhz)

SSMCCLK

(133Mhz)

PCLK

(66Mhz)

Figure 2-7. MPLL Based clock domain

The MSysClk is the base clock for S3C2443 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc.
The following table shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is deter mined

by PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.

Table 2-4. Clock division ratio of MPLL region

MPLL Clock Domain

Division Ratio (to MSysClk) [HCLK:DDRCL K:PCLK]

HCLKDIV PCLKDIV

PREDIV

(2'b00)

PREDIV

(2'b01)

PREDIV

(2'b10)

PREDIV

(2'b11)

ARMCLK

2’b00 1’b0 1:1:1 2:2:2 3:3:3 4:4:4 MSysClk
2’b00 1’b1 1:1:2 2:2:4 3:3:6 4:4:8 MSysClk / 2
2’b01 1’b0 2:1:2 4:2:4 6:3:6 8:4:8 MSysClk / 3
2’b01 1’b1 2:1:4 4:2:8 6:3:12 8:4:16 MSysClk / 4
2’b11 1’b0 4:2:4 8:4:8 12:6:12 16:8:16 MSysClk / 6
2’b11 1’b1 4:2:8 8:4:16 12:6:24 16:8:32 MSysClk / 8

MSysClk / 12
MSysClk / 16

(async)

2-10

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

EXAMPLE FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA
CLOCKS.

PLL output frequency = 1066Mhz
Target frqeuency

ARMCLK = 533Mhz
HCLK = 133Mhz
PCLK = 66Mhz
DDRCLK = 266Mhz
SSMCCLK = 66Mhz

Register value

ARMDIV = 4’b1000
PREDIV = 2’b01
HCLKDIV = 2’b01
PCLKDIV = 1’b1
HALKHCLK = 1’b1

2-11

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

Figure 2-8 shows EPLL and special clocks for various peripherals

SCL

I2

K

DISPSYSCL

K

(FIMD)

UARTCLK

XTI

EXTCLK

EPllRefClk

PLL2126X

(20 ~ 100Mhz)

ESYSCLK

Divider

(1~

Divider

(1~

Divider

(1~

25

1

)

6

I2SEXTCLK

)

6

1

)

6

Divider

(1~4)

Divider

(1~4)

Divider

(1~4)

Divider

(1~

1

)

6

USBHOSTCLK

HSMMCCLK

SPICLK(2.0)

CAMCLK

(portOut)

Figure 2-8. EPLL Based clock domain

ESYSCLK CONTROL

Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and
all clocks are enabled or disabled by accessing SCLKCON register. According to USB host interface, If you want
to get the clock with exact 50% duty cycle, then make EPLL generate 96MHz and divide the clock.

EPLL will be turned off during STOP and SLEEP mode automatically. Also, EPLL will be generated clock to
ESYSCLK, after exiting STOP and SLEEP mode if corresponding bits are enabled in SCLKCON register.

Table 2-5. ESYSCLK Control

Condition ESYSCLK state EPLL state

After reset EPLL reference clock off

After configuring EPLL

During PLL lock time: LOW

After PLL lock time: EPLL output

on

2-12

S3C2443X RISC MICROPROCESSOR SYSTEM CONTROLLER

POWER MANAGEMENT

The power management block controls the system clocks by software for the reduction of power consumption in
S3C2443X. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal.
S3C2443X has four power-down modes. The following section describes each powe r management mode.

Related registers are PWRMODE, PWRCFG and WKUPSTAT.

POWER MODE STATE DIAGRAM

Figure 2-9 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering
conditions are set by the main CPU.

Normal

(General Clock

CMD CMD

Gating Mode)

IDLE

One of

wakeup

source

CMD

restricted

SLEEP

One of

wakeup

source

STOP

Reset

or

wakeup

evants.

Figure 2-9. Power mode state diagram

2-13

SYSTEM CONTROLLER S3C2443X RISC MICROPROCESSOR

POWER SAVING MODES
Normal Mode (General Clock Gating Mode)

In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed
by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the
corresponding bit (or bits) is changed. (these bits are set or cleared by the main CPU.)

IDLE Mode

In IDLE mode, the clock to CPU core is stopped. The IDLE mode is activated just after the execution of the
STORE instruction that enables the IDLE Mode bit. The IDLE Mode bit should be cleared after the wake-up from
the IDLE state for the entering of next IDLE Mode. The H/W logic only detects the low-to-high triggering of the
IDLE Mode bit.

STOP Mode

In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit
are also stopped(oscillator circuit is stopped optionally, see PWRCFG register). The STOP Mode is activated after
the execution of the STORE instruction that enables the STOP mode bit. The STOP Mode bit should be cleared
after the wake-up from the STOP state for the entering of next STOP mode. The H/W logic only detects the low­to-high triggering of the STOP Mode bit.

To exit from STOP mode, External interrupt, RTC alarm, RTC Tick, or BATT_FLT has to be activated. During the
wake-up sequences, the crystal oscillator and PLL may begin to operate. The crystal-oscillator settle-down-time
and the PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted
by the hardware of S3C2443X. During these time-waits, the clock is not supplied to the internal logic circuitry.

STOP mode Entering sequence

note3

is as follows

1. Set the STOP Mode bit ( by the main CPU)

2. System controller requests bus controller to finish current transactions.

3. Bus controller send acknowledge to system controller after completed bu s transactions.

4. System controller request memory controller to enter into self refresh mode. It is for preserving contents in
SDRAM.

5. System controller wait for self refresh acknowledge from memory controller.

6. After receiving the self-refresh acknowledge, system controller disables system clocks, and switches
SYSCLK’s source to MPLL reference clock.

7. Disables PLLs and Crystal(XTI) oscillation. If OSC_EN_STOP bit in PWRCFG register is ‘high’ then system
controller doesn’t disable crystal oscillation.

note3. DRAM has to be in self-refresh mode duri ng STOP and SLEEP mode to retain valid memory data. LCD must be

stopped before STOP and SLEEP mode, because DRAM can't be accessed when it is in self-refresh mode.

STOP mode Exiting sequence is as follows

1. Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms).

2. After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the PL Ls
and waits the PLL locking time

3. Switching the clock source, now the PLL is the clock source.

2-14