SAMSUNG S3C2443X User Manual

S3C2443X

USER’S MANUAL

Revision 1.2

REVISION HISTORY

Revision	Date	Description
1.0	February 7, 2007	First release
1.1	March 6, 2007	IIC Bus Interface update

1.2	March 22, 2007	Overview, Electrical Data update
		(Operating voltage of VDD_SDRAM: 1.8V => 1.8V/2.5V/3.3V)

S3C2443X

32-BIT RISC

MICROCONTROLLERS

USER MANUAL

Revision 1.2

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

S3C2443X 32-Bit RISC Microcontrollers User manual, Revision 1.2

Publication Number: 21-S3-C2443X-012007

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.

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All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Giheunggu

Yongin-City, Gyeonggi-Do, Korea

C.P.O. Box #37, Suwon 449-900

TEL: (82)-(031)-209-1928

FAX: (82)-(031)-209-1909

Home Page: http://www.samsungsemi.com

Printed in the Republic of Korea

Table of Contents

Chapter 1	Product Overview
Introduction ...................................................................................................................................................		1-1
Features ........................................................................................................................................................		1-2
Block Diagram...............................................................................................................................................		1-5
Pin Assignments ...........................................................................................................................................		1-6
Signal Descriptions .......................................................................................................................................		1-26
S3C2443X Operation Mode Description..............................................................................................		1-32
S3C2443X Memory MAP and Base Address of Special Registers .....................................................		1-33

Chapter 2	System Controller
Overview .......................................................................................................................................................		2-1
Feature..........................................................................................................................................................		2-1
Block Diagram...............................................................................................................................................		2-2
Functional Descriptions.................................................................................................................................		2-3
Watchdog Reset...................................................................................................................................		2-4
Software Reset.....................................................................................................................................		2-5
Wakeup Reset......................................................................................................................................		2-5
Clock Management .......................................................................................................................................		2-6
Clock Generation Overview..................................................................................................................		2-6
Clock Source Selection ........................................................................................................................		2-6
PLL (Phase-Locked-Loop) ...................................................................................................................		2-8
Change PLL Settings in Normal Operation..........................................................................................		2-8
System Clock Control...........................................................................................................................		2-9
Example for Configuring Clock Regiter to Produce Specific Frequency of AMBA clocks. ..................		2-11
ECLK Control........................................................................................................................................		2-12
Power Management......................................................................................................................................		2-13
Power Mode State Diagram .................................................................................................................		2-13
Power Saving Modes ...........................................................................................................................		2-14
Wake-up Event.....................................................................................................................................		2-16
Output Port State and Stop and Sleep Mode.......................................................................................		2-16
Power Saving Mode Entering/Exiting Condition...................................................................................		2-17
Register Descriptions	....................................................................................................................................	2-18
Address Map ........................................................................................................................................		2-18
Individual Register Descriptions....................................................................................................................		2-20
Clock Source Control Registers (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON)2-20
Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON) .....................		2-23
Power Management Registers (PWRMODE and PWRCFG)..............................................................		2-27
Reset Control Registers (SWRST and RSTCON) ...............................................................................		2-29
Usage of PWROFF_SLP......................................................................................................................		2-30
System Controller Status Registers (WKUPSTAT and RSTSTAT) .....................................................		2-31
Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC) ....................................................		2-32
MISC. (INFORM0~3)............................................................................................................................		2-34
USB PHY Control register (PHYctrl) ....................................................................................................		2-34
USB PHY POWER Control register (PHYPWR)..................................................................................		2-35
USB Reset Control Register (urstcon) .................................................................................................		2-36
USB Clock Control register (uclkcon)...................................................................................................		2-36

S3C2443X MICROCONTROLLER

iii

Table of Contents (Continued)

Chapter 3	Bus Matrix & EBI
Overview........................................................................................................................................................		3-1
Special Function Registers............................................................................................................................		3-2
Matrix Core 0 priority Register (Bpriority0) ...........................................................................................		3-2
Matrix Core 1 priority Register (Bpriority1) ...........................................................................................		3-2
EBI Control Register (EBICON) ....................................................................................................................		3-3

Chapter 4	Bus Priorities
Overview........................................................................................................................................................		4-1
Bus Priority Map ...................................................................................................................................		4-1
Chapter 5	Static Memory Controller (SMC)
Overview........................................................................................................................................................		5-1
Feature ..........................................................................................................................................................		5-2
Block Diagram ...............................................................................................................................................		5-3
Asynchronous Read .............................................................................................................................		5-4
Asynchronous Burst Read....................................................................................................................		5-6
Synchronous Read/Synchronous Burst Read......................................................................................		5-7
Asynchronous Write..............................................................................................................................		5-8
Synchronous Write/ Synchronous Burst Write .....................................................................................		5-10
Bus Turnaround	....................................................................................................................................	5-11
Special Registers ..........................................................................................................................................		5-13
Bank Idle Cycle Control Registers 0-5..................................................................................................		5-13
Bank Read wait State Control Registers 0-5........................................................................................		5-13
Bank Write wait State Control Registers 0-5 ........................................................................................		5-14
Bank Output Enable Assertion Delay Control Registers 0-5................................................................		5-14
Bank Write Enable Assertion Delay Control Registers 0-5 ..................................................................		5-15
Bank Control Registers 0-5 ..................................................................................................................		5-16
Bank Status Registers 0-5....................................................................................................................		5-18
Bank Burst Read wait Delay Control Registers 0-5..............................................................................		5-18
Bank Onenand Type Selection Register ..............................................................................................		5-19
SMC Status Register ............................................................................................................................		5-19
SMC Control Register...........................................................................................................................		5-20

iv	S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 6	Mobile DRAM Controller
Overview .......................................................................................................................................................		6-1
Block Diagram...............................................................................................................................................		6-2
Mobile DRAM Initialization Sequence...........................................................................................................		6-3
Mobile DRAM (SDRAM OR DDR) Initialization Sequence ..................................................................		6-3
Mobile DRAM Configuration Register ..................................................................................................		6-6
Mobile DRAM Control Register ............................................................................................................		6-7
Mobile DRAM Timming Control Register .............................................................................................		6-8
Mobile DRAM (Extended) Mode Regiter Set Register.........................................................................		6-9
Mobile DRAM Refresh Control Register ..............................................................................................		6-10
Mobile DRAM Write Buffer Time out Register......................................................................................		6-10

Chapter 7	NAND Flash Controller
Overview .......................................................................................................................................................		7-1
Features ...............................................................................................................................................		7-1
Block Diagram ......................................................................................................................................		7-2
Boot Loader Function ...........................................................................................................................		7-2
Pin Configuration Table........................................................................................................................		7-3
Nand Flash Memory Timing .................................................................................................................		7-4
Software Mode .....................................................................................................................................		7-4
2048 Byte SLC ECC Parity Code Assignment Table...........................................................................		7-6
16 Byte ECC SLC Parity Code Assignment Table...............................................................................		7-6
ECC Module Features..........................................................................................................................		7-7
SLC ECC Programming Guide ............................................................................................................		7-8
MLC ECC Programming Guide (Encoding) .........................................................................................		7-8
MLC ECC Programming Guide (Decoding) .........................................................................................		7-9
Nand Flash Memory Mapping ..............................................................................................................		7-10
Nand Flash Controller Special Registers......................................................................................................		7-12
Nand Flash Controller Register Map....................................................................................................		7-12
Nand Flash Configuration Register ......................................................................................................		7-13
Control Register ...................................................................................................................................		7-14
Command Register ..............................................................................................................................		7-16
Address Register..................................................................................................................................		7-16
Data Register........................................................................................................................................		7-16
Main Data Area ECC Register .............................................................................................................		7-17
Spare Area ECC Register ....................................................................................................................		7-18
Progrmmable Block Address Register .................................................................................................		7-19
Nfcon Status Register ..........................................................................................................................		7-21
ECC0/1 Status Register .......................................................................................................................		7-22
Main Data Area ECC0 Status Register ................................................................................................		7-24
Spare Area ECC Status Register.........................................................................................................		7-25
MLC 4-bit ECC Error Patten Register ..................................................................................................		7-25

S3C2443X MICROCONTROLLER

	Table of Contents (Continued)
Chapter 8	CF Controller
Overview........................................................................................................................................................		8-1
Features................................................................................................................................................		8-2
Block Diagram ......................................................................................................................................		8-3
Timing Diagram	....................................................................................................................................	8-6
Special Function Registers...................................................................................................................		8-11
Individual Register Descriptions....................................................................................................................		8-14
MUX_REG Register..............................................................................................................................		8-14
PCCARD Interrupt Mask & Source Register ........................................................................................		8-16
PCCARD_Attr Register.........................................................................................................................		8-17
PCCARD_I/O Register .........................................................................................................................		8-17
PCCARD_COMM Register...................................................................................................................		8-18
ATA_Control Register...........................................................................................................................		8-19
ATA_Status Register ............................................................................................................................		8-19
ATA_Command Register......................................................................................................................		8-20
ATA_SWRST Register .........................................................................................................................		8-21
ATA_IRQ Register ................................................................................................................................		8-21
ATA_IRQ_Mask Register .....................................................................................................................		8-22
ATA_CFG Register...............................................................................................................................		8-23
ATA_PIO_Time Register ......................................................................................................................		8-25
ATA_UDMA_Time Register..................................................................................................................		8-25
ATA_XFR_NUM Register.....................................................................................................................		8-26
ATA_XFR_CNT Register......................................................................................................................		8-26
ATA_TBUF_START Register ...............................................................................................................		8-26
ATA_TBUF_SIZE Register...................................................................................................................		8-27
ATA_SBUF_START Register...............................................................................................................		8-27
ATA_SBUF_SIZE Register...................................................................................................................		8-27
ATA_CADDR_TBUF Register ..............................................................................................................		8-28
ATA_CADDR_SBUF Register..............................................................................................................		8-28
ATA_PIO_DTR Register.......................................................................................................................		8-28
ATA_PIO_FED Register .......................................................................................................................		8-29
ATA_PIO_SCR Register.......................................................................................................................		8-29
ATA_PIO_LLR Register........................................................................................................................		8-29
ATA_PIO_LMR Register.......................................................................................................................		8-30
ATA_PIO_LMR Register.......................................................................................................................		8-30
ATA_PIO_DVR Register.......................................................................................................................		8-30
ATA_PIO_CSD Register.......................................................................................................................		8-31
ATA_PIO_DAD Register.......................................................................................................................		8-31
ATA_PIO_RDATA Register..................................................................................................................		8-31
BUS_FIFO_STATUS Register .............................................................................................................		8-32
ATA_FIFO_STATUS Register..............................................................................................................		8-32

vi	S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 9	DMA Controller
Overview .......................................................................................................................................................		9-1
DMA Request Sources .................................................................................................................................		9-2
DMA Operation .............................................................................................................................................		9-3
External DMA DREQ/DACK Protocol ..................................................................................................		9-4
Examples of Possible Cases................................................................................................................		9-7
DMA Special Registers .................................................................................................................................		9-8
DMA Initial Source Register (DISRC) ..................................................................................................		9-8
DMA Initial Source Control Register (DISRCC) ...................................................................................		9-8
DMA Initial Destination Register (DIDST) ............................................................................................		9-9
DMA Initial Destination Control Register (DIDSTC).............................................................................		9-9
DMA Control Register (DCON) ............................................................................................................		9-10
DMA Status Register (DSTAT).............................................................................................................		9-12
DMA Current Source Register (DCSRC) .............................................................................................		9-13
Current Destination Register (DCDST)................................................................................................		9-13
DMA Mask Trigger Register (DMASKTRIG)........................................................................................		9-14
DMA Requeset Selection Register (DMAREQSEL) ............................................................................		9-15

Chapter 10	Interrupt Controller
Overview .......................................................................................................................................................		10-1
Interrupt Controller Operation ..............................................................................................................		10-2
Interrupt Sources..................................................................................................................................		10-3
Interrupt Priority Generating Block .......................................................................................................		10-4
Interrupt Priority	....................................................................................................................................	10-5
Interrupt Controller Special Registers...........................................................................................................		10-6
Source Pending (SRCPND) Register...................................................................................................		10-6
Interrupt Mode (INTMOD) Register......................................................................................................		10-8
Interrupt Mask (INTMSK) Register.......................................................................................................		10-10
Priority Register (PRIORITY) ...............................................................................................................		10-12
Interrupt Pending (INTPND) Register ..................................................................................................		10-14
Interrupt Offset (INTOFFSET) Register ...............................................................................................		10-16
Sub Source Pending (SUBSRCPND) Register....................................................................................		10-17
Interrupt Sub Mask (INTSUBMSK) Register........................................................................................		10-19
Interrupt Sub Mask (INTSUBMSK) Register........................................................................................		10-19

S3C2443X MICROCONTROLLER

vii

Table of Contents (Continued)

Chapter 11	I/O PORTS
Overview........................................................................................................................................................			11-1
S3C2443X Port Configuration ..............................................................................................................			11-2
Port Control Descriptions ..............................................................................................................................			11-8
Port Configuration Register (Gpacon-Gpmcon) ...................................................................................			11-8
Port Data Register (Gpadat-Gpmdat)...................................................................................................			11-8
Port Pull-Up/Down Register (Gpbudp-Gpeudp,Gpgudph,Gphudp,Gpjudp,Gpludp,Gpmudp).............			11-8
Miscellaneous Control Register............................................................................................................			11-8
External Interrupt Control Register .......................................................................................................			11-8
I/O Port Control Register ...............................................................................................................................			11-9
Port A Control Registers (GPACDL, GPACDH) ...................................................................................			11-9
GPACDL/GPACDH Setup ....................................................................................................................			11-11
Port B Control Registers (GPBCON, GPBDAT, GPBUDP)..................................................................			11-12
Port C Control Registers (GPCCON, GPCDAT, GPCUDP).................................................................			11-14
Port D Control Registers (GPDCON, GPDDAT, GPDUDP).................................................................			11-16
Port E Control Registers (GPECON, GPEDAT, GPEUDP)..................................................................			11-18
Port F Control Registers (GPFCON, GPFDAT, GPFUDP) ..................................................................			11-20
Port G Control Registers (GPGCON, GPGDAT, GPGUDP)................................................................			11-21
Port H Control Registers (GPHCON, GPHDAT, GPHUDP).................................................................			11-23
Port J Control Registers (GPJCON, GPJDAT, GPJUDP)....................................................................			11-25
Port L Control Registers (GPLCON, GPLDAT, GPLUDP) ...................................................................			11-27
Port M Control Registers (GPMCON, GPMDAT, GPMUDP) ...............................................................			11-29
Miscellaneous Control Register (MISCCR) ..........................................................................................			11-30
Dclk Control Registers (DCLKCON).....................................................................................................			11-31
EXTINTn (External Interrupt Control Register		n).................................................................................	11-32
EINTFLTn (External Interrupt Filter Register		n) ..................................................................................	11-36
EINTMASK (External Interrupt Mask Register) ....................................................................................			11-37
EINTPEND (External Interrupt Pending Register)................................................................................			11-38
GSTATUSn (General Status Registers)...............................................................................................			11-39
DSCn (Drive Strength Control) .............................................................................................................			11-40
MSLCON (Memory Sleep Control Register) ........................................................................................			11-43
SDATA / RDATA Pull-Down Control Registers (DATAPDEN).............................................................			11-45

Chapter 12	Watchdog Timer
Overview........................................................................................................................................................		12-1
Features................................................................................................................................................		12-1
Watchdog Timer Operation ...........................................................................................................................		12-2
Block Diagram ......................................................................................................................................		12-2
Wtdat & Wtcnt.......................................................................................................................................		12-2
Consideration of Debugging Environment............................................................................................		12-2
Watchdog Timer Special Registers...............................................................................................................		12-3
Watchdog Timer Control (WTCON) Register .......................................................................................		12-3
Watchdog Timer Data (WTDAT) Register............................................................................................		12-4
Watchdog Timer Count (WTCNT) Register..........................................................................................		12-4

viii	S3C2443X MICROCONTROLLER

	Table of Contents (Continued)
Chapter 13	PWM Timer
Overview .......................................................................................................................................................		13-1
Feature .................................................................................................................................................		13-1
PWM Timer Operation ..................................................................................................................................		13-3
Prescaler & Divider...............................................................................................................................		13-3
Basic Timer Operation..........................................................................................................................		13-3
Auto Reload & Double Buffering ..........................................................................................................		13-4
Timer Initialization Using Manual Update bit and Inverter Bit ..............................................................		13-5
Timer Operation ...................................................................................................................................		13-6
Pulse Width Modulation (PWM) ...........................................................................................................		13-7
Output Level Control ............................................................................................................................		13-8
Dead Zone Generator ..........................................................................................................................		13-9
Dma request mode...............................................................................................................................		13-10
PWM Timer Control Registers ......................................................................................................................		13-11
Timer Configuration Register0 (TCFG0)..............................................................................................		13-11
Timer Configuration Register1 (TCFG1)..............................................................................................		13-12
Timer Control (TCON) Register ...........................................................................................................		13-13
Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)................................		13-15
Timer 0 Count Observation Register (TCNTO0)..................................................................................		13-15
Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)................................		13-16
Timer 1 Count Observation Register (TCNTO1)..................................................................................		13-16
Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)................................		13-17
Timer 2 Count Observation Register (TCNTO2)..................................................................................		13-17
Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)................................		13-18
Timer 3 Count Observation Register (TCNTO3)..................................................................................		13-18
Timer 4 Count Buffer Register (TCNTB4) ............................................................................................		13-19
Timer 4 Count Observation Register (TCNTO4)..................................................................................		13-19
Chapter 14	Real Time Clock
Overview .......................................................................................................................................................		14-1
Features ...............................................................................................................................................		14-1
Real Time Clock Operation ..................................................................................................................		14-2
Leap Year Generator............................................................................................................................		14-2
Read/Write Registers ...........................................................................................................................		14-3
Backup Battery Operation ....................................................................................................................		14-3
Alarm Function .....................................................................................................................................		14-3
Tick time interrupt.................................................................................................................................		14-4
32.768kHz X-Tal Connection Example ................................................................................................		14-5

S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 14	Real Time Clock
Real Time Clock Special Registers...............................................................................................................		14-6
Real Time Clock Control (RTCCON) Register .....................................................................................		14-6
Tick Time Count (TICNT0) Register 0..................................................................................................		14-7
Tick Time Count (TICNT1) Register 1..................................................................................................		14-7
RTC Alarm Control (RTCALM) Register ..............................................................................................		14-8
Alarm Second Data (ALMSEC) Register..............................................................................................		14-9
Alarm Min Data (ALMMIN) Register .....................................................................................................		14-9
Alarm Hour Data (ALMHOUR) Register...............................................................................................		14-9
Alarm Date Data (ALMDATE) Register ................................................................................................		14-10
Alarm Mon Data (ALMMON) Register ..................................................................................................		14-10
Alarm Year Data (ALMYEAR) Register ................................................................................................		14-10
BCD Second (BCDSEC) Register ........................................................................................................		14-11
BCD Minute (BCDMIN) Register ..........................................................................................................		14-11
BCD Hour (BCDHOUR) Register .........................................................................................................		14-12
BCD Date (BCDDATE) Register ..........................................................................................................		14-12
BCD Day (BCDDAY) Register..............................................................................................................		14-12
BCD Month (BCDMON) Register .........................................................................................................		14-13
BCD Year (BCDYEAR) Register ..........................................................................................................		14-13
TICK Counter (tickcnt) Register............................................................................................................		14-13
RTC Lowbat Check (RTCLbat) Register ..............................................................................................		14-14

Chapter 15	UART
Overview........................................................................................................................................................		15-1
Features................................................................................................................................................		15-1
Block Diagram ...............................................................................................................................................		15-2
Uart Operation ......................................................................................................................................		15-3
Uart Special Registers...................................................................................................................................		15-10
Uart Line Control Register ....................................................................................................................		15-10
Uart Control Register ............................................................................................................................		15-11
Uart Control Register ............................................................................................................................		15-11
Uart FIFO Control Register...................................................................................................................		15-13
Uart Modem Control Register...............................................................................................................		15-14
Uart Tx/Rx Status Register...................................................................................................................		15-15
Uart Error Status Register ....................................................................................................................		15-16
Uart FIFO Status Register ....................................................................................................................		15-17
Uart Modem Status Register ................................................................................................................		15-18
Uart Transmit Buffer Register (Holding Register & FIFO Register) .....................................................		15-19
Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................		15-19
Uart Baud Rate Divisor Register ..........................................................................................................		15-20

x	S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 16	USB Host Controller
Overview .......................................................................................................................................................		16-1
USB Host Controller Special Registers................................................................................................		16-2
Chapter 17	USB 2.0 Function
Overview .......................................................................................................................................................		17-1
Feature .................................................................................................................................................		17-1
Block Diagram...............................................................................................................................................		17-2
To Activate USB Port1 for USB 2.0 Function ...............................................................................................		17-3
USB 2.0 Function Controller Special Registers ............................................................................................		17-4
Registers .......................................................................................................................................................		17-6
Index Register (IR) ...............................................................................................................................		17-6
Endpoint Interrupt Register (EIR).........................................................................................................		17-7
Endpoint Interrupt Enable Register (EIER) ..........................................................................................		17-8
Function Address Register (FAR) ........................................................................................................		17-9
Frame Number Register (FNR)............................................................................................................		17-10
ENdpoint Direction Register (EDR)......................................................................................................		17-11
Test Register (TR)................................................................................................................................		17-12
System Status Register (SSR).............................................................................................................		17-13
System Control Register (SCR) ...........................................................................................................		17-15
EP0 Status Register (EP0SR)..............................................................................................................		17-17
EP0 Control Register (EP0CR)] ...........................................................................................................		17-18
Endpoint# Buffer Register (EP#BR)....................................................................................................		17-19
Endpoint Status Register (EsR) ...........................................................................................................		17-20
Endpoint Control Register (ECR) .........................................................................................................		17-22
Byte Read Count Register (BRCR)......................................................................................................		17-24
Byte Write Count Register (BWCR) .....................................................................................................		17-25
MAX Packet register (MPR) .................................................................................................................		17-26
DMA Control register (DCR) ................................................................................................................		17-27
DMA Transfer Counter Register (DTCR) .............................................................................................		17-28
DMA FIFO Counter Register (DFCR) ..................................................................................................		17-29
DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)......................................................................		17-30
DMA Interface Control Register (DICR) ...............................................................................................		17-31
Memory Base Address Register (MBAR).............................................................................................		17-32
Memory Current Address Register (MCAR) ........................................................................................		17-33
Burst FIFO Control Register(FCON) ....................................................................................................		17-33
Burst FIFO Status Register(FSTAT) ....................................................................................................		17-33
AHB Master(DMA) Operation Flow Chart ............................................................................................		17-34

S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 18	IIC-BUS Interface
Overview........................................................................................................................................................		18-1
IIC-Bus Interface...................................................................................................................................		18-3
Start and Stop Conditions.....................................................................................................................		18-3
Data Transfer Format ...........................................................................................................................		18-4
ACK Signal Transmission.....................................................................................................................		18-5
Read-Write Operation...........................................................................................................................		18-6
Bus Arbitration Procedures...................................................................................................................		18-6
Abort Conditions ...................................................................................................................................		18-6
Configuring IIC-Bus ..............................................................................................................................		18-6
Flowcharts of Operations in Each Mode ..............................................................................................		18-7
IIC-Bus Interface Special Registers ..............................................................................................................		18-11
Multi-Master IIC-Bus Control (IICCON) Register..................................................................................		18-11
Multi-Master IIC-BUS Control/Status (IICSTAT) Register....................................................................		18-12
Multi-Master IIC-BUS Address (IICADD) Register ...............................................................................		18-13
Multi-Master IIC-BUS Transmit/Receive Data Shift (IICDS) Register ..................................................		18-13
Multi-Master IIC-BUS Line Control(IICLC) Register .............................................................................		18-14

Chapter 19	SPI Interface
Overview........................................................................................................................................................		19-1
Features................................................................................................................................................		19-1
Block Diagram ......................................................................................................................................		19-2
SPI Operation .......................................................................................................................................		19-3
Programming Procedure ......................................................................................................................		19-3
SPI special registers......................................................................................................................................		19-7
SPI Control Register .............................................................................................................................		19-7
SPI Status Register ..............................................................................................................................		19-9
SPI Pin Control Register.......................................................................................................................		19-11

Chapter 20	HS_SPI Controller
Overview........................................................................................................................................................		20-1
Features................................................................................................................................................		20-1
Block Diagram ...............................................................................................................................................		20-2
Signal Description .........................................................................................................................................		20-3
Operation ..............................................................................................................................................		20-3
SPI Transfer Format......................................................................................................................................		20-4
Sequence of Special Function Register ........................................................................................................		20-5
Register Descriptions	....................................................................................................................................	20-5

xii	S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 21	CSTN LCD Display Controller
Overview .......................................................................................................................................................		21-1
Common Features................................................................................................................................		21-2
External Interface Signal ......................................................................................................................		21-2
Block Diagram...............................................................................................................................................		21-3
STN LCD Controller Operation .....................................................................................................................		21-4
Timing Generator (TIMEGEN)..............................................................................................................		21-4
Video Operation ...................................................................................................................................		21-5
Dithering and Frame Rate Control .......................................................................................................		21-7
Memory Data Format (STN, BSWP = 0)..............................................................................................		21-9
PAD Muxing ..................................................................................................................................................		21-17
LCD Controller Special Registers ........................................................................................................		21-18

Chapter 22	TFT LCD
Overview .......................................................................................................................................................		22-1
Top block diagram Display Controller...........................................................................................................		22-2
Features ...............................................................................................................................................		22-3
Functional Description ..................................................................................................................................		22-4
Brief of the sub-block............................................................................................................................		22-4
Data Flow .............................................................................................................................................		22-4
Overview of the Color Data ..................................................................................................................		22-6
VD Signal Connection ..........................................................................................................................		22-18
Palette usage........................................................................................................................................		22-20
Palette Read/Write ...............................................................................................................................		22-22
Window Blending ..........................................................................................................................................		22-23
Overview...............................................................................................................................................		22-23
Vtime Controller Operation ...........................................................................................................................		22-27
RGB Interface case ..............................................................................................................................		22-27
Virtual Display ...............................................................................................................................................		22-28
RGB Interface Spec .............................................................................................................................		22-29
LCD CPU Interface (i80-system i/f)......................................................................................................		22-30
Signals..................................................................................................................................................		22-31
PAD Muxing..........................................................................................................................................		22-32
Programmer’s Model.....................................................................................................................................		22-33
Overview...............................................................................................................................................		22-33

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xiii

	Table of Contents (Continued)
Chapter 23	CAMERA Interface
Overview........................................................................................................................................................		23-1
Features................................................................................................................................................		23-2
External Interface ..........................................................................................................................................		23-2
Signal Description.................................................................................................................................		23-2
Timing Diagram	....................................................................................................................................	23-3
External/Internal Connection Guide ..............................................................................................................		23-5
Camera Interface Operation..........................................................................................................................		23-5
Two DMA ports .....................................................................................................................................		23-5
Clock Domain .......................................................................................................................................		23-7
Frame Memory Hirerarchy....................................................................................................................		23-7
Memory Storing Method .......................................................................................................................		23-9
Timing Diagram for Register Setting ....................................................................................................		23-10
MSDMA Feature ...................................................................................................................................		23-13
Software Interface .........................................................................................................................................		23-14
Camera Interface Special Registers .............................................................................................................		23-14
Source Format Register........................................................................................................................		23-14
Window Option Register.......................................................................................................................		23-15
Global Control Register ........................................................................................................................		23-17
Window Option Register 2....................................................................................................................		23-18
Y1 Start Address Register ....................................................................................................................		23-18
Y2 Start Address Register ....................................................................................................................		23-18
Y3 Start Address Register ....................................................................................................................		23-19
Y4 Start Address Register ....................................................................................................................		23-19
CB1 Start Address Register .................................................................................................................		23-19
Cb2 Start Address Register..................................................................................................................		23-20
CB3 Start Address Register .................................................................................................................		23-20
CB4 Start Address Register .................................................................................................................		23-20
Cr1 Start Address Register...................................................................................................................		23-20
Cr2 Start Address Register...................................................................................................................		23-21
Cr3 Start Address Register...................................................................................................................		23-21
Cr4 Start Address Register...................................................................................................................		23-21
Codec Target Format Register .............................................................................................................		23-22
Codec DMA Control Register ...............................................................................................................		23-24
Register Setting Guide for Codec Scaler and Preview Scaler .............................................................		23-25
Codec Pre-Scaler Control Register 1 ...................................................................................................		23-28
Codec Pre-Scaler Control Register 2 ...................................................................................................		23-28
Codec Main-Scaler Control Register....................................................................................................		23-29
Codec DMA Target Area Register........................................................................................................		23-29
Codec Status Register..........................................................................................................................		23-30
RGB1 Start Address Register...............................................................................................................		23-30
RGB2 Start Address Register...............................................................................................................		23-31
RGB3 Start Address Register...............................................................................................................		23-31
RGB4 Start Address Register...............................................................................................................		23-31

xiv	S3C2443X MICROCONTROLLER

Table of Contents (Continued)

Chapter 23	CAMERA Interface
Preview Target Format Register ..........................................................................................................		23-32
Preview DMA Control Register ............................................................................................................		23-33
Preview Pre-Scaler Control Register 1 ................................................................................................		23-34
Preview Pre-Scaler Control Register 2 ................................................................................................		23-34
Preview Main-Scaler Control Register .................................................................................................		23-35
Preview DMA Target Area Register .....................................................................................................		23-35
Preview Status Register .......................................................................................................................		23-36
Image Capture Enable Register...........................................................................................................		23-37
Codec Capture Sequence Register .....................................................................................................		23-38
Codec Scan Line Offset Register.........................................................................................................		23-39
Image Effects Register .........................................................................................................................		23-40
Msdma Y Start Address Register.........................................................................................................		23-41
Msdma Cb Start Address Register.......................................................................................................		23-41
Msdma Cr Start Address Register .......................................................................................................		23-41
Msdma Y End Address Register ..........................................................................................................		23-41
Msdma Cb End Address Register........................................................................................................		23-42
Msdma Cr End Address Register.........................................................................................................		23-42
Msdma Y Offset Register .....................................................................................................................		23-42
Msdma Cb Offset Register ...................................................................................................................		23-43
Msdma Cr Offset Register....................................................................................................................		23-43
Msdma Source Image Width Register .................................................................................................		23-43
Msdma Control Register.......................................................................................................................		23-45

Chapter 24	ADC & Touch Screen Interface
Overview .......................................................................................................................................................		24-1
Features ...............................................................................................................................................		24-1
ADC & Touch Screen Interface Operation....................................................................................................		24-2
Block Diagram ......................................................................................................................................		24-2
Function Descriptions...........................................................................................................................		24-3
ADC and Touch Screen Interface Special Registers....................................................................................		24-6
ADC Control (ADCCON) Register........................................................................................................		24-6
ADC Touch Screen Control (ADCTSC) Register.................................................................................		24-7
ADC Start Delay (Adcdly) Register ......................................................................................................		24-8
ADC Conversion Data (ADCDAT0) Register .......................................................................................		24-9
ADC Conversion Data (ADCDAT1) Register .......................................................................................		24-10
ADC Touch Screen Up-Down Int Check Register (Adcupdn)..............................................................		24-10
ADC Channel Mux Register (ADCMUX) ..............................................................................................		24-11

S3C2443X MICROCONTROLLER

	Table of Contents (Continued)
Chapter 25	IIS-BUS Interface
Overview........................................................................................................................................................		25-1
Features................................................................................................................................................		25-1
IIS Controller Operation.................................................................................................................................		25-2
Block Diagram ......................................................................................................................................		25-2
Master/Slave mode...............................................................................................................................		25-3
Sampling Frequency and Master Clock ...............................................................................................		25-6
IIS Clock Mapping Table.......................................................................................................................		25-6
IIS-BUS Interface Special Registers .............................................................................................................		25-7
IIS Control Register (I2scon) ................................................................................................................		25-7
IIS Mode Register (I2smod)..................................................................................................................		25-9
IIS FIFO Control Register (i2sfic) .........................................................................................................		25-10
IIS Prescaler Control Register (i2sfic) ..................................................................................................		25-11
IIS Transmit Data Register (i2stxd) ......................................................................................................		25-11
IIS Receive Data Register (i2srxd) .......................................................................................................		25-11
Chapter 26	AC97 Controller
Overview........................................................................................................................................................		26-1
Features................................................................................................................................................		26-1
AC97 Controller Operation ............................................................................................................................		26-2
Block Diagram ......................................................................................................................................		26-2
Internal Data Path.................................................................................................................................		26-3
Operation Flow Chart............................................................................................................................		26-4
AC-LINK Digital Interface Protocol .......................................................................................................		26-5
AC-link Output Frame (SDATA_OUT)..................................................................................................		26-6
AC-link Input Frame (SDATA_IN).........................................................................................................		26-6
Powering Down the AC-link..................................................................................................................		26-7
Waking up the AC-link - Wake up Triggered by the AC97 Controller ..................................................		26-7
Cold AC97 Reset ..................................................................................................................................		26-8
WARM AC97 Reset ..............................................................................................................................		26-8
AC97 Controller Special Registers................................................................................................................		26-9
AC97 Global Control Register (AC_GLBCTRL) ...................................................................................		26-9
AC97 Global Status Register (AC_GLBSTAT).....................................................................................		26-10
AC97 CODEC Command Register (AC_CODEC_CMD).....................................................................		26-10
AC97 CODEC Status Register (AC_CODEC_STAT) ..........................................................................		26-11
AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................		26-11
AC97 MIC in Channel FIFO Address Register (AC_MICADDR) .........................................................		26-12
AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)......................................................		26-12
AC97 MIC in Channel FIFO Data RegisteR (AC_MICDATA) ..............................................................		26-12

xvi	S3C2443X MICROCONTROLLER

	Table of Contents (Continued)
Chapter 27	MMC/SD/SDIO Controller
Features ........................................................................................................................................................		27-1
Block Diagram...............................................................................................................................................		27-1
SD Operation ................................................................................................................................................		27-2
SDIO Operation.............................................................................................................................................		27-3
SDI Special Registers ...................................................................................................................................		27-4
SDI Control Register (SDICON)...........................................................................................................		27-4
SDI Baud Rate Prescaler Register (SDIPRE)......................................................................................		27-4
SDI Command Argument Register (SDICmdArg)................................................................................		27-5
SDI Command Control Register (SDICmdCon)...................................................................................		27-5
SDI Command Status Register (SDICmdSta)......................................................................................		27-6
SDI Response Register 0 (SDIRSP0)..................................................................................................		27-6
SDI Response Register 1 (SDIRSP1)..................................................................................................		27-6
SDI Response Register 2 (SDIRSP2)..................................................................................................		27-7
SDI Response Register 3 (SDIRSP3)..................................................................................................		27-7
SDI Data / Busy Timer Register (SDIDTimer)......................................................................................		27-7
SDI Block Size Register (SDIBSize) ....................................................................................................		27-7
SDI Data Control Register (SDIDatCon) ..............................................................................................		27-8
SDI Data Remain Counter Register (ADIDatCnt) ................................................................................		27-9
SDI Data Status Register (ADIDatSta).................................................................................................		27-9
SDI Fifo Status Register (SDIFSTA) ....................................................................................................		27-10
SDI Interrupt Mask Register (SDIIntMsk).............................................................................................		27-11
SDI Data Register (SDIDAT)................................................................................................................		27-12
Chapter 28	High-Speed MMC Controller
Overview .......................................................................................................................................................		28-1
Features ........................................................................................................................................................		28-1
Block Diagram...............................................................................................................................................		28-2
SDI Special Registers ...................................................................................................................................		28-3
Configuration Register Types...............................................................................................................		28-3
System Address Register.....................................................................................................................		28-4
Block Size Register ..............................................................................................................................		28-5
Block Count Register............................................................................................................................		28-6
Argument Register ...............................................................................................................................		28-7
Transfer mode Register........................................................................................................................		28-7
Command Register ..............................................................................................................................		28-9
Response Register...............................................................................................................................		28-12
Buffer Data Port Register .....................................................................................................................		28-13
Present State Register .........................................................................................................................		28-13
Host Control Register ...........................................................................................................................		28-21
Power Control Register ........................................................................................................................		28-22
Block Gap Control Register..................................................................................................................		28-23
Wakeup Control Register .....................................................................................................................		28-25

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xvii

Table of Contents (Concluded)

Chapter 28	High-Speed MMC Controller
Clock Control Register..........................................................................................................................		28-26
Timeout Control Register......................................................................................................................		28-28
Software Reset Register.......................................................................................................................		28-29
Normal Interrupt Status Register ..........................................................................................................		28-30
Error Interrupt Status Register..............................................................................................................		28-34
Normal Interrupt Status Enable Register..............................................................................................		28-36
Error Interrupt Status Enable Register .................................................................................................		28-38
Normal Interrupt Signal Enable Register..............................................................................................		28-39
Error Interrupt Signal Enable Register..................................................................................................		28-41
Autocmd12 Error Status Register.........................................................................................................		28-42
Capabilities Register.............................................................................................................................		28-44
Maximum Current Capabilities Register...............................................................................................		28-46
Control Register 2.................................................................................................................................		28-47
Control Register 3 Register ..................................................................................................................		28-49
Host Controller Version Register ..........................................................................................................		28-50

Chapter 29	Electrical Data
Absolute Maximum Ratings...........................................................................................................................		29-1
Recommended Operating Conditions ...........................................................................................................		29-2
D.C. Electrical Characteristics.......................................................................................................................		29-4
A.C. Electrical Characteristics.......................................................................................................................		29-6

Chapter 30	Mechanical Data
Package Deimensions...................................................................................................................................		30-1

xviii

S3C2443X MICROCONTROLLER

List of Figures

Figure	Title	Page
Number		Number
1-1	S3C2443X Block Diagram ..................................................................................................	1-5
1-2	S3C2443X Pin Assignments (400-FBGA) Top view...........................................................	1-6
1-3	Memory Map .......................................................................................................................	1-33
2-1	System controller block diagram.........................................................................................	2-2
2-2	Power-on reset sequence...................................................................................................	2-4
2-3	Clock generator block diagram ...........................................................................................	2-6
2-4	PLL(Phase-Locked Loop) Block Diagram ..........................................................................	2-8
2-5	The case that changes slow clock by setting PMS valuenote2 .............................................	2-8
2-6	The clock distribution block diagram...................................................................................	2-9
2-7	MPLL Based clock domain .................................................................................................	2-10
2-8	EPLL Based clock domain ..................................................................................................	2-12
2-9	Power mode state diagram.................................................................................................	2-13
2-10	Entering STOP mode and exiting STOP mode (wake-up) .................................................	2-15
3-1	The configuration of MATRIX and Memory sub-system of S3C2443.................................	3-1
5-1	SMC Block Diagram............................................................................................................	5-3
5-2	SMC Core Block Diagram...................................................................................................	5-3
5-3	External Memory Two Output Enable Delay State Read ...................................................	5-4
5-4	Read Timing diagram (DRnCS = 1, DRnOWE = 0)............................................................	5-4
5-5	Read Timing Diagram (DRnCS = 1, DRnOWE = 1) ...........................................................	5-5
5-6	External burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read .............	5-6
5-7	External Synchronous Fixed Length Four Transfer Burst Read.........................................	5-7
5-8	External Memory Two Write Enable Delay State Write ......................................................	5-8
5-9	Write Timing Diagram (DRnCS = 1, DRnOWE = 0) ...........................................................	5-9
5-10	Write Timing Diagram (DRnCS = 1, DRnOWE = 1) ...........................................................	5-9
5-11	Synchronous Two Wait State Write ....................................................................................	5-10
5-12	Read, then wo Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)............	5-11
5-13	Memory Interface with 8-bit SRAM (512KB).......................................................................	5-12
5-14	Memory Interface with 16-bit SRAM (1MB) ........................................................................	5-12
6-1	Mobile DRAM Controller Block Diagram.............................................................................	6-2
6-2	Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ....................................................	6-4
6-3	Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks)...........................................	6-4
6-4	Memory Interface with 16-bit Mobile DDR ..........................................................................	6-5
7-1	NAND Flash Controller Block Diagram...............................................................................	7-2
7-2	NAND Flash Controller Boot Loader Block Diagram ..........................................................	7-2
7-3	CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0)................................................	7-4
7-4	nWE & nRE Timing (TWRPH0=0, TWRPH1=0).................................................................	7-4
7-5	NAND Flash Memory Mapping ...........................................................................................	7-10
7-6	A 8-bit NAND Flash Memory Interface ...............................................................................	7-11
7-7	Two 8-bit NAND Flash Memory Interface ...........................................................................	7-11
7-8	A 16-bit NAND Flash Memory Interface .............................................................................	7-11

S3C2443X MICROCONTROLLER

xix

List of Figures (Continued)

Figure	Title	Page
Number		Number
8-1	CF Controller Top Block Diagram .......................................................................................	8-3
8-2	PC Card Controller Top Block Diagram ..............................................................................	8-4
8-3	ATA Controller Top Block Diagram .....................................................................................	8-5
8-4	PC Card State Definition .....................................................................................................	8-6
8-5	PIO Mode Waveform...........................................................................................................	8-7
8-6	UDMA - In operation (terminated by device).......................................................................	8-8
8-7	UDMA - In Operation (terminated by host)..........................................................................	8-8
8-8	UDMA - Out Operation (terminated by device) ...................................................................	8-9
8-9	UDMA - Out Operation (terminated by host).......................................................................	8-9
8-10	Memory Map Diagram.........................................................................................................	8-11
9-1	Basic DMA Timing Diagram ................................................................................................	9-4
9-2	Demand/Handshake Mode Comparison.............................................................................	9-5
9-3	Burst 4 Transfer size ...........................................................................................................	9-6
9-4	Single service, Demand Mode, Single Transfer Size..........................................................	9-7
9-5	Single service, Handshake Mode, Single Transfer Size.....................................................	9-7
9-6	Whole service, Handshake Mode, Single Transfer Size.....................................................	9-7
10-1	Interrupt Process Diagram ..................................................................................................	10-1
10-2	Priority Generating Block.....................................................................................................	10-4
12-1	Watchdog Timer Block Diagram .........................................................................................	12-2
13-1	16-bit PWM Timer Block Diagram.......................................................................................	13-2
13-2	Timer Operations.................................................................................................................	13-3
13-3	Example of Double Buffering Function................................................................................	13-4
13-4	Example of a Timer Operation ............................................................................................	13-6
13-5	Example of PWM.................................................................................................................	13-7
13-6	Inverter On/Off.....................................................................................................................	13-8
13-7	The Wave Form When a Dead Zone Feature is Enabled...................................................	13-9
13-8	Timer4 DMA Mode Operation .............................................................................................	13-10
14-1	Real Time Clock Block Diagram .........................................................................................	14-2
14-2	RTC tick interrupt clock scheme .........................................................................................	14-5
14-3	Main Oscillator Circuit Example ..........................................................................................	14-5
15-1	UART Block Diagram (with FIFO) .......................................................................................	15-2
15-2	UART AFC interface............................................................................................................	15-4
15-3	Example showing UART Receiving 5 Characters with 2 Errors .........................................	15-6
15-4	IrDA Function Block Diagram..............................................................................................	15-8
15-5	Serial I/O Frame Timing Diagram (Normal UART) .............................................................	15-9
15-6	Infrared Transmit Mode Frame Timing Diagram.................................................................	15-9
15-7	Infrared Receive Mode Frame Timing Diagram..................................................................	15-9
15-8	nCTS and Delta CTS Timing Diagram ................................................................................	15-18

xx	S3C2443X MICROCONTROLLER

List of Figures (Continued)

Figure	Title	Page
Number		Number
16-1	USB Host Controller Block Diagram ...................................................................................	16-1
17-1	USB2.0 Block Diagram .......................................................................................................	17-2
17-2	USB2.0 Function Block Diagram ........................................................................................	17-3
17-3	OUT Transfer Operation Flow ............................................................................................	17-34
17-4	IN Transfer Operation Flow.................................................................................................	17-35
18-1	IIC-Bus Block Diagram........................................................................................................	18-2
18-2	Start and Stop Condition.....................................................................................................	18-3
18-3	IIC-Bus Interface Data Format............................................................................................	18-4
18-4	Data Transfer on the IIC-Bus..............................................................................................	18-5
18-5	Acknowledge on the IIC-Bus...............................................................................................	18-5
18-6	Operations for Master/Transmitter Mode............................................................................	18-7
18-7	Operations for Master/Receiver Mode................................................................................	18-8
18-8	Operations for Slave/Transmitter Mode..............................................................................	18-9
18-9	Operations for Slave/Receiver Mode..................................................................................	18-10
19-1	SPI Block Diagram..............................................................................................................	19-2
19-2	SPI Transfer Format ...........................................................................................................	19-4
19-3	SPI Slave Rx mode with Format B (1-Byte Buffer mode)...................................................	19-6
20-1	HS-SPI Interface block diagram .........................................................................................	20-2
20-2	HS-SPI Transfer Format .....................................................................................................	20-4
21-1	LCD Controller Block Diagram............................................................................................	21-3
21-2	Monochrome Display Types (STN).....................................................................................	21-12
21-3	Color Display Types (STN) .................................................................................................	21-13
21-4	8-bit Single Scan Display Type STN LCD Timing ..............................................................	21-15
21-7	Example of Scrolling in Virtual Display (Single Scan) ........................................................	21-16
22-1	Top block diagram Display Controller.................................................................................	22-2
22-2	Block diagram of the Data Flow..........................................................................................	22-5
22-3	16BPP(5:6:5) Display Types...............................................................................................	22-22
22-4	Blending Diagram ...............................................................................................................	22-25
22-5	Color-key function configurations .......................................................................................	22-26
22-6	Example of Scrolling in Virtual Display ...............................................................................	22-28
22-7	LCD RGB interface Timing .................................................................................................	22-29
22-8	WRITE Cycle Timing...........................................................................................................	22-30

S3C2443X MICROCONTROLLER

xxi

List of Figures (Continued)

Figure	Title	Page
Number		Number
23-1	Camera interface overview .................................................................................................	23-1
23-2	ITU-R BT 601 Input timing diagram ....................................................................................	23-3
23-3	ITU-R BT 656 Input timing diagram ....................................................................................	23-3
23-4	Sync signal timing diagram .................................................................................................	23-4
23-5	IO connection guide ............................................................................................................	23-5
23-6	Two DMA ports....................................................................................................................	23-6
23-7	CAMIF clock generation......................................................................................................	23-7
23-8	Ping-pong Memory Hierarchy .............................................................................................	23-8
23-9	Memory storing style ...........................................................................................................	23-9
23-10	Timing diagram for register setting......................................................................................	23-11
23-11	iming diagram for last IRQ...................................................................................................	23-13
23-12	MSDMA or External Camera interface (only CAMIFpreview path).....................................	23-13
23-13	Window offset scheme (WinHorOfst2 & WinVerOfst2 are assigned in the
	CIWDOFST2 register) .........................................................................................................	23-15
23-14	Interrupt generation scheme ...............................................................................................	23-17
23-16	Scaling scheme ...................................................................................................................	23-26
23-17	Preview image mirror and rotation ......................................................................................	23-32
23-18	Capture codec dma frame control.......................................................................................	23-38
23-19	Scan line offset....................................................................................................................	23-39
23-20	Image effect result...............................................................................................................	23-40
23-21	ENVID_MS SFR setting when DMA start to read memory data.........................................	23-46
23-22	SFR & Operation (related each DMA when selected MSDMA input path).........................	23-46
24-1	ADC and Touch Screen Interface Block Diagram...............................................................	24-2
24-2	Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode ................................	24-5
25-1	IIS-Bus Block Diagram ........................................................................................................	25-2
25-2	IIS Clock Control Block Diragram........................................................................................	25-3
25-3	IIS Audio Serial Data Formats.............................................................................................	25-5
26-1	AC97 Block Diagram ...........................................................................................................	26-2
26-2	Internal Data Path ...............................................................................................................	26-3
26-3	AC97 Operation Flow Chart ................................................................................................	26-4
26-4	Bi-directional AC-link Frame with Slot Assignments ...........................................................	26-5
26-5	AC-link Output Frame..........................................................................................................	26-6
26-6	AC-link Input Frame ............................................................................................................	26-6
26-7	AC97 Powerdown Timing....................................................................................................	26-7
26-8	AC97 Power down/Power up Flow......................................................................................	26-8
27-1	SD Interface block diagram.................................................................................................	27-1

xxii	S3C2443X MICROCONTROLLER

List of Figures (Continued)

Figure	Title	Page
Number		Number
28-1	HSMMC block diagram .......................................................................................................	28-2
28-2	Card Detect State ...............................................................................................................	28-18
28-3	Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer ..........	28-19
28-4	Timing of Command Inhibit (DAT) for the case of response with busy ..............................	28-19
28-5	Timing of Command Inhibit (CMD) for the case of no response command .......................	28-19
29-1	XTIpll Clock Timing .............................................................................................................	29-6
29-2	EXTCLK Clock Input Timing ...............................................................................................	29-6
29-3	EXTCLK/HCLK in case that EXTCLK is used without the PLL ..........................................	29-6
29-4	HCLK/CLKOUT/SCLK in case that EXTCLK is used .........................................................	29-7
29-5	Manual Reset Input Timing .................................................................................................	29-7
29-6	Power-On Oscillation Setting Timing ..................................................................................	29-8
29-7	Sleep Mode Return Oscillation Setting Timing ...................................................................	29-9
29-8	SMC Synchronous Read Timing ........................................................................................	29-10
29-9	SMC Asynchronous Read Timing.......................................................................................	29-10
29-10	SMC Asynchronous Write Timing.......................................................................................	29-11
29-11	SMC Synchronous Write Timing.........................................................................................	29-11
29-12	SMC Wait Timing ................................................................................................................	29-12
29-13	Nand Flash Timing..............................................................................................................	29-13
29-14	SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit).........................	29-14
29-15	SDRAM MRS Timing ..........................................................................................................	29-15
29-16	SDRAM Auto Refresh Timing (Trp = 2, Trc = 4).................................................................	29-16
29-17	External DMA Timing (Handshake, Single transfer)...........................................................	29-17
29-18	TFT LCD Controller Timing.................................................................................................	29-17
29-19	IIS Interface Timing (I2S Master Mode Only) .....................................................................	29-18
29-20	IIS Interface Timing (I2S Slave Mode Only) .......................................................................	29-18
29-21	IIC Interface Timing.............................................................................................................	29-18
29-22	SD/MMC Interface Timing...................................................................................................	29-19
29-23	SPI Interface Timing (CPHA = 1, CPOL = 1)......................................................................	29-20
29-24	High Speed SPI Interface Timing (CPHA = 0, CPOL = 0)..................................................	29-20
29-25	USB Timing (Data signal rise/fall time) ...............................................................................	29-21
29-26	High Speed SDMMC Interface Timing................................................................................	29-21
30-1	400-FBGA-1313 Package Dimension 1(Top View) ............................................................	30-1
30-2	400-FBGA-1313 Package Dimension 1(Bottom View).......................................................	30-2

S3C2443X MICROCONTROLLER

xxiii

List of Tables

Table	Title	Page
Number		Number
1-1	400-Pin FBGA Pin Assignments – Pin Number Order (1/4) ...............................................	1-7
1-2	S3C2443X 400-Pin FBGA Pin Assignments (Sheet 1 of 12,TBD) .....................................	1-11
1-3	S3C2443X Signal Descriptions ...........................................................................................	1-26
1-4	S3C2443X Operation Mode Description.............................................................................	1-32
1-5	S3C2443X Special Registers..............................................................................................	1-35
2-1	Registers & GPIO status in RESET (R: reset, S: sustain previous value)..........................	2-5
2-2	Clock source selection for the main PLL and clock generation logicnote1 ............................	2-6
2-3	Clock source selection for the EPLL ...................................................................................	2-7
2-4	Clock division ratio of MPLL region.....................................................................................	2-10
2-5	ECLK Control ......................................................................................................................	2-12
2-6	The status of PLL and ARMCLK after wake-up ..................................................................	2-16
2-7	Power saving mode entering/exiting condition....................................................................	2-17
2-8	System Controller Address Map .........................................................................................	2-18
8-1	Timing Parameter Each PIO Mode .....................................................................................	8-7
8-2	Timing Parameter Each UDMA Mode.................................................................................	8-10
8-3	Memory Map Table .............................................................................................................	8-12
9-1	DMA request sources for each channel..............................................................................	9-2
11-1	S3C2443X Port Configuration.............................................................................................	11-2
15-1	Interrupts in Connection with FIFO .....................................................................................	15-5
15-2	Recommended value table of DIVSLOTn register..............................................................	15-20
16-1	OHCI Registers for USB Host Controller ............................................................................	16-2
17-1	Non-Indexed Registers........................................................................................................	17-4
17-2	Indexed Registers ...............................................................................................................	17-5
20-1	External signals description ................................................................................................	20-3
21-1	Relation Between VCLK and CLKVAL (STN, HCLK = 60MHz)..........................................	21-5
21-2	Dither Duty Cycle Examples................................................................................................	21-7
21-3	LCDCNTL (STN) / DISPCON (TFT) Port Muxing Table .....................................................	21-17
21-4	MV Value for Each Display Mode .......................................................................................	21-29
22-1	25(A:8:8:8) Palette Data Format .........................................................................................	22-20
22-2	19BPP (A:6:6:6) Palette Data Format .................................................................................	22-21
22-3	16BPP(A:5:5:5) Palette Data Format ..................................................................................	22-21
22-4	Relation between VCLK and CLKVAL (TFT, Freq. of Video Clock Source=60MHz) .........	22-27
22-5	LCD RGB I/F signals ...........................................................................................................	22-31
22-6	CPU I/F (i80-System Interface) ...........................................................................................	22-31
22-7	LCDCNTL (STN) / DISPCON (TFT) Port Muxing Table .....................................................	22-32

xxiv	S3C2443X MICROCONTROLLER

List of Tables (Continued)

Table	Title	Page
Number		Number
23-1	Camera interface signal description ...................................................................................	23-2
23-2	Video timing reference codes of ITU-656 format................................................................	23-4
23-3	Sync signal timing requirement...........................................................................................	23-4
25-1	CODEC clock (CODECLK = 256, 384, 512 or 768fs) ........................................................	25-6
25-2	IIS clock mapping table.......................................................................................................	25-6
28-1	Determination of Transfer Type ..........................................................................................	28-8
28-2	Relation Between Parameters and the Name of Response Type......................................	28-11
28-3	Response Bit Definition for Each Response Type..............................................................	28-12
28-4	The relation between Command CRC Error and Command Timeout Error.......................	28-34
28-5	The relation between Command CRC Error and Command Timeout Error.......................	28-42
28-6	Maximum Current Value Definition .....................................................................................	28-45
29-1	Absolute Maximum Rating ..................................................................................................	29-1
29-2	Recommended Operating Conditions.................................................................................	29-2
29-3	Normal I/O PAD DC Electrical Characteristics ...................................................................	29-4
29-4	Special Memory DDR I/O PAD DC Electrical Characteristics ............................................	29-5
29-5	USB DC Electrical Characteristics......................................................................................	29-5
29-6	RTC OSC DC Electrical Characteristics.............................................................................	29-5
29-12	Clock Timing Constants ......................................................................................................	29-22
29-13	SSMC Timing Constants.....................................................................................................	29-23
29-14	NFCON Bus Timing Constants...........................................................................................	29-23
29-15	Memory Interface Timing Constants (SDRAM) ..................................................................	29-24
29-16	DMA Controller Module Signal Timing Constants ..............................................................	29-25
29-17	TFT LCD Controller Module Signal Timing Constants .......................................................	29-25
29-18	IIS Controller Module Signal Timing Constants(I2S Master Mode Only) ...........................	29-25
29-19	IIS Controller Module Signal Timing Constants(I2S Slave Mode Only) .............................	29-26
29-20	IIC BUS Controller Module Signal Timing...........................................................................	29-26
29-21	SD/MMC Interface Transmit/Receive Timing Constants ....................................................	29-27
29-22	SPI Interface Transmit/Receive Timing Constants.............................................................	29-27
29-23	High Speed SPI Interface Transmit/Receive Timing Constants.........................................	29-27
29-24	USB Electrical Specifications..............................................................................................	29-28
29-25	USB Full Speed Output Buffer Electrical Characteristics ...................................................	29-29
29-26	USB High Speed Output Buffer Electrical Characteristics..................................................	29-29
29-27	High Speed SDMMC Interface Transmit/Receive Timing Constants .................................	29-29

S3C2443X MICROCONTROLLER

xxv

NOTES

xxvi	S3C2443X MICROCONTROLLER

S3C2443X RISC MICROPROCESSOR	PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2443X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2443X is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2443X includes the following components.

The S3C2443X is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for costand power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2443X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2443X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

•Around 400MHz @ 1.3V, 533MHz @ 1.375V Core, 1.8V/2.5V/3.3V ROM/SRAM, 1.8V/2.5V/3.3V SDRAM, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU

•External memory controller (SDRAM Control and Chip Select logic) and CF/ATA I/F controller

•LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA

•6-ch DMA controllers with external request pins

•4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

•2-ch SPls (1-ch High Speed SPI)

•IIC bus interface (multi-master support)

•IIS Audio CODEC interface & AC97 CODEC Interface

•SD Host interface version 1.0 & MMC Protocol version 2.11 compatible

•High-Speed MMC Protocol version 4.0 compatible

•2-ch USB Host controller (ver 1.1 Complaint)/1-ch USB Device controller (ver 2.0 Complaint)

•4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

•10-ch 10-bit ADC and Touch screen interface

•RTC with calendar function

•Camera interface (Max. 8M pixels input support. 2M pixel input support for scaling)

•147 General Purpose I/O ports / 24-ch external interrupt source

•Power control: Normal, Idle, Stop and Sleep mode

•On-chip clock generator with PLL

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PRODUCT OVERVIEW	S3C2443X RISC MICROPROCESSOR

FEATURES

Architecture

•Integrated system for hand-held devices and general embedded applications.

•16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core.

•Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.

•Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

•ARM920T CPU core supports the ARM debug architecture.

•Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).

System Manager

•Little/Big Endian support.

•Two independent memory bus - one for the ROM/SRAM bus (ROM Bank0~Bank5) and one for the DRAM bus (SDRAM Bank0~Bank1)

•Address space: 64M bytes for Rom bank0 ~ bank5, 128M bytes for SDRAM bank0 ~ bank1.

•Supports programmable 8/16-bit data bus width for ROM/SRAM bank and programmable 16/32bit data bus width for DRAM bank

•Fixed bank start address from Rom bank 0 to bank 5 and SDRAM bank 0 to bank1.

•Eight memory banks:

–Six memory banks for ROM, SRAM, and others (NAND/CF etc.).

–Two memory banks for Synchronous DRAM.

•Complete Programmable access cycles for all memory banks.

•Supports external wait signals to expand the bus cycle.

•Supports self-refresh mode in SDRAM for power-down.

•Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, OneNAND and others).

NAND Flash Boot Loader

•Supports booting from NAND flash memory. (Only 8bit boot support)

•4KB internal buffer for booting.

•Supports storage memory for NAND flash memory after booting.

•Supports Advanced NAND flash

Cache Memory

•64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB).

•8words length per line with one valid bit and two dirty bits per line.

•Pseudo random or round robin replacement algorithm.

•Write-through or write-back cache operation to update the main memory.

•The write buffer can hold 16 words of data and four addresses.

Clock & Power Manager

•On-chip MPLL and EPLL:

EPLL generates the clock to operate USB Host, IIS, UART, etc.

MPLL generates the clock to operate MCU at maximum 533Mhz @ 1.375V.

•Clock can be fed selectively to each function block by software.

•Power mode: Normal, Idle, STOP and Sleep mode

Normal mode: Normal operating mode

Idle mode: The clock for only CPU is stopped. STOP mode: All clocks are stopped.

Sleep mode: The Core power including all peripherals is shut down.

•Woken up by EINT[15:0] or RTC alarm & tick interrupt from Sleep mode and STOP mode.

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