Samsung S3C2440A User Manual

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Page 1

S3C2440A

32-BIT RISC

MICROPROCESSOR

USER'S MANUAL

PRELIMINARY

Revision 0.14

(June 30, 2004)

Page 2

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2440A 16/32- bit RISC m icroproc essor . SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.

The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a m emory complier. Its lowpower, simple, elegant and fully static design is partic ularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2440A offers outstanding f eatures with its CPU core, a 16/32-bit ARM920T RISC process or designed by Advanced RISC Machines, Ltd. The ARM920T im plements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals , the S3C2440A minimizes overall system costs and eliminates the need to configure additional components. The integrated on-c hip func tions that are des cribed in this document include:

• Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-

Cache/MMU

• External memory controller (SDRAM Control and Chip Select logic)

• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA

• 4-ch DMA controllers with external request pins

• 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 2-ch SPls

• IIC bus interface (multi-master support)

• IIS Audio CODEC interface

• AC’97 CODEC interface

• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible

• 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 8-ch 10-bit ADC and Touch screen interface

• RTC with calendar function

• Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)

• 130 General Purpose I/O ports / 24-ch external interrupt source

• Power control: Normal, Slow, Idle and Sleep mode

• On-chip clock generator with PLL

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

FEATURES

Architecture

• Integrated system for hand-held devices and

general embedded applications.

• 16/32-Bit RISC architecture and powerful

instruction set with ARM920T CPU core.

• Enhanced ARM architecture MMU to support

WinCE, EPOC 32 and Linux.

• Instruction cache, data cache, write buffer and

Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

• ARM920T CPU core supports the ARM debug

architecture.

• Internal Advanced Microcontroller Bus

Architecture (AMBA) (AMBA2.0, AHB/APB).

System Manager

• Little/Big Endian support.

• Support Fast bus mode and Asynchronous bus

mode.

• Address space: 128M bytes for each bank (total

1G bytes).

• Supports programmable 8/16/32-bit data bus

width for each bank.

• Fixed bank start address from bank 0 to bank 6.

• Programmable bank start address and bank size

for bank 7.

• Eight memory banks:

– Six memory banks for ROM, SRAM, and others. – Two memory banks for ROM/SRAM/ Synchronous DRAM.

• Complete Programmable access cycles for all

memory banks.

• Supports external wait signals to expand the bus

cycle.

NAND Flash Boot Loader

• Supports booting from NAND flash memory.

• 4KB internal buffer for booting.

• Supports storage memory for NAND flash

memory after booting.

• Supports Advanced NAND flash

Cache Memory

• 64-way set-associative cache with I-Cache

(16KB) and D-Cache (16KB).

• 8words length per line with one valid bit and two

dirty bits per line.

• Pseudo random or round robin replacement

algorithm.

• Write-through or write-back cache operation to

update the main memory.

• The write buffer can hold 16 words of data and

four addresses.

Clock & Power Manager

• On-chip MPLL and UPLL:

UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400Mhz @ 1.3V.

• Clock can be fed selectively to each function

block by software.

• Power mode: Normal, Slow, Idle, and Sleep

mode

Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Sleep mode: The Core power including all

peripherals is shut down.

• Woken up by EINT[15:0] or RTC alarm interrupt

from Sleep mode

• Supports self-refresh mode in SDRAM for power-

down.

• Supports various types of ROM for booting

(NOR/NAND Flash, EEPROM, and others).

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

FEATURES (Continued)

Interrupt Controller

• 60 Interrupt sources

(One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera), 1 AC97

• Level/Edge mode on external interrupt source

• Programmable polarity of edge and level

• Supports Fast Interrupt request (FIQ) for very

urgent interrupt request

Timer with Pulse Width Modulation (PWM)

• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal

timer with DMA-based or interrupt-based operation

• Programmable duty cycle, frequency, and polarity

• Dead-zone generation

• Supports external clock sources

RTC (Real Time Clock)

• Full clock feature: msec, second, minute, hour,

date, day, month, and year

• 32.768 KHz operation

• Alarm interrupt

• Time tick interrupt

General Purpose Input/Output Ports

• 24 external interrupt ports

• 130 Multiplexed input/output ports

gray levels, 256 colors and 4096 colors for STN LCD

• Supports multiple screen size

– Typical actual screen size: 640x480, 320x240,

160x160, and others. – Maximum frame buffer size is 4 Mbytes. – Maximum virtual screen size in 256 color mode:

4096x1024, 2048x2048, 1024x4096 and others

TFT(Thin Film Transistor) Color Displays Feature

• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette

color displa ys for color TFT

• Supports 16, 24 bpp non-palette true-color

displays for color TFT

• Supports maximum 16M color TFT at 24 bpp

mode

• LPC3600 Timing controller embedded for

LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait / 256K-color/ Reflective a-Si TFT LCD)

• LCC3600 Timing controller embedded for

LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait / 256K-color/ Transflective a-Si TFT LCD)

• Supports multiple screen size

– Typical actual screen size: 640x480, 320x240,

160x160, and others. – Maximum frame buffer size is 4Mbytes. – Maximum virtual screen size in 64K color mode :

2048x1024, and others

UART

DMA Controller

• 4-ch DMA controller

• Supports memory to memory, IO to memory,

memory to IO, and IO to IO transfers

• Burst transfer mode to enhance the transfer rate

LCD Controller STN LCD Displays Feature

• Supports 3 types of STN LCD panels: 4-bit dual

scan, 4-bit single scan, 8-bit single scan display type

• Supports monochrome mode, 4 gray levels, 16

1-3

• 3-channel UART with DMA-based or interrupt-

based operation

• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data

transmit/receive (Tx/Rx)

• Supports external clocks for the UART operation

(UEXTCLK)

• Programmable baud rate

• Supports IrDA 1.0

• Loopback mode for testing

• Each channel has internal 64-byte Tx FIFO and

64-byte Rx FIFO.

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

FEATURES (Continued)

A/D Converter & Touch Screen Interface

• 8-ch multiplexed ADC

• Max. 500KSPS and 10-bit Resolution

• Internal FET for direct Touch screen interface

Watchdog Timer

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

IIC-Bus Interface

• 1-ch Multi-Master IIC-Bus

• Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode.

IIS-Bus Interface

• 1-ch IIS-bus for audio interface with DMA-based

operation

• Serial, 8-/16-bit per channel data transfers

• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx

• Supports IIS format and MSB-justified data format

AC97 Audio-CODEC Interface

• Support 16-bit samples

• 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs

• DMA burst4 access support(only word transfer)

• Compatible with SD Memory Card Protocol

version 1.0

• Compatible with SDIO Card Protocol version 1.0

• 64 Bytes FIFO for Tx/Rx

• Compatible with Multimedia Card Protocol version

2.11

SPI Interface

• Compatible with 2-ch Serial Peripheral Interface

Protocol version 2.11

• 2x8 bits Shift register for Tx/Rx

• DMA-based or interrupt-based operation

Camera Interface

• ITU-R BT 601/656 8-bit mode support

• DZI (Digital Zoom In) capability

• Programmable polarity of video sync signals

• Max. 4096 x 4096 pixels input support ( 2048 x

2048 pixel input support for scaling)

• Image mirror and rotation (X-axis mirror, Y-axis

mirror, and 180° rotation)

• Camera output format (RGB 16/24-bit and YCbCr

4:2:0/4:2:2 format)

1-ch MIC input

USB Host

• 2-port USB Host

• Complies with OHCI Rev. 1.0

• Compatible with USB Specification version 1.1

USB Device

• 1-port USB Device

• 5 Endpoints for USB Device

• Compatible with USB Specification version 1.1

SD Host Interface

• Normal, Interrupt and DMA data transfer

mode(byte, halfword, word transfer)

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Operating Voltage Range

• Core : 1.20V for 300MHz

1.30V for 400MHz Memory:1.8V/ 2.5V/3.0V/3.3V

• I/O : 3.3V

Operating Frequency

• Fclk Up to 400MHz

• Hclk Up to 136MHz

• Pclk Up to 68MHz

Package

• 289-FBGA

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

BLOCK DIAGRAM

ARM920T

IVA[31:0]

JTAG

Clock Generator

(MPLL)

IPA[31:0]

Instruction

MMU

C13

ARM9TDMI

Processor core

(Internal Embedded ICE)

C13

Data

MMU

LCD

CONT.

USB Host CONT.

ExtMaster

NAND Ctrl.

NAND Flash Boot

Loader

DPA[31:0]

LCD

DMA

Instruction

CACHE

(16KB)

ID[31:0]

CP15

DD[31:0]

DVA[31:0]DVA[31:0]

Data

CACHE

(16KB)

A H B

B U S

Bridge & DMA (4Ch)

External

Coproc

Interface

Write

Buffer

WriteBack

PA Tag

RAM

BUS CONT.

Arbitor/Decode

Interrupt CONT.

Power

Management

Camera

Interface

Memory CONT.

SRAM/NOR/SDRAM

AMBA

Bus

I/F

WBPA[31:0]

UART 0, 1, 2

USB Device

I2C

I2S

SDI/MMC

Watchdog

Timer

BUS CONT.

Arbitor/Decode

SPI 0, 1

SPI

P B

B U S

Figure 1-1. S3C2440A Block Diagram

1-5

GPIO

RTC

ADC

Timer/PWM

0 ~ 3, 4(Internal)

AC97

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

PIN ASSIGNMENTS

1234567891011121314151617

BOTTOM VIEW

Figure 1-2. S3C2440A Pin Assignments (289-FBGA)

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

A1 VDDi C1 VDDMOP E1 nFRE/GPA20 A2 SCKE C2 nGCS5/GPA16 E2 VSSMOP A3 VSSi C3 nGCS2/GPA13 E3 nGCS7 A4 VSSi C4 nGCS3/GPA14 E4 nWAIT A5 VSSMOP C5 nOE E5 nBE3 A6 VDDi C6 nSRAS E6 nWE A7 VSSMOP C7 ADDR4 E7 ADDR1 A8 ADDR10 C8 ADDR11 E8 ADDR6 A9 VDDMOP C9 ADDR15 E9 ADDR14 A10 VDDi C10 ADDR21/GPA6 E10 ADDR23/GPA8 A11 VSSMOP C11 ADDR24/GPA9 E11 DATA2 A12 VSSi C12 DATA1 E12 DATA20 A13 DATA3 C13 DATA6 E13 DATA19 A14 DATA7 C14 DATA11 E14 DATA18 A15 VSSMOP C15 DATA13 E15 DATA17 A16 VDDi C16 DATA16 E16 DATA21 A17 DATA10 C17 VSSi E17 DATA24 B1 VSSMOP D1 ALE/GPA18 F1 VDDi B2 nGCS1/GPA12 D2 nGCS6 F2 VSSi B3 SCLK1 D3 nGCS4/GPA15 F3 nFWE/GPA19 B4 SCLK0 D4 nBE0 F4 nFCE/GPA22 B5 nBE1 D5 nBE2 F5 CLE/GPA17 B6 VDDMOP D6 nSCAS F6 nGCS0 B7 ADDR2 D7 ADDR7 F7 ADDR0/GPA0 B8 ADDR9 D8 ADDR5 F8 ADDR3 B9 ADDR12 D9 ADDR16/GPA1 F9 ADDR18/GPA3 B10 VSSi D10 ADDR20/GPA5 F10 DATA4 B11 VDDi D11 ADDR26/GPA11 F11 DATA5 B12 VDDMOP D12 DATA0 F12 DATA27 B13 VSSMOP D13 DATA8 F13 DATA31 B14 VDDMOP D14 DATA14 F14 DATA26 B15 DATA9 D15 DATA12 F15 DATA22 B16 VDDMOP D16 VSSMOP F16 VDDi B17 DATA15 D17 VSSMOP F17 VDDMOP

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 3)

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

G1 VSSOP J1 VDDOP L1 LEND/GPC0 G2 CAMHREF/GPJ10 J2 VDDiarm L2 VDDiarm G3 CAMDATA1/GPJ1 J3 CAMCLKOUT/GPJ11 L3 nXDACK0/GPB9 G4 VDDalive J4 CAMRESET/GPJ12 L4 VCLK/GPC1 G5 CAMPCLK/GPJ8 J5 TOUT1/GPB1 L5 nXBREQ/GPB6 G6 FRnB J6 TOUT0/GPB0 L6 VD1/GPC9 G7 CAMVSYNC/GPJ9 J7 TOUT2/GPB2 L7 VFRAME/GPC3 G8 ADDR8 J8 CAMDATA6/GPJ6 L8 I2SSDI/AC_SDATA_IN G9 ADDR17/GPA2 J9 SDDAT3/GPE10 L9 SPICLK0/GPE13 G10 ADDR25/GPA10 J10 EINT10/nSS0/GPG2 L10 EINT15/SPICLK1/GPG7 G11 DATA28 J11 TXD2/nRTS1/GPH6 L11 EINT22/GPG14 G12 DATA25 J12 PWREN L12 Xtortc G13 DATA23 J13 TCK L13 EINT2/GPF2 G14 XTIpll J14 TMS L14 EINT5/GPF5 G15 XTOpll J15 RXD2/nCTS1/GPH7 L15 EINT6/GPF6 G16 DATA29 J16 TDO L16 EINT7/GPF7 G17 VSSi J17 VDDalive L17 nRTS0/GPH1 H1 VSSiarm K1 VSSiarm M1 VLINE/GPC2 H2 CAMDATA7/GPJ7 K2 nXBACK/GPB5 M2 LCD_LPCREV/GPC6 H3 CAMDATA4/GPJ4 K3 TOUT3/GPB3 M3 LCD_LPCOE/GPC5 H4 CAMDATA3/GPJ3 K4 TCLK0/GPB4 M4 VM/GPC4 H5 CAMDATA2/GPJ2 K5 nXDREQ1/GPB8 M5 VD9/GPD1 H6 CAMDATA0/GPJ0 K6 nXDREQ0/GPB10 M6 VD6/GPC14 H7 CAMDATA5/GPJ5 K7 nXDACK1/GPB7 M7 VD16/SPIMISO1/GPD8 H8 ADDR13 K8 SDCMD/GPE6 M8 SDDAT1/GPE8 H9 ADDR19/GPA4 K9 SPIMISO0/GPE11 M9 IICSDA/GPE15 H10 ADDR22/GPA7 K10 EINT13/SPIMISO1/GPG5 M10 EINT20/GPG12 H11 VSSOP K11 nCTS0/GPH0 M11 EINT17/nRTS1/GPG9 H12 EXTCLK K12 VDDOP M12 VSSA_UPLL H13 DATA30 K13 TXD0/GPH2 M13 VDDA_UPLL H14 nBATT_FLT K14 RXD0/GPH3 M14 Xtirtc H15 nTRST K15 UEXTCLK/GPH8 M15 EINT3/GPF3 H16 nRESET K16 TXD1/GPH4 M16 EINT1/GPF1 H17 TDI K17 RXD1/GPH5 M17 EINT4/GPF4

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 3)

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

N1 VSSOP R1 VD3/GPC11 U1 VDDiarm N2 VD0/GPC8 R2 VD8/GPD0 U2 VDDiarm N3 VD4/GPC12 R3 VD11/GPD3 U3 VSSOP N4 VD2/GPC10 R4 VD13/GPD5 U4 VSSiarm N5 VD10/GPD2 R5 VD18/SPICLK1/GPD10 U5 VD23/nSS0/GPD15 N6 VD15/GPD7 R6 VD21 /GPD13 U6 I2SSDO/AC_SDATA_OUT N7 VD22/nSS1/GPD14 R7 I2SSCLK/AC_BIT_CLK U7 VSSiarm N8 SDCLK/GPE5 R8 SDDAT0/GPE7 U8 IICSCL/GPE14 N9 EINT8/GPG0 R9 CLKOUT0/GPH9 U9 VSSOP N10 EINT18/nCTS1/GPG10 R10 EINT11/nSS1/GPG3 U10 VSSiarm N11 DP0 R11 EINT14/SPIMOSI1/GPG6 U11 VDDi N12 DN1/PDN0 R12 NCON U12 EINT19/TCLK1/GPG11 N13 nRSTOUT/GPA21 R13 OM1 U13 EINT23/GPG15 N14 MPLLCAP R14 AIN0 U14 DP1/PDP0 N15 VDD_RTC R15 AIN2 U15 VSSOP N16 VDDA_MPLL R16 XM/AIN6 U16 Vref N17 EINT0/GPF0 R17 VSSA_MPLL U17 AIN1 P1 LCD_LPCREVB/GPC7 T1 VSSiarm P2 VD5/GPC13 T2 VSSiarm P3 VD7/GPC15 T3 VDDOP P4 VD12/GPD4 T4 VD17/SPIMOSI1/GPD9 P5 VD14/GPD6 T5 VD19/GPD11 P6 VD20/GPD12 T6 VDDiarm P7 I2SLRCK/AC_SYNC T7 CDCLK/AC_nRESET P8 SDDAT2/GPE9 T8 VDDiarm P9 SPIMOSI0/GPE12 T9 EINT9/GPG1 P10 CLKOUT1/GPH10 T10 EINT16/GPG8 P11 EINT12/LCD_PWREN/GPG4 T11 EINT21/GPG13 P12 DN0 T12 VDDOP P13 OM2 T13 OM3 P14 VDDA_ADC T14 VSSA_ADC P15 AIN3 T15 OM0 P16 XP/AIN7 T16 YM/AIN4 P17 UPLLCAP T17 YP/AIN5

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

F7 ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) t10s E7 ADDR1 ADDR1 Hi-z O(L) O(L) t10s B7 ADDR2 ADDR2 Hi-z O(L) O(L) t10s

F8 ADDR3 ADDR3 Hi-z O(L) O(L) t10s C7 ADDR4 ADDR4 Hi-z O(L) O(L) t10s D8 ADDR5 ADDR5 Hi-z O(L) O(L) t10s E8 ADDR6 ADDR6 Hi-z O(L) O(L) t10s D7 ADDR7 ADDR7 Hi-z O(L) O(L) t10s

G8 ADDR8 ADDR8 Hi-z O(L) O(L) t10s

B8 ADDR9 ADDR9 Hi-z O(L) O(L) t10s A8 ADDR10 ADDR10 Hi-z O(L) O(L) t10s C8 ADDR11 ADDR11 Hi-z O(L) O(L) t10s B9 ADDR12 ADDR12 Hi-z O(L) O(L) t10s H8 ADDR13 ADDR13 Hi-z O(L) O(L) t10s E9 ADDR14 ADDR14 Hi-z O(L) O(L) t10s C9 ADDR15 ADDR15 Hi-z O(L) O(L) t10s D9 ADDR16/GPA1 ADDR16 Hi-z/– O(L)/– O(L) t10s

G9 ADDR17/GPA2 ADDR17 Hi-z/– O(L)/– O(L) t10s

F9 ADDR18/GPA3 ADDR18 Hi-z/– O(L)/– O(L) t10s H9 ADDR19/GPA4 ADDR19 Hi-z/– O(L)/– O(L) t10s

D10 ADDR20/GPA5 ADDR20 Hi-z/– O(L)/– O(L) t10s C10 ADDR21/GPA6 ADDR21 Hi-z/– O(L)/– O(L) t10s H10 ADDR22/GPA7 ADDR22 Hi-z/– O(L)/– O(L) t10s E10 ADDR23/GPA8 ADDR23 Hi-z/– O(L)/– O(L) t10s C11 ADDR24/GPA9 ADDR24 Hi-z/– O(L)/– O(L) t10s G10 ADDR25/GPA10 ADDR25 Hi-z/– O(L)/– O(L) t10s D11 ADDR26/GPA11 ADDR26 Hi-z/– O(L)/– O(L) t10s R14 AIN0 AIN0 – – AI r10 U17 AIN1 AIN1 – – AI r10 R15 AIN2 AIN2 – – AI r10 P15 AIN3 AIN3 – – AI r10 T16 YM/AIN4 AIN4 –/– –/– AI r10 T17 YP/AIN5 YP –/– –/– AI r10 R16 XM/AIN6 AIN6 –/– –/– AI r10

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

P16 XP/AIN7 XP –/– –/– AI r10

H6 CAMDATA0/GPJ0 GPJ0 –/– Hi-z/– I t8

G3 CAMDATA1/GPJ1 GPJ1 –/– Hi-z/– I t8

H5 CAMDATA2/GPJ2 GPJ2 –/– Hi-z/– I t8 H4 CAMDATA3/GPJ3 GPJ3 –/– Hi-z/– I t8 H3 CAMDATA4/GPJ4 GPJ4 –/– Hi-z/– I t8 H7 CAMDATA5/GPJ5 GPJ5 –/– Hi-z/– I t8

J8 CAMDATA6/GPJ6 GPJ6 –/– Hi-z/– I t8

H2 CAMDATA7/GPJ7 GPJ7 –/– Hi-z/– I t8 G5 CAMPCLK/GPJ8 GPJ8 –/– Hi-z/– I t8 G7 CAMVSYNC/GPJ9 GPJ9 –/– Hi-z/– I t8 G2 CAMHREF/GPJ10 GPJ10 –/– Hi-z/– I t8

J3 CAMCLKOUT/GPJ11 GPJ11 –/– O(L)/– I t8

J4 CAMRESET/GPJ12 GPJ12 –/– O(L)/– I t8 D12 DATA0 DATA0 Hi-z Hi-z,O(L) I b12s C12 DATA1 DATA1 Hi-z Hi-z,O(L) I b12s E11 DATA2 DATA2 Hi-z Hi-z,O(L) I b12s A13 DATA3 DATA3 Hi-z Hi-z,O(L) I b12s F10 DATA4 DATA4 Hi-z Hi-z,O(L) I b12s F11 DATA5 DATA5 Hi-z Hi-z,O(L) I b12s C13 DATA6 DATA6 Hi-z Hi-z,O(L) I b12s A14 DATA7 DATA7 Hi-z Hi-z,O(L) I b12s D13 DATA8 DATA8 Hi-z Hi-z,O(L) I b12s B15 DATA9 DATA9 Hi-z Hi-z,O(L) I b12s A17 DATA10 DATA10 Hi-z Hi-z,O(L) I b12s C14 DATA11 DATA11 Hi-z Hi-z,O(L) I b12s D15 DATA12 DATA12 Hi-z Hi-z,O(L) I b12s C15 DATA13 DATA13 Hi-z Hi-z,O(L) I b12s D14 DATA14 DATA14 Hi-z Hi-z,O(L) I b12s B17 DATA15 DATA15 Hi-z Hi-z,O(L) I b12s C16 DATA16 DATA16 Hi-z Hi-z,O(L) I b12s E15 DATA17 DATA17 Hi-z Hi-z,O(L) I b12s E14 DATA18 DATA18 Hi-z Hi-z,O(L) I b12s

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

E13 DATA19 DATA19 Hi-z Hi-z,O(L) I b12s E12 DATA20 DATA20 Hi-z Hi-z,O(L) I b12s E16 DATA21 DATA21 Hi-z Hi-z,O(L) I b12s

F15 DATA22 DATA22 Hi-z Hi-z,O(L) I b12s G13 DATA23 DATA23 Hi-z Hi-z,O(L) I b12s E17 DATA24 DATA24 Hi-z Hi-z,O(L) I b12s G12 DATA25 DATA25 Hi-z Hi-z,O(L) I b12s

F14 DATA26 DATA26 Hi-z Hi-z,O(L) I b12s

F12 DATA27 DATA27 Hi-z Hi-z,O(L) I b12s G11 DATA28 DATA28 Hi-z Hi-z,O(L) I b12s G16 DATA29 DATA29 Hi-z Hi-z,O(L) I b12s H13 DATA30 DATA30 Hi-z Hi-z,O(L) I b12s

F13 DATA31 DATA31 Hi-z Hi-z,O(L) I b12s P12 DN0 DN0 – – AI us N11 DP0 DP0 – – AI us N12 DN1/PDN0 DN1 –/– – AI us U14 DP1/PDP0 DP1 –/– – AI us N17 EINT0/GPF0 GPF0 –/– Hi-z/– I t8 M16 EINT1/GPF1 GPF1 –/– Hi-z/– I t8

L13 EINT2/GPF2 GPF2 –/– Hi-z/– I t8 M15 EINT3/GPF3 GPF3 –/– Hi-z/– I t8 M17 EINT4/GPF4 GPF4 –/– Hi-z/– I t8

L14 EINT5/GPF5 GPF5 –/– Hi-z/– I t8

L15 EINT6/GPF6 GPF6 –/– Hi-z/– I t8

L16 EINT7/GPF7 GPF7 –/– Hi-z/– I t8

N9 EINT8/GPG0 GPG0 –/– Hi-z/– I t8 T9 EINT9/GPG1 GPG1 –/– Hi-z/– I t8

J10 EINT10/nSS0/GPG2 GPG2 –/–/– Hi-z/Hi-z/– I t8 R10 EINT11/nSS1/GPG3 GPG3 –/–/– Hi-z/Hi-z/– I t8 P11 EINT12/LCD_PWREN/GPG4 GPG4 –/–/– Hi-z/O(L)/– I t8 K10 EINT13/SPIMISO1/GPG5 GPG5 –/–/– Hi-z/Hi-z/– I t8 R11 EINT14/SPIMOSI1/GPG6 GPG6 –/–/– Hi-z/Hi-z/– I t8

L10 EINT15/SPICLK1/GPG7 GPG7 –/–/– Hi-z/Hi-z/– I t8

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

T10 EINT16/GPG8 GPG8 –/– Hi-z/– I t8 M11 EINT17/nRTS1/GPG9 GPG9 –/–/– Hi-z/O(H)/– I t8 N10 EINT18/nCTS1/GPG10 GPG10 –/–/– Hi-z/Hi-z/– I t8 U12 EINT19/TCLK1/GPG11 GPG11 –/–/– Hi-z/Hi-z/– I t12 M10 EINT20/GPG12 GPG12 –/– Hi-z/– I t12

T11 EINT21/GPG13 GPG13 –/– Hi-z/– I t12

L11 EINT22/GPG14 GPG14 –/– Hi-z/– I t12 U13 EINT23/GPG15 GPG15 –/– Hi-z/– I t12 H12 EXTCLK EXTCLK – – AI is

P17 UPLLCAP UPLLCAP – – AI r50 N14 MPLLCAP MPLLCAP – – AI r50 H14 nBATT_FLT nBATT_FLT – – I is

D4 nBE0 nBE0 Hi-z Hi-z,O(H) O(H) t10s B5 nBE1 nBE1 Hi-z Hi-z,O(H) O(H) t10s D5 nBE2 nBE2 Hi-z Hi-z,O(H) O(H) t10s E5 nBE3 nBE3 Hi-z Hi-z,O(H) O(H) t10s

R12 NCON NCON – – I is

G6 FRnB FRnB – Hi-z,O(L) I d2s

F3 nFWE/GPA19 GPA19 O(H)/– Hi-z,O(H)/– O(H) t10s

E1 nFRE/GPA20 GPA20 O(H)/– Hi-z,O(H)/– O(H) t10s

F4 nFCE/GPA22 GPA21 O(H)/– Hi-z,O(H)/– O(H) t10s F5 CLE/GPA17 GPA17 O(L)/– Hi-z,O(L)/– O(L) t10s

D1 ALE/GPA18 GPA18 O(L)/– Hi-z,O(L)/– O(L) t10s

N13 nRSTOUT/GPA21 GPA21 –/– O(L)/– O(L) b8

C5 nOE nOE Hi-z Hi-z,O(H) O(H) t10s

H16 nRESET nRESET – – I is

F6 nGCS0 nGCS0 Hi-z Hi-z,O(H) O(H) t10s B2 nGCS1/GPA12 GPA12 Hi-z/– Hi-z,O(H)/– O(H) t10s C3 nGCS2/GPA13 GPA13 Hi-z/– Hi-z,O(H)/– O(H) t10s C4 nGCS3/GPA14 GPA14 Hi-z/– Hi-z,O(H)/– O(H) t10s D3 nGCS4/GPA15 GPA15 Hi-z/– Hi-z,O(H)/– O(H) t10s C2 nGCS5/GPA16 GPA16 Hi-z/– Hi-z,O(H)/– O(H) t10s D2 nGCS6 nGCS6 Hi-z Hi-z,O(H) O(H) t10s

1-13

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

E3 nGCS7 nGCS7 Hi-z Hi-z,O(H) O(H) t10s D6 nSCAS nSCAS Hi-z Hi-z,O(H) O(H) t10s C6 nSRAS nSRAS Hi-z Hi-z,O(H) O(H) t10s

H15 nTRST nTRST I – I is

E4 nWAIT nWAIT – Hi-z,O(L) I d2s E6 nWE nWE Hi-z Hi-z,O(H) O(H) t10s

J6 TOUT0/GPB0 GPB0 –/– O(L)/– I t8 J5 TOUT1/GPB1 GPB1 –/– O(L)/– I t8

J7 TOUT2/GPB2 GPB2 –/– O(L)/– I t8 K3 TOUT3/GPB3 GPB3 –/– O(L)/– I t8 K4 TCLK0/GPB4 GPB4 –/– –/– I t8 K2 nXBACK/GPB5 GPB5 –/– O(H)/– I t8

L5 nXBREQ/GPB6 GPB6 –/– –/– I t8 K7 nXDACK1/GPB7 GPB7 –/– O(H)/– I t8 K5 nXDREQ1/GPB8 GPB8 –/– –/– I t8

L3 nXDACK0/GPB9 GPB9 –/– O(H)/– I t8 K6 nXDREQ0/GPB10 GPB10 –/– –/– I t8

T15 OM0 OM0 – – I is R13 OM1 OM1 – – I is P13 OM2 OM2 – – I is T13 OM3 OM3 – – I is

J12 PWREN PWREN O(H) O(L) O(H) b8

K11 nCTS0/GPH0 GPH0 –/– –/– I t8

L17 nRTS0/GPH1 GPH1 –/– O(H)/– I t8 K13 TXD0/GPH2 GPH2 –/– O(H)/– I t8 K14 RXD0/GPH3 GPH3 –/– –/– I t8 K16 TXD1/GPH4 GPH4 –/– O(H)/– I t8 K17 RXD1/GPH5 GPH5 –/– –/– I t8

J11 TXD2/nRTS1/GPH6 GPH6 –/–/– O(H)/O(H)/– I t8

J15 RXD2/nCTS1/GPH7 GPH7 –/–/– Hi-z/Hi-z/– I t8 K15 UEXTCLK/GPH8 GPH8 –/– Hi-z/– I t8

R9 CLKOUT0/GPH9 GPH9 –/– O(L)/– I t12

P10 CLKOUT1/GPH10 GPH10 –/– O(L)/– I t12

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

A2 SCKE SCKE Hi-z O(L) O(H) t10s B4 SCLK0 SCLK0 Hi-z O(L) O(SCLK) t12s B3 SCLK1 SCLK1 Hi-z O(L) O(SCLK) t12s P7 I2SLRCK/AC_SYNC GPE0 –/– Hi-z/– I t8 R7 I2SSCLK/AC_BIT_CLK GPE1 –/– Hi-z/– I t8 T7 CDCLK/AC_nRESET GPE2 –/– Hi-z/– I t8

L8 I2SSDI/AC_SDATA_IN GPE3 –/–/– Hi-z/Hi-z/– I t8 U6 I2SSDO/AC_SDATA_OUT GPE4 –/–/– O(L)/Hi-z/– I t8 N8 SDCLK/GPE5 GPE5 –/– O(L)/– I t8 K8 SDCMD/GPE6 GPE6 –/– Hi-z/– I t8 R8 SDDAT0/GPE7 GPE7 –/– Hi-z/– I t8

M8 SDDAT1/GPE8 GPE8 –/– Hi-z/– I t8

P8 SDDAT2/GPE9 GPE9 –/– Hi-z/– I t8

J9 SDDAT3/GPE10 GPE10 –/– Hi-z/– I t8 K9 SPIMISO0/GPE11 GPE11 –/– Hi-z/– I t8 P9 SPIMOSI0/GPE12 GPE12 –/– Hi-z/– I t8

L9 SPICLK0/GPE13 GPE13 –/– Hi-z/– I t8 U8 IICSCL/GPE14 GPE14 –/– Hi-z/– I d8

M9 IICSDA/GPE15 GPE15 –/– Hi-z/– I d8

J13 TCK TCK I – I is

H17 TDI TDI I – I is

J16 TDO TDO O O O ot J14 TMS TMS I – I is

L1 LEND/GPC0 GPC0 –/– O(L)/– I t8

L4 VCLK/GPC1 GPC1 –/– O(L)/– I t8

M1 VLINE/GPC2 GPC2 –/– O(L)/– I t8

L7 VFRAME/GPC3 GPC3 –/– O(L)/– I t8

M4 VM/GPC4 GPC4 –/– O(L)/– I t8 M3 LCD_LPCOE/GPC5 GPC5 –/– O(L)/– I t8 M2 LCD_LPCREV/GPC6 GPC6 –/– O(L)/– I t8

P1 LCD_LPCREVB/GPC7 GPC7 –/– O(L)/– I t8 N2 VD0/GPC8 GPC8 –/– O(L)/– I t8

L6 VD1/GPC9 GPC9 –/– O(L)/– I t8

1-15

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

N4 VD2/GPC10 GPC10 –/– O(L)/– I t8 R1 VD3/GPC11 GPC11 –/– O(L)/– I t8 N3 VD4/GPC12 GPC12 –/– O(L)/– I t8

P2 VD5/GPC13 GPC13 –/– O(L)/– I t8

M6 VD6/GPC14 GPC14 –/– O(L)/– I t8

P3 VD7/GPC15 GPC15 –/– O(L)/– I t8 R2 VD8/GPD0 GPD0 –/– O(L)/– I t8 M5 VD9/GPD1 GPD1 –/– O(L)/– I t8 N5 VD10/GPD2 GPD2 –/– O(L)/– I t8 R3 VD11/GPD3 GPD3 –/– O(L)/– I t8

P4 VD12/GPD4 GPD4 –/– O(L)/– I t8 R4 VD13/ GPD5 GPD5 –/–/– O(L)/O/– I t8

P5 VD14/GPD6 GPD6 –/–/– O(L)/O/– I t8 N6 VD15/GPD7 GPD7 –/–/– O(L)/O/– I t8 M7 VD16/SPIMISO1/GPD8 GPD8 –/–/– O(L)/Hi-z/– I t8

T4 VD17/SPIMOSI1/GPD9 GPD9 –/–/– O(L)/Hi-z/– I t8 R5 VD18/SPICLK1/GPD10 GPD10 –/–/– O(L)/Hi-z/– I t8

T5 VD19//GPD11 GPD11 –/–/– O(L)/Hi-z/– I t8

P6 VD20/ GPD12 GPD12 –/–/– O(L)/Hi-z/– I t8 R6 VD21/ GPD13 GPD13 –/–/– O(L)/Hi-z/– I t8 N7 VD22/nSS1/GPD14 GPD14 –/–/– O(L)/Hi-z/– I t8 U5 VD23/nSS0/GPD15 GPD15 –/–/– O(L)/Hi-z/– I t8

U16 Vref Vref – – AI ia G14 XTIpll XTIpll – – AI m26 M14 Xtirtc Xtirtc – – AI nc G15 XTOpll XTOpll – – AO m26

L12 Xtortc Xtortc – – AO nc

N15 VDD_RTC VDD_RTC P P P drtc

P14 VDDA_ADC VDDA_ADC P P P d33th N16 VDDA_MPLL VDDA_MPLL P P P d12t M13 VDDA_UPLL VDDA_UPLL P P P d12t

G4 VDDalive VDDalive P P P d12i

J17 VDDalive VDDalive P P P d12i

1-16

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

A1 VDDi VDDi P P P d12c A10 VDDi VDDi P P P d12c A16 VDDi VDDi P P P d12c

A6 VDDi VDDi P P P d12c B11 VDDi VDDi P P P d12c

F1 VDDi VDDi P P P d12c F16 VDDi VDDi P P P d12c

U11 VDDi VDDi P P P d12c

L2 VDDiarm VDDiarm P P P d12c T6 VDDiarm VDDiarm P P P d12c T8 VDDiarm VDDiarm P P P d12c

U1 VDDiarm VDDiarm P P P d12c

J2 VDDiarm VDDiarm P P P d12c

U2 VDDiarm VDDiarm P P P d12c

A9 VDDMOP VDDMOP P P P d33o

B12 VDDMOP VDDMOP P P P d33o B14 VDDMOP VDDMOP P P P d33o B16 VDDMOP VDDMOP P P P d33o

B6 VDDMOP VDDMOP P P P d33o

C1 VDDMOP VDDMOP P P P d33o

F17 VDDMOP VDDMOP P P P d33o

J1 VDDOP VDDOP P P P d33o

T12 VDDOP VDDOP P P P d33o

T3 VDDOP VDDOP P P P d33o

K12 VDDOP VDDOP P P P d33o T14 VSSA_ADC VSSA_ADC P P P sth R17 VSSA_MPLL VSSA_MPLL P P P st M12 VSSA_UPLL VSSA_UPLL P P P st A12 VSSi VSSi P P P si

A3 VSSi VSSi P P P si A4 VSSi VSSi P P P si

B10 VSSi VSSi P P P si C17 VSSi VSSi P P P si

1-17

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9 of 9)

Number

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

I/O Type

F2 VSSi VSSi P P P si

G17 VSSi VSSi P P P si

H1 VSSiarm VSSiarm P P P si K1 VSSiarm VSSiarm P P P si T1 VSSiarm VSSiarm P P P si T2 VSSiarm VSSiarm P P P si

U10 VSSiarm VSSiarm P P P si

U4 VSSiarm VSSiarm P P P si

U7 VSSiarm VSSiarm P P P si A11 VSSMOP VSSMOP P P P so A15 VSSMOP VSSMOP P P P so

A5 VSSMOP VSSMOP P P P so

A7 VSSMOP VSSMOP P P P so

B1 VSSMOP VSSMOP P P P so B13 VSSMOP VSSMOP P P P so D16 VSSMOP VSSMOP P P P so D17 VSSMOP VSSMOP P P P so

E2 VSSMOP VSSMOP P P P so

G1 VSSOP VSSOP P P P so

N1 VSSOP VSSOP P P P so U15 VSSOP VSSOP P P P so

U3 VSSOP VSSOP P P P so

U9 VSSOP VSSOP P P P so H11 VSSOP VSSOP P P P so

1-18

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

NOTE:

1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.

2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.

3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.

4. AI/AO means analog input/analog output.

5. P, I, and O mean power, input and output respectively.

6. The I/O state @nRESET shows the pin status in the @nRESET duration below.

@nRESET4 OSCin

nRESET

FCLK

1-19

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS.

Input (I)/Output (O) Type Descriptions

d12i(vdd12ih) 1.2V Vdd for alive power d12c(vdd12ih_core), si(vssih) 1.2V Vdd/Vss for internal logic d33o(vdd33oph), so(vssoph) 3.3V Vdd/Vss for external logic

d33th(vdd33th_abb) ,sth(vssbbh_abb)

3.3V Vdd/Vss for analog circuitry

d12t(vdd12t_abb), st(vssbb_abb) 1.2V Vdd/Vss for analog circuitry drtc(vdd30th_rtc) 3.0V Vdd for RTC power

t8(phbsu100ct8sm)

Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=8mA

is(phis) Input pad, LVCMOS schmitt-trigger level us(pbusb0) USB pad t10(phtot10cd) 5V tolerant Output pad, Tri-state . ot(phot8) Output pad, tri-state, Io=8mA b8(phob8) Output pad, Io=8mA t16(phot16sm) Output pad, tri-state, medium slew rate, Io=16mA r10(phiar10_abb) Analog input pad with 10-ohm resistor ia(phia_abb) Analog input pad gp(phgpad_option) Pad for analog pin m26(phsoscm26_2440a) Oscillator cell with enable and feedback resistor

t12(phbsu100ct12sm)

Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=12mA

d8(phbsd8sm) Bi-directional pad, LVCMOS schmitt-trigger, Open Drain, Io=8mA

t10s(phtot10cd_10_2440a)

b12s(phtbsu100ct12cd_12_2440a)

d2s(phtbsd2_2440a)

output pad, LVCMOS , tri -state, output drive strenth control, Io=4,6,8,10mA

Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri -state,output drive strenth control, Io=6,8,10,12mA

Bi-directional pad, LVCMOS schmitt-trigger, open-drain, output drive strenth ignore,

r50(phoar50_abb) Analog Output pad, 50Kohm resistor, Separated bulk-bias t12s(phtot12cd_12_2440a)

output pad, LVCMOS , tri -state, output drive strenth control, Io=6,8,10,12mA

nc(phnc) No connection pad

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

SIGNAL DESCRIPTIONS

Table 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6)

Signal Input/Output Descriptions

Bus Controller

OM[1:0] I OM[1:0] sets S3C2440A in the TEST mode, which is used only at fabrication.

Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during RESET cycle.

00:Nand-boot 01:16-bit 10:32-bit 11:Test mode

ADDR[26:0] O ADDR[26:0] (Address Bus) outputs the memory address of the corresponding

bank .

DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write. The bus width is programmable among 8/16/32-bit.

nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is

within the address region of each bank. The number of access cycles and the

bank size can be programmed. nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle. nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle. nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the

local bus. BACK active indicates that bus control has been granted. nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2440A has surrendered

control of the local bus to another bus master. nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the

current bus cycle cannot be completed.

SDRAM/SRAM

nSRAS O SDRAM Row Address Strobe nSCAS O SDRAM Column Address Strobe nSCS[1:0] O SDRAM Chip Select DQM[3:0] O SDRAM Data Mask SCLK[1:0] O SDRAM Clock SCKE O SDRAM Clock Enable nBE[3:0] O Upper Byte/Lower Byte Enable(In case of 16-bit SRAM) nWBE[3:0] O Write Byte Enable

NAND Flash

CLE O Command Latch Enable ALE O Address Latch Enable nFCE O Nand Flash Chip Enable nFRE O Nand Flash Read Enable nFWE O Nand Flash Write Enable NCON I Nand Flash Configuration FRnB I Nand Flash Ready/Busy

* If NAND flash controller isn’t used, it has to be pull-up. (3.3V)

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-3. S3C2440A Signal Descriptions (Sheet 2 of 6)

Signal Input/Output Descriptions

LCD Control Unit

VD[23:0] O LCD_PWREN O VCLK O VFRAME O VLINE O VM O VSYNC O HSYNC O VDEN O LEND O STV O CPV O LCD_HCLK O TP O STH O LCD_LPCOE O LCD_LPCREV O LCD_LPCREVB O

STN/TFT/SEC TFT: LCD Data Bus STN/TFT/SEC TFT: LCD panel power enable control signal STN/TFT: LCD clock signal STN: LCD Frame signal STN: LCD line signal STN: VM alternates the polarity of the row and column voltage TFT: Vertical synchronous signal TFT: Horizontal synchronous signal TFT: Data enable signal TFT: Line End signal SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TF T: Timing control signal for specific TFT LCD SEC TF T: Timing control signal for specific TFT LCD SEC TF T: Timing control signal for specific TFT LCD

CAMERA Interface

CAMRESET O Software Reset to the Camera CAMCLKOUT O Master Clock to the Camera CAMPCLK I Pixel clock from Camera CAMHREF I Horizontal sync signal from Camera CAMVSYNC I Vertical sync signal from Camera CAMDATA[7:0] I Pixel data for YCbCr

Interrupt Control Unit

EINT[23:0] I External Interrupt request

DMA

nXDREQ[1:0] I External DMA request nXDACK[1:0] O External DMA acknowledge

1-22

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6)

Signal Input/Output Descriptions

UART

RxD[2:0] I UART receives data input TxD[2:0] O UART transmits data output nCTS[1:0] I UART clear to send input signal nRTS[1:0] O UART request to send output signal UEXTCLK I External clock input for UART

ADC

AIN[7:0] AI ADC input[7:0]. If it isn’t used pin, it has to be Low (Ground). Vref AI ADC Vref IIC-Bus IICSDA IO IIC-bus data IICSCL IO IIC-bus clock IIS-Bus I2SLRCK IO IIS-bus channel select clock I2SSDO O IIS-bus serial data output I2SSDI I IIS-bus serial data input I2SSCLK IO IIS-bus serial clock CDCLK O CODEC system clock AC’97 AC_SYNC AC_BIT_CLK AC_nRESET AC_SDATA_IN AC_SDATA_OUT

O 48 kHz fixed rate sample sync

IO 12.288 MHz serial data clock

O AC’97 Master H/W Reset

I Serial, time division multiplexed, AC’97 input stream

O Serial, time division multiplexed, AC’97 output stream Touch Screen nXPON O Plus X-axis on-off control signal XMON O Minus X-axis on-off control signal nYPON O Plus Y-axis on-off control signal YMON O Minus Y-axis on-off control signal

USB Host

DN[1:0] IO DATA(–) from USB host. (Need to 15K ohm pull-down) DP[1:0] IO DATA(+) from USB host. (Need to 15K ohm pull-down)

USB Device

PDN0 IO DATA(–) for USB peripheral.

(Need to 470K ohm pull-down for power consumption in sleep mode)

PDP0 IO DATA(+) for USB peripheral. (Need to 1.5K ohm pull-up)

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6)

Signal Input/Output Description

SPI

SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role.

SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role. SPICLK[1:0] IO SPI clock nSS[1:0] I SPI chip select(only for slave mode)

SDDAT[3:0] IO SD receive/transmit data SDCMD IO SD receive response/ transmit command SDCLK O SD clock General Port GPn[129:0] IO General input/output ports (some ports are output only) TIMMER/PWM TOUT[3:0] O Timer output[3:0] TCLK[1:0] I External timer clock input JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start.

If debugger is used, A 10K pull-up resistor has to be connected.

If debugger(black ICE) is not used, nTRST pin must be issued by a low active

pulse(Typically connected to nRESET). TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP

controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.

A 10K pull-up resistor must be connected to TCK pin. TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.

A 10K pull-up resistor must be connected to TDI pin. TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and

data.

1-24

Page 26

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6)

Signal Input/Output Description

Reset, Clock & Power

XTOpll AO Crystal Output for internal osc circuit.

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.

If it isn't used, it has to be a floating pin. MPLLCAP AI Loop filter capacitor for main clock. UPLLCAP AI Loop filter capacitor for USB clock. XTIrtc AI 32 kHz crystal input for RTC. If it isn’t used, it has to be High (3.3V). XTOrtc AO 32 kHz crystal output for RTC. If it isn’t used, it has to be Float. CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock

output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK. nRESET ST nRESET suspends any operation in progress and places S3C2440A into a

known reset state. For a reset, nRESET must be held to L level for at least 4

OSCin after the processor power has been stabilized. nRSTOUT O For external device reset control(nRSTOUT = nRESET & nWDTRST &

SW_RESET) PWREN O 1.2V/1.3V core power on-off control signal nBATT_FLT I Probe for battery state(Does not wake up at Sleep mode in case of low battery

state). If it isn’t used, it has to be High (3.3V). OM[3:2] I OM[3:2] determines how the clock is made.

OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.

OM[3:2] = 01b, Crystal is used for MPLL CLK source

and EXTCLK is used for UPLL CLK source.

OM[3:2] = 10b, EXTCLK is used for MPLL CLK source

and Crystal is used for UPLL CLK source.

OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. EXTCLK I External clock source.

When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK

source.

When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only.

When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only.

If it isn't used, it has to be High (3.3V). XTIpll AI Crystal Input for internal osc circuit.

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK

source.

When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.

When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.

If it isn't used, XTIpll has to be High (3.3V).

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Page 27

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6)

Signal Input/Output Description

Power

VDDalive P S3C2440A reset block and port status register VDD.

It should be always supplied whether in normal mode or in Sleep mode. VDDiarm P S3C2440A core logic VDD for ARM core. VDDi P S3C2440A core logic VDD for Internal block. VSSi/VSSiarm P S3C2440A core logic VSS VDDi_MPLL P S3C2440A MPLL analog and digital VDD. VSSi_MPLL P S3C2440A MPLL analog and digital VSS. VDDOP P S3C2440A I/O port VDD(3.3V) VDDMOP P S3C2440A Memory I/O VDD

3.3V : SCLK up to 135MHz

2.5V : SCLK up to 135MHz

1.8V : SCLK up to 93MHz VSSOP P S3C2440A I/O port VSS RTCVDD P RTC VDD (3.0V, Input range: 1.8 ~ 3.6V)

This pin must be connected to power properly if RTC isn't used. VDDi_UPLL P S3C2440A UPLL analog and digital VDD VSSi_UPLL P S3C2440A UPLL analog and digital VSS VDDA_ADC P S3C2440A ADC VDD(3.3V) VSSA_ADC P S3C2440A ADC VSS

NOTE:

1. I/O means Input/Output.

2. AI/AO means analog input/analog output.

3. ST means schmitt-trigger.

4. P means power.

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Page 28

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

S3C2440A SPECIAL REGISTERS

Table 1-4. S3C2440A Special Registers (Sheet 1 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Memory Controller

BWSCON 0x48000000

←

W R/W Bus Width & Wait Status Control BANKCON0 0x48000004 Boot ROM Control BANKCON1 0x48000008 BANK1 Control BANKCON2 0x4800000C BANK2 Control BANKCON3 0x48000010 BANK3 Control BANKCON4 0x48000014 BANK4 Control BANKCON5 0x48000018 BANK5 Control BANKCON6 0x4800001C BANK6 Control BANKCON7 0x48000020 BANK7 Control REFRESH 0x48000024 DRAM/SDRAM Refresh Control BANKSIZE 0x48000028 Flexible Bank Size MRSRB6 0x4800002C Mode register set for SDRAM BANK6 MRSRB7 0x48000030 Mode register set for SDRAM BANK7

1-27

Page 29

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 2 of 14)

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

USB Host Controller

HcRevision 0x49000000 HcControl 0x49000004 HcCommonStatus 0x49000008

←

W Control and Status Group

HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 Memory Pointer Group HcPeriodCuttentED 0x4900001C HcControlHeadED 0x49000020 HcControlCurrentED 0x49000024 HcBulkHeadED 0x49000028 HcBulkCurrentED 0x4900002C HcDoneHead 0x49000030 HcRmInterval 0x49000034 Frame Counter Group HcFmRemaining 0x49000038 HcFmNumber 0x4900003C HcPeriodicStart 0x49000040 HcLSThreshold 0x49000044 HcRhDescriptorA 0x49000048 Root Hub Group HcRhDescriptorB 0x4900004C HcRhStatus 0x49000050 HcRhPortStatus1 0x49000054 HcRhPortStatus2 0x49000058 Interrupt Controller SRCPND 0X4A000000 ← W R/W Interrupt Request Status INTMOD 0X4A000004 W Interrupt Mode Control INTMSK 0X4A000008 R/W Interrupt Mask Control PRIORITY 0X4A00000C W IRQ Priority Control INTPND 0X4A000010 R/W Interrupt Request Status INTOFFSET 0X4A000014 R Interrupt request source offset SUBSRCPND 0X4A000018 R/W Sub source pending INTSUBMSK 0X4A00001C R/W Interrupt sub mask

1-28

Page 30

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 3 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

DMA

DISRC0 0x4B000000 DISRCC0 0x4B000004 DIDST0 0x4B000008 DIDSTC0 0x4B00000C DCON0 0x4B000010 DSTAT0 0x4B000014 DCSRC0 0x4B000018 DCDST0 0x4B00001C DMASKTRIG0 0x4B000020 DISRC1 0x4B000040 DISRCC1 0x4B000044 DIDST1 0x4B000048 DIDSTC1 0x4B00004C DCON1 0x4B000050 DSTAT1 0x4B000054 DCSRC1 0x4B000058 DCDST1 0x4B00005C DMASKTRIG1 0x4B000060 DISRC2 0x4B000080 DISRCC2 0x4B000084 DIDST2 0x4B000088 DIDSTC2 0x4B00008C DCON2 0x4B000090 DSTAT2 0x4B000094 DCSRC2 0x4B000098 DCDST2 0x4B00009C DMASKTRIG2 0x4B0000A0 DISRC3 0x4B0000C0 DISRCC3 0x4B0000C4 DIDST3 0x4B0000C8 DIDSTC3 0x4B0000CC DCON3 0x4B0000D0 DSTAT3 0x4B0000D4 DCSRC3 0x4B0000D8 DCDST3 0x4B0000DC DMASKTRIG3 0x4B0000E0

←

Acc.

Unit

Read/

Write

Function

W R/W DMA 0 Initial Source

DMA 0 Initial Source Control DMA 0 Initial Destination DMA 0 Initial Destination Control DMA 0 Control R DMA 0 Count DMA 0 Current Source DMA 0 Current Destination R/W DMA 0 Mask Trigger DMA 1 Initial Source DMA 1 Initial Source Control DMA 1 Initial Destination DMA 1 Initial Destination Control DMA 1 Control R DMA 1 Count DMA 1 Current Source DMA 1 Current Destination R/W DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Source Control DMA 2 Initial Destination DMA 2 Initial Destination Control DMA 2 Control R DMA 2 Count DMA 2 Current Source DMA 2 Current Destination R/W DMA 2 Mask Trigger

W R/W DMA 3 Initial Source

DMA 3 Initial Source Control DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 Control R DMA 3 Count DMA 3 Current Source DMA 3 Current Destination R/W DMA 3 Mask Trigger

1-29

Page 31

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 4 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit

Read/

Write

Function

Clock & Power Management

LOCKTIME 0x4C000000

←

W R/W PLL Lock Time Counter MPLLCON 0x4C000004 MPLL Control UPLLCON 0x4C000008 UPLL Control CLKCON 0x4C00000C Clock Generator Control CLKSLOW 0x4C000010 Slow Clock Control CLKDIVN 0x4C000014 Clock divider Control CAMDIVN 0x4C000018 Camera Clock divider Control LCD Controller LCDCON1 0X4D000000

←

W R/W LCD Control 1 LCDCON2 0X4D000004 LCD Control 2 LCDCON3 0X4D000008 LCD Control 3 LCDCON4 0X4D00000C LCD Control 4 LCDCON5 0X4D000010 LCD Control 5 LCDSADDR1 0X4D000014 STN/TFT: Frame Buffer Start

Address1

LCDSADDR2 0X4D000018 STN/TFT: Frame Buffer Start

Address2 LCDSADDR3 0X4D00001C STN/TFT: Virtual Screen Address Set REDLUT 0X4D000020 STN: Red Lookup Table GREENLUT 0X4D000024 STN: Green Lookup Table BLUELUT 0X4D000028 STN: Blue Lookup Table DITHMODE 0X4D00004C STN: Dithering Mode TPAL 0X4D000050 TFT: Temporary Palette LCDINTPND 0X4D000054 LCD Interrupt Pending LCDSRCPND 0X4D000058 LCD Interrupt Source LCDINTMSK 0X4D00005C LCD Interrupt Mask TCONSEL 0X4D000060 TCON(LPC3600/LCC3600) Control

1-30

Page 32

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 5 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

NAND Flash

NFCONF 0x4E000000 NFCONT 0x4E000004 NFCMD 0x4E000008 NFADDR 0x4E00000C NFDATA 0x4E000010 NFMECC0 0x4E000014 NFMECC1 0x4E000018 NFSECC 0x4E00001C NFSTAT 0x4E000020 NFESTAT0 0x4E000024 NFESTAT1 0x4E000028 NFMECC0 0x4E00002C NFMECC1 0x4E000030 NFSECC 0x4E000034 NFSBLK 0x4E000038 NFEBLK 0x4E00003C

←

Acc.

Unit

Read/

Write

Function

W R/W NAND Flash Configuration

NAND Flash Control NAND Flash Command NAND Flash Address NAND Flash Data NAND Flash Main area ECC0/1 NAND Flash Main area ECC2/3 NAND Flash Spare area ECC NAND Flash Operation Status NAND Flash ECC Status for I/O[7:0] NAND Flash ECC Status for I/O[15:8] R NAND Flash Main area ECC0 status NAND Flash Main Area ECC1 status NAND Flash Spare Area ECC status R/W NAND Flash start block address NAND Flash end block address

1-31

Page 33

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 6 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Camera Interface

CISRCFMT 0x4F000000 CIWDOFST 0x4F000004 CIGCTRL 0x4F000008 CICOYSA1 0x4F000018 CICOYSA2 0x4F00001C CICOYSA3 0x4F000020 CICOYSA4 0x4F000024 CICOCBSA1 0x4F000028 CICOCBSA2 0x4F00002C CICOCBSA3 0x4F000030 CICOCBSA4 0x4F000034 CICOCRSA1 0x4F000038 CICOCRSA2 0x4F00003C CICOCRSA3 0x4F000040 CICOCRSA4 0x4F000044 CICOTRGFMT 0x4F000048 CICOCTRL 0x4F00004C CICOSCPRERATIO 0x4F000050 CICOSCPREDST 0x4F000054 CICOSCCTRL 0x4F000058 CICOTAREA 0x4F00005C CICOSTATUS 0x4F000064 CIPRCLRSA1 0x4F00006C CIPRCLRSA2 0x4F000070 CIPRCLRSA3 0x4F000074 CIPRCLRSA4 0x4F000078 CIPRTRGFMT 0x4F00007C CIPRCTRL 0x4F000080 CIPRSCPRERATIO 0x4F000084 CIPRSCPREDST 0x4F000088 CIPRSCCTRL 0x4F00008C CIPRTAREA 0x4F000090 CIPRSTATUS 0x4F000098 CIIMGCPT 0x4F0000A0

←

Acc.

Unit

Read/

Write

Function

W RW Input Source Format

Window offset register Global control register Y 1st frame start address for codec DMA Y 2nd frame start address for codec DMA Y 3rd frame start address for codec DMA Y 4th frame start address for codec DMA Cb 1st frame start address for codec DMA Cb 2nd frame start address for codec DMA Cb 3rd frame start address for codec DMA Cb 4th frame start address for codec DMA Cr 1st frame start address for codec DMA Cr 2nd frame start address for codec DMA Cr 3rd frame start address for codec DMA Cr 4th frame start address for codec DMA Target image format of codec DMA Codec DMA control related Codec pre-scaler ratio control Codec pre-scaler destination format Codec main-scaler control Codec scaler target area Codec path status RGB 1st frame start address for preview DMA RGB 2nd frame start address for preview DMA RGB 3rd frame start address for preview DMA RGB 4th frame start address for preview DMA Target image format of preview DMA Preview DMA control related Preview pre-scaler ratio control Preview pre-scaler destination format Preview main-scaler control Preview scaler target area Preview path status Image capture enable command

1-32

Page 34

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 7 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit

Read/

Write

Function

UART

ULCON0 0x50000000

←

UCON0 0x50000004 UFCON0 0x50000008 UMCON0 0x5000000C UTRSTAT0 0x50000010 UERSTAT0 0x50000014 UFSTAT0 0x50000018

W R/W UART 0 Line Control

UART 0 Control UART 0 FIFO Control UART 0 Modem Control R UART 0 Tx/Rx Status UART 0 Rx Error Status

UART 0 FIFO Status UMSTAT0 0x5000001C UART 0 Modem Status UTXH0 0x50000023 0x50000020 B W UART 0 Transmission Hold URXH0 0x50000027 0x50000024 R UART 0 Receive Buffer UBRDIV0 0x50000028

←

ULCON1 0x50004000 UCON1 0x50004004 UFCON1 0x50004008 UMCON1 0x5000400C UTRSTAT1 0x50004010 UERSTAT1 0x50004014 UFSTAT1 0x50004018

W R/W UART 0 Baud Rate Divisor

UART 1 Line Control

UART 1 Control

UART 1 FIFO Control

UART 1 Modem Control

R UART 1 Tx/Rx Status

UART 1 Rx Error Status

UART 1 FIFO Status UMSTAT1 0x5000401C UART 1 Modem Status UTXH1 0x50004023 0x50004020 B W UART 1 Transmission Hold URXH1 0x50004027 0x50004024 R UART 1 Receive Buffer UBRDIV1 0x50004028

←

ULCON2 0x50008000 UCON2 0x50008004 UFCON2 0x50008008 UTRSTAT2 0x50008010 UERSTAT2 0x50008014 UFSTAT2 0x50008018

W R/W UART 1 Baud Rate Divisor

UART 2 Line Control

UART 2 Control

UART 2 FIFO Control

R UART 2 Tx/Rx Status

UART 2 Rx Error Status

UART 2 FIFO Status UTXH2 0x50008023 0x50008020 B W UART 2 Transmission Hold URXH2 0x50008027 0x50008024 R UART 2 Receive Buffer UBRDIV2 0x50008028

←

W R/W UART 2 Baud Rate Divisor

1-33

Page 35

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 8 of 14)

Name

Address

(B. Endian)

PWM Timer

TCFG0 0x51000000 TCFG1 0x51000004 TCON 0x51000008 TCNTB0 0x5100000C TCMPB0 0x51000010 TCNTO0 0x51000014 TCNTB1 0x51000018 TCMPB1 0x5100001C TCNTO1 0x51000020 TCNTB2 0x51000024 TCMPB2 0x51000028 TCNTO2 0x5100002C TCNTB3 0x51000030 TCMPB3 0x51000034 TCNTO3 0x51000038 TCNTB4 0x5100003C TCNTO4 0x51000040

Address

(L. Endian)

←

Acc. Unit

Read/

Write

Function

W R/W Timer Configuration

Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 R Timer Count Observation 0 R/W Timer Count Buffer 1 Timer Compare Buffer 1 R Timer Count Observation 1 R/W Timer Count Buffer 2 Timer Compare Buffer 2 R Timer Count Observation 2 R/W Timer Count Buffer 3 Timer Compare Buffer 3 R Timer Count Observation 3 R/W Timer Count Buffer 4 R Timer Count Observation 4

1-34

Page 36

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 9 of 14)

(B. Endian)

Address

(L. Endian)

Acc. Unit

Read/

Write

Function

USB Device

FUNC_ADDR_REG 0x52000143 0x52000140 B R/W Function Address PWR_REG 0x52000147 0x52000144 Power Management EP_INT_REG 0x5200014B 0x52000148 EP Interrupt Pending and Clear USB_INT_REG 0x5200015B 0x52000158 USB Interrupt Pending and Clear EP_INT_EN_REG 0x5200015F 0x5200015C Interrupt Enable USB_INT_EN_REG 0x5200016F 0x5200016C Interrupt Enable FRAME_NUM1_REG 0x52000173 0x52000170 R Frame Number Lower Byte FRAME_NUM2_REG 0x52000177 0x52000174 Frame Number Higher Byte INDEX_REG 0x5200017B 0x52000178 R/W Register Index EP0_CSR 0x52000187 0x52000184 Endpoint 0 Status IN_CSR1_REG 0x52000187 0x52000184 In Endpoint Control Status IN_CSR2_REG 0x5200018B 0x52000188 In Endpoint Control Status MAXP_REG 0x52000183 0x52000180 Endpoint Max Packet OUT_CSR1_REG 0x52000193 0x52000190 Out Endpoint Control Status OUT_CSR2_REG 0x52000197 0x52000194 Out Endpoint Control Status OUT_FIFO_CNT1_REG 0x5200019B 0x52000198 R Endpoint Out Write Count OUT_FIFO_CNT2_REG 0x5200019F 0x5200019C Endpoint Out Write Count EP0_FIFO 0x520001C3 0x520001C0 R/W Endpoint 0 FIFO EP1_FIFO 0x520001C7 0x520001C4 Endpoint 1 FIFO EP2_FIFO 0x520001CB 0x520001C8 Endpoint 2 FIFO EP3_FIFO 0x520001CF 0x520001CC Endpoint 3 FIFO EP4_FIFO 0x520001D3 0x520001D0 Endpoint 4 FIFO EP1_DMA_CON 0x52000203 0x52000200 EP1 DMA Interface Control EP1_DMA_UNIT 0x52000207 0x52000204 EP1 DMA Tx Unit Counter EP1_DMA_FIFO 0x5200020B 0x52000208 EP1 DMA Tx FIFO Counter EP1_DMA_TTC_L 0x5200020F 0x5200020C EP1 DMA Total Tx Counter EP1_DMA_TTC_M 0x52000213 0x52000210 EP1 DMA Total Tx Counter EP1_DMA_TTC_H 0x52000217 0x52000214 EP1 DMA Total Tx Counter

1-35

Page 37

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 10 of 14)

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/Write Function

USB Device (Continued)

EP2_DMA_CON 0x5200021B 0x52000218 B R/W EP2 DMA Interface Control EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit Counter EP2_DMA_FIFO 0x52000223 0x52000220 EP2 DMA Tx FIFO Counter EP2_DMA_TTC_L 0x52000227 0x52000224 EP2 DMA Total Tx Counter EP2_DMA_TTC_M 0x5200022B 0x52000228 EP2 DMA Total Tx Counter EP2_DMA_TTC_H 0x5200022F 0x5200022C EP2 DMA Total Tx Counter EP3_DMA_CON 0x52000243 0x52000240 EP3 DMA Interface Control EP3_DMA_UNIT 0x52000247 0x52000244 EP3 DMA Tx Unit Counter EP3_DMA_FIFO 0x5200024B 0x52000248 EP3 DMA Tx FIFO Counter EP3_DMA_TTC_L 0x5200024F 0x5200024C EP3 DMA Total Tx Counter EP3_DMA_TTC_M 0x52000253 0x52000250 EP3 DMA Total Tx Counter EP3_DMA_TTC_H 0x52000257 0x52000254 EP3 DMA Total Tx Counter EP4_DMA_CON 0x5200025B 0x52000258 EP4 DMA Interface Control EP4_DMA_UNIT 0x5200025F 0x5200025C EP4 DMA Tx Unit Counter EP4_DMA_FIFO 0x52000263 0x52000260 EP4 DMA Tx FIFO Counter EP4_DMA_TTC_L 0x52000267 0x52000264 EP4 DMA Total Tx Counter EP4_DMA_TTC_M 0x5200026B 0x52000268 EP4 DMA Total Tx Counter EP4_DMA_TTC_H 0x5200026F 0x5200026C EP4 DMA Total Tx Counter

Watchdog Timer

WTCON 0x53000000 ← W R/W Watchdog Timer Mode WTDAT 0x53000004 Watchdog Timer Data WTCNT 0x53000008 Watchdog Timer Count IIC IICCON 0x54000000 ← W R/W IIC Control IICSTAT 0x54000004 IIC Status IICADD 0x54000008 IIC Address IICDS 0x5400000C IIC Data Shift IICLC 0x54000010 IIC multi-master line control IIS IISCON 0x55000000,02 0x55000000 HW,W R/W IIS Control IISMOD 0x55000004,06 0x55000004 IIS Mode IISPSR 0x55000008,0A 0x55000008 IIS Prescaler IISFCON 0x5500000C,0E 0x5500000C IIS FIFO Control IISFIFO 0x55000012 0x55000010 HW IIS FIFO Entry

1-36

Page 38

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 11 of 14)

Name

Address

(B. Endian)

Address

(L.

Endian)

I/O port

GPACON 0x56000000

←

GPADAT 0x56000004 GPBCON 0x56000010 GPBDAT 0x56000014 GPBUP 0x56000018 GPCCON 0x56000020 GPCDAT 0x56000024 GPCUP 0x56000028 GPDCON 0x56000030 GPDDA1T 0x56000034 GPDUP 0x56000038 GPECON 0x56000040 GPEDAT 0x56000044 GPEUP 0x56000048 GPFCON 0x56000050 GPFDAT 0x56000054 GPFUP 0x56000058 GPGCON 0x56000060 GPGDAT 0x56000064 GPGUP 0x56000068 GPHCON 0x56000070 GPHDAT 0x56000074 GPHUP 0x56000078 GPJCON 0x560000D0 GPJDAT 0x560000D4 GPJUP 0x560000D8 MISCCR 0x56000080 DCLKCON 0x56000084 EXTINT0 0x56000088 EXTINT1 0x5600008C EXTINT2 0x56000090

Acc. Unit

Read/

Write

Function

W R/W Port A Control

Port A Data Port B Control Port B Data Pull-up Control B Port C Control Port C Data Pull-up Control C Port D Control Port D Data Pull-up Control D Port E Control Port E Data Pull-up Control E Port F Control Port F Data Pull-up Control F Port G Control Port G Data Pull-up Control G Port H Control Port H Data Pull-up Control H Port J Control Port J Data Pull-up Control J Miscellaneous Control DCLK0/1 Control External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2

1-37

Page 39

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 12 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

I/O port (Continued)

EINTFLT0 0x56000094 EINTFLT1 0x56000098 EINTFLT2 0x5600009C EINTFLT3 0x560000A0 EINTMASK 0x560000A4 EINTPEND 0x560000A8 GSTATUS0 0x560000AC GSTATUS1 0x560000B0 GSTATUS2 0x560000B4 GSTATUS3 0x560000B8 GSTATUS4 0x560000BC MSLCON 0x560000CC

←

W R/W Reserved

Reserved External Interrupt Filter Control Register 2 External Interrupt Filter Control Register 3 External Interrupt Mask External Interrupt Pending

R External Pin Status R/W Chip ID Reset Status Inform Register Inform Register Memory Sleep Control Register

RTC

RTCCON 0x57000043 0x57000040 B R/W RTC Control TICNT 0x57000047 0x57000044 Tick time count RTCALM 0x57000053 0x57000050 RTC Alarm Control ALMSEC 0x57000057 0x57000054 Alarm Second ALMMIN 0x5700005B 0x57000058 Alarm Minute ALMHOUR 0x5700005F 0x5700005C Alarm Hour ALMDATE 0x57000063 0x57000060 Alarm Day ALMMON 0x57000067 0x57000064 Alarm Month ALMYEAR 0x5700006B 0x57000068 Alarm Year BCDSEC 0x57000073 0x57000070 BCD Second BCDMIN 0x57000077 0x57000074 BCD Minute BCDHOUR 0x5700007B 0x57000078 BCD Hour BCDDATE 0x5700007F 0x5700007C BCD Day BCDDAY 0x57000083 0x57000080 BCD Date BCDMON 0x57000087 0x57000084 BCD Month BCDYEAR 0x5700008B 0x57000088 BCD Year

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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 13 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

A/D converter

ADCCON 0x58000000 ADCTSC 0x58000004

←

W R/W ADC Control

ADC Touch Screen Control

ADCDLY 0x58000008 ADC Start or Interval Delay ADCDAT0 0x5800000C R ADC Conversion Data ADCDAT1 0x58000010 ADC Conversion Data ADCUPDN 0x58000014 R/W Stylus Up or Down Interrpt status SPI SPCON0,1 0x59000000,20

←

W R/W SPI Control SPSTA0,1 0x59000004,24 R SPI Status SPPIN0,1 0x59000008,28 R/W SPI Pin Control SPPRE0,1 0x5900000C,2C SPI Baud Rate Prescaler SPTDAT0,1 0x59000010,30 SPI Tx Data SPRDAT0,1 0x59000014,34 R SPI Rx Data

SD interface

SDICON 0x5A000000

←

W R/W SDI Control SDIPRE 0x5A000004 SDI Baud Rate Prescaler SDICARG 0x5A000008 SDI Command Argument SDICCON 0x5A00000C SDI Command Control SDICSTA 0x5A000010 R/(C) SDI Command Status SDIRSP0 0x5A000014 R SDI Response SDIRSP1 0x5A000018 SDI Response SDIRSP2 0x5A00001C SDI Response SDIRSP3 0x5A000020 SDI Response SDIDTIMER 0x5A000024 R/W SDI Data / Busy Timer SDIBSIZE 0x5A000028 SDI Block Size SDIDCON 0x5A00002C

SDI Data control SDIDCNT 0x5A000030 R SDI Data Remain Counter SDIDSTA 0x5A000034 R/(C) SDI Data Status SDIFSTA 0x5A000038 R SDI FIFO Status SDIIMSK 0x5A00003C

←

W SDI Interrupt Mask

SDIDAT 0x5A000043 0x5A000040 B R/W SDI Data

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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 14 of 14)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

AC97 Audio-CODEC Interface

AC_GLBCTRL 0x5B000000 R/W AC97 Global Control Register AC_GLBSTAT

0x5B000004 R AC97 Global Status Register

←

AC_CODEC_CMD 0x5B000008 R/W AC97 Codec Command Register AC_CODEC_STAT 0x5B00000C R AC97 Codec Status Register AC_PCMADDR 0x5B000010 AC97 PCM Out/In Channel FIFO

Address Register

AC_MICADDR 0x5B000014 AC97 Mic In Channel FIFO Address

AC_PCMDATA 0x5B000018 R/W AC97 PCM Out/In Channel FIFO

Data Register

AC_MICDATA 0x5B00001C

AC97 MIC In Channel FIFO Data

Cautions on S3C2440A Special Registers

1. In the little endian mode ‘L’, endian address must be used. In the big endian mode ‘B’ endian address must be used.

2. The special registers have to be accessed for each recommended access unit.

3. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32bit) in little/big endian.

4. Make sure that the ADC registers, RTC registers and UART registers be read/write by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used.

5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer(int *).

HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *).

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2 PROGRAMMER'S MODEL

OVERVIEW

S3C2440A is developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd.

PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of the two states:

• ARM state which executes 32-bit, word-aligned ARM instructions

• THUMB state is a state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC

uses bit 1 to select between alternate halfwords

NOTES

Transition between these two states does not affect the processor mode or the contents of the registers.

SWITCHING STATE Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register.

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception is entered with the processor in THUMB state.

Entering ARM State Entry into ARM state can be done by the following methods:-

• On execution of the BX instruction with the state bit clear in the operand register.

• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is

placed in the exception mode's link register, and execution commences at the exception's vector address.

MEMORY FORMATS

ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in Big-Endian or Little-Endian format.

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BIG-ENDIAN FORMAT

In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.

Higher Address

Lower Address

31 8

4 0

Most significant byte is at lowest address. Word is addressed by byte address of most significant byte.

24 1516

9 5 1

10 6 2

87 0

11 7 3

Word Address

8 4 0

Figure 2-1. Big-Endian Addresses of Bytes within Words

LITTLE-ENDIAN FORMAT

In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.

Higher Address

31 23 8 7 0

24 1516

Word Address

8 4 0

Lower Address

11 7 3

Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.

10 6 2

9 5 1

Figure 2-2. Little-Endian Addresses of Bytes within Words

INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). Data Types

ARM920T supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.

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S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

OPERATING MODES ARM920T supports seven modes of operation:

• User (usr): The normal ARM program execution state

• FIQ (fiq): Designed to support a data transfer or channel process

• IRQ (irq): Used for general-purpose interrupt handling

• Supervisor (svc): Protected mode for the operating system

• Abort mode (abt): Entered after a data or instruction prefetch abort

• System (sys): A privileged user mode for the operating system

• Undefined (und): Entered when an undefined instruction is executed

Mode changes can be made using the control of software, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.

REGISTERS

ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode decides which registers are available to the programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which register is available in each mode: the banked registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information.

This register is used as the subroutine link register. This receives a copy of R15 when a Branch and Link (BL) instruction is executed. Rest of the time it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines.

This register holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.

This register is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state there are many FIQ handlers which don’t require saving registers. User, IRQ, Supervisor, Abort and Undefined, each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

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ARM State General Registers and Program Counter

System & User

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC)

CPSR CPSR

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 R8_

fiq

R9_

fiq

R10_

fiq

R11_

fiq

R12_

fiq

R13_

fiq

R14_

fiq

R15 (PC)

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_

svc

R14_

svc

R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ R14_ R15 (PC)

ARM State Program Status Registers

CPSR

SPSR_

fiq

CPSR

SPSR_

svc

abt abt

abt

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_

irq

R14_

irq

R15 (PC)

CPSR

SPSR_irq

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ R14_ R15 (PC)

CPSR

SPSR_

und und

und

= banked register

Figure 2-3. Register Organization in ARM State

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S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

The THUMB State Register Set

The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Progr am Counter (PC), a stack pointer regis ter (SP), a link r egister (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.

THUMB State General Registers and Program Counter

System & User

R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC

CPSR CPSR

= banked register

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 SP_ LR_ PC

fiq

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 SP_ LR_ PC

svc svc

R0 R1 R2 R3 R4 R5 R6 R7 SP_ LR_ PC

abt abt

THUMB State Program Status Registers

SPSR_

fiq

CPSR

SPSR_

svc

CPSR

SPSR_

abt

R0 R1 R2 R3 R4 R5 R6 R7

und

SP_ LR_

und

CPSR

SPSR_

irq

R0 R1 R2 R3 R4 R5 R6 R7

fiq

SP_ LR_

fiq

CPSR

SPSR_

und

Figure 2-4. Register Organization in THUMB state

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PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

The relationship between ARM and THUMB state registers The relationship between ARM and THUMB state registers are as below:-

• THUMB state R0-R7 and ARM state R0-R7 are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical

• THUMB state SP maps onto ARM state R13

• THUMB state LR maps onto ARM state R14

• The THUMB state Program Counter maps onto the ARM state Program Counter (R15)

This relationship is shown in Figure 2-5.

THUMB state ARM state

R0 R1 R2 R3 R4 R5 R6 R7

Stack Pointer (SP)

Link register (LR)

Program Counter (PC)

CPSR SPSR

Stack Pointer (R13)

Link register (R14)

Program Counter (R15)

R0 R1 R2 R3 R4 R5 R6 R7 R8

R9 R10 R11 R12

CPSR SPSR

Lo-registersHi-registers

Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers

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S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

Accessing Hi-Registers in THUMB State

In THUMB state, registers R8-R15 (“Hi registers”) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.

A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, Please refer to Figure 3-34.

THE PROGRAM STATUS REGISTERS

The ARM920T contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are:

• Hold information about the most recently performed ALU operation

• Control the enabling and disabling of interrupts

• Set the processor operating mode

The arrangement of bits is shown in Figure 2-6.

Condition Code Flags

30 29 2728 26252423 876543210

Z C V I F T M4 M3 M2 M1 M0

Overflow Carry/Borrow/Extend Zero Negative/Less Than

(Reserved) Control Bits

Figure 2-6. Program Status Register Format

Mode bits State bit FIQ disable IRQ disable

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PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

The Condition Code Flags

The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.

In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.

The Control Bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.

The T bit This reflects the operating state. When this bit is set, the processor is executed in

THUMB state, or otherwise it is executing in ARM state. This is reflected on the TBIT external signal.

Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.

Interrupt disable bits I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ

interrupts respectively.

The mode bits The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the

processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied.

Reserved bits

The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.

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Table 2-1. PSR Mode Bit Values

M[4:0] Mode Visible THUMB state registers Visible ARM state registers

10000 User R7..R0,

LR, SP

R14..R0, PC, CPSR

PC, CPSR

10001 FIQ R7..R0,

LR_fiq, SP_fiq PC, CPSR, SPSR_fiq

10010 IRQ R7..R0,

LR_irq, SP_irq PC, CPSR, SPSR_irq

10011 Supervisor R7..R0,

LR_svc, SP_svc, PC, CPSR, SPSR_svc

10111 Abort R7..R0,

LR_abt, SP_abt, PC, CPSR, SPSR_abt

11011 Undefined R7..R0

LR_und, SP_und, PC, CPSR, SPSR_und

11111 System R7..R0,

LR, SP

R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq

R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq

R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc

R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt

R12..R0, R14_und, R13_und, PC, CPSR

R14..R0, PC, CPSR

PC, CPSR

Reserved bits The remaining bits in the PSR's are reserved. While changing a PSR's flag or control bits , you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.

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EXCEPTIONS

Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.

It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14.

Action on Entering an Exception

While handling an exception, the ARM920T does following activities:

1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state.

2. Copies the CPSR into the appropriate SPSR

3. Forces the CPSR mode bits to a value which depends on the exception

4. Forces the PC to fetch the next instruction from the relevant exception vector

It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the

PC is loaded with the exception vector address.

Action on Leaving an Exception

On completion, the exception handler:

1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.)

2. Copies the SPSR back to the CPSR

3. Clears the interrupt disable flags, if they were set on entry

NOTES

An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception.

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Exception Entry/Exit Summary

Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.

Table 2-2. Exception Entry/Exit

Return Instruction Previous State Notes ARM R14_x THUMB R14_x

BL MOV PC, R14 PC + 4 PC + 2 1 SWI MOVS PC, R14_svc PC + 4 PC + 2 1 UDEF MOVS PC, R14_und PC + 4 PC + 2 1 FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4 2 IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4 2 PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4 1 DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8 3 RESET NA – – 4

NOTES:

1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.

2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.

3. Where PC is the address of the Load or Store instruction which generated the data abort.

4. The value saved in R14_svc upon reset is unpredictable.

FIQ

The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching).

FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing

SUBS PC,R14_fiq,#4

FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction.

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IRQ

The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting I bit in the CPSR, though this can only be done from a privileged (non-User) mode.

Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing

SUBS PC,R14_irq,#4

Abort

An abort indicates that the current memory access cannot be completed. It can be signaled by the external ABORT input. ARM920T checks for the abort exception during memory access cycles.

There are two types of abort:

• Prefetch Abort: occurs during an instruction prefetch.

• Data Abort: occurs during a data access.

If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed – the abort doesn’t take place because a branch occurs while it is in the pipeline -.

If a data abort occurs, the action taken depends on the instruction type:

• Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this.

• The swap instruction (SWP) is aborted as though it had not been executed.

• Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the

instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction.

The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort.

After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb):

SUBS PC,R14_abt,#4 ; for a prefetch abort, or SUBS PC,R14_abt,#8 ; for a data abort

This restores both the PC and the CPSR, and retries the aborted instruction.

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Software Interrupt

The Software Interrupt Instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):

MOV PC,R14_svc

This restores the PC and CPSR, and returns to the instruction following the SWI.

NOTES

nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core.

Undefined Instruction

When ARM920T comes across an instruction which cannot be handled, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.

After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb):

MOVS PC,R14_und

This restores the CPSR and returns to the instruction following the undefined instruction.

Exception Vectors

The following table shows the exception vector addresses.

Table 2-3. Exception Vectors

Address Exception Mode in Entry

0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software Interrupt Supervisor

0x0000000C Abort (prefetch) Abort

0x00000010 Abort (data) Abort 0x00000014 Reserved Reserved 0x00000018 IRQ IRQ

0x0000001C FIQ FIQ

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Exception Priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled:

Highest priority:

1. Reset

2. Data abort

3. FIQ

4. IRQ

5. Prefetch abort

Lowest priority:

6. Undefined Instruction, Software interrupt.

Not All Exceptions Can Occur at Once:

Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (nonoverlapping) decodings of the current instruction.

If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations.

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INTERRUPT LATENCIES

The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the instruction at 0x1C.

Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchronizer (Tsyncmin) plus Tfiq. This is 4 processor cycles.

RESET

When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses.

When nRESET goes HIGH again, ARM920T:

1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined.

2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit.

3. Forces the PC to fetch the next instruction from address 0x00.

4. Execution resumes in ARM state.

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NOTES

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

3 ARM INSTRUCTION SET

INSTRUCTION SET SUMMAY

This chapter describes the ARM instruction set in the ARM920T core.

FORMAT SUMMARY

The following figure shows the ARM instruction set.

27 26 252423 22 21 201918 17 16 15 1314 12 11 1031302928 9876543210

Cond Rn Data/Processing/

Cond Cond Cond Cond Cond

Cond

Cond Cond Cond Cond Cond

Cond

0000 00AS

000 0 001B

000PU0WL

000PU1WL

01IPUBWL 01I 100PUBWL 10 L1 110PUBWL

11 01

11 01L

11 11

Opcode

0I S

ASU100 00

10001000

CP Opc

Opc

11111111

CRn

Offset

CRd

Ignored by processor

Operand2

RnRdHi RdLo

Offset

CP#

PSR Transfer

Offset

CRm

Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer:

immendiate offset Single Data Transfer

Undefined Block Data Transfer Branch Coprocessor Data Transfer

Coprocessor Data Operation

Coprocessor Register Transfer

Software Interrupt

27 26 252423 22 21 201918 17 16 15 1314 12 11 1031302928 9876543210

Figure 3-1. ARM Instruction Se t Format

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NOTES

Some instruction codes are not defined but does not cause Undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.

INSTRUCTION SUMMARY

Table 3-1. The ARM Instruction Set

Mnemonic Instruction Action

ADC Add with carry Rd: = Rn + Op2 + Carry ADD Add Rd: = Rn + Op2 AND AND Rd: = Rn AND Op2

B Branch R15: = address

BIC Bit Clear Rd: = Rn AND NOT Op2

BL Branch with Link R14: = R15, R15: = address

BX Branch and Exchange R15: = Rn, T bit: = Rn[0]

CDP Coprocessor Data Processing (Coprocessor-specific) CMN Compare Negative CPSR flags: = Rn + Op2 CMP Compare CPSR flags: = Rn - Op2 EOR Exclusive OR Rd: = (Rn AND NOT Op2)

OR (Op2 AND NOT Rn) LDC Load coprocessor from memory Coprocessor load LDM Load multiple registers Stack manipulation (Pop) LDR Load register from memory Rd: = (address)

MCR Move CPU register to coprocessor

cRn: = rRn {<op>cRm}

MLA Multiply Accumulate

Rd: = (Rm × Rs) + Rn

MOV Move register or constant Rd: = Op2

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Table 3-1. The ARM Instruction Set (Continued)

Mnemonic Instruction Action

MRC Move from coprocessor register to

Rn: = cRn {<op>cRm}

CPU register MRS Move PSR status/flags to register Rn: = PSR MSR Move register to PSR status/flags PSR: = Rm

MUL Multiply

MVN Move negative register

Rd: = Rm × Rs Rd: = 0 × FFFFFFFF EOR Op2

ORR OR Rd: = Rn OR Op2

RSB Reverse Subtract Rd: = Op2 - Rn RSC Reverse Subtract with Carry Rd: = Op2 - Rn - 1 + Carry SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry STC Store coprocessor register to memory address: = CRn STM Store Multiple Stack manipulation (Push) STR Store register to memory <address>: = Rd SUB Subtract Rd: = Rn - Op2

SWI Software Interrupt OS call

SWP Swap register with memory Rd: = [Rn], [Rn] := Rm

TEQ Test bitwise equality CPSR flags: = Rn EOR Op2

TST Test bits CPSR flags: = Rn AND Op2

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THE CONDITION FIELD

In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored.

There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set.

In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used.

In the absence of a suffix, the condition field for most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes.

Table 3-2. Condition Code Summary

Code Suffix Flags Meaning

0000 EQ Z set equal 0001 NE Z clear not equal 0010 CS C set unsigned higher or same 0011 CC C clear unsigned lower 0100 MI N set negative 0101 PL N clear positive or zero 0110 VS V set overflow 0111 VC V clear no overflow 1000 HI C set and Z clear unsigned higher 1001 LS C clear or Z set unsigned lower or same 1010 GE N equals V greater or equal 1011 LT N not equal to V less than 1100 GT Z clear AND (N equals V) greater than 1101 LE Z set OR (N not equal to V) less than or equal 1110 AL (ignored) always

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND EXCHANGE (BX)

This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter,

PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions.

31 2427 19 15 8 7 0

28 16 111223 20 4 3

Cond Rn

000 1 100 0 111 1 111 1 111 1 000 1

[3:0] Operand Register

If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions

[31:28] Condition Field

Figure 3-2. Branch and Exchange Instructions

INSTRUCTION CYCLE TIMES

The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively.

ASSEMBLER SYNTAX

BX - branch and exchange. BX {cond} Rn

{cond} Two character condition mnemonic. See Table 3-2. Rn is an expression evaluating to a valid register number.

USING R15 AS AN OPERAND If R15 is used as an operand, the behavior is undefined.

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Examples

ADR R0, Into_THUMB + 1

BX R0

CODE16

Into_THUMB

ADR R5, Back_to_ARM

BX R5

ALIGN

CODE32

Back_to_ARM

Generate branch target address and set bit 0 high – hence it comes in THUMB state

Branch and change to THUMB state.

Assemble subsequent code as

THUMB instructions

Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state.

Branch and change back to ARM state.

Word alignment

Assemble subsequent code as ARM instructions

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND BRANCH WITH LINK (B, BL)

The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below.

31 2427

28 23

Cond Offset

101

[24] Link bit

0 = Branch 1 = Branch with link

[31:28] Condition Field

Figure 3-3. Branch Instructions

Branch instruction contains a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction.

Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required.

THE LINK BIT

Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared.

To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.

INSTRUCTION CYCLE TIMES

Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle).

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ASSEMBLER SYNTAX Items in “{}” are optional. Items in “<>” must be present. B{L}{cond} <expression>

{L}

Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction.

{cond}

A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be used.

The destination. The assembler calculates the offset

Examples here BAL here ; Assembles to 0xEAFFFFFE (note effect of PC offset).

B there ; Always condition used as default. CMP R1,#0 ; Compare R1 with zero and branch to fred if R1 was zero, otherwise continue. BEQ fred ; Continue to next instruction. BL sub+ROM ; Call subroutine at computed address. ADDS R1,#1 ; Add 1 to register 1, setting CPSR flags on the result then call subroutine if BLCC sub ; the C flag is clear, which will be the case unless R1 held 0xFFFFFFFF.

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

DATA PROCESSING

The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4.

31 2427 19 15

28 16 111221

26 25

Cond Operand2

00 L20OpCode S Rn Rd

[15:12] Destination register

0 = Branch 1 = Branch with link

[19:16] 1st operand register

0 = Branch 1 = Branch with link

[20] Set condition codes

0 = Do not after condition codes 1 = Set condition codes

[24:21] Operation codes

0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2

[25] Immediate operand

0 = Operand 2 is a register 1 = Operand 2 is an immediate value

[11:0] Operand 2 type selection

311 04

Shift

[3:0] 2nd operand register [11:4] Shift applied to Rm

811 07

Rotate

[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm

Imm

[31:28] Condition field

Figure 3-4. Data Processing Instructions

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn).

The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction.

Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3.

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

CPSR FLAGS

The data processing operations can be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected. The C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result.

Table 3-3. ARM Data Processing Instructions

Assembler Mnemonic OP Code Action

AND 0000 Operand1 AND operand2 EOR 0001 Operand1 EOR operand2 WUB 0010 Operand1 - operand2

RSB 0011 Operand2 operand1

ADD 0100 Operand1 + operand2

ADC 0101 Operand1 + operand2 + carry

SBC 0110 Operand1 - operand2 + carry - 1

RSC 0111 Operand2 - operand1 + carry - 1

TST 1000 As AND, but result is not written

TEQ 1001 As EOR, but result is not written CMP 1010 As SUB, but result is not written CMN 1011 As ADD, but result is not written ORR 1100 Operand1 OR operand2 MOV 1101 Operand2 (operand1 is ignored)

BIC 1110 Operand1 AND NOT operand2 (Bit clear)

MVN 1111 NOT operand2 (operand1 is ignored)

The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

SHIFTS

When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may contain an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5.

456711

[6:5] Shift type

00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right

[11:7] Shift amount

5 bit unsigned integer

0RS

[6:5] Shift type

00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right

[11:8] Shift register

Shift amount specified in bottom-byte of Rs

456711 8

Figure 3-5. ARM Shift Operations

Instruction specified shift amount

When the shift amount is specified in the instruction, it is contained in a 5 bit field which can take any value from 0 to 31. A Logical Shift Left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6.

31 27 26

Contents of Rm

carry out

Value of Operand 2

000000

Figure 3-6. Logical Shift Left

NOTES

LSL #0 is a special case, where the shifter carries out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A Logical Shift Right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7.

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

Contents of Rm

00000

Value of Operand 2

carry out

Figure 3-7. Logical Shift Right

The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.

An Arithmetic Shift Right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 3-8.

4530

Contents of Rm

Value of Operand 2

carry out

Figure 3-8. Arithmetic Shift Right

The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.

Contents of Rm

Value of Operand 2

carry out

Figure 3-9. Rotate Right

The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10.

Contents of Rm

carry out

Value of Operand 2

Figure 3-10. Rotate Right Extended

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15.

If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.

If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation.

If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:

1. LSL by 32 has result zero, carry out equal to bit 0 of Rm.

2. LSL by more than 32 has result zero, carry out zero.

3. LSR by 32 has result zero, carry out equal to bit 31 of Rm.

4. LSR by more than 32 has result zero, carry out zero.

5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.

6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.

7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above.

NOTES

The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

IMMEDIATE OPERAND ROTATES

The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2.

WRITING TO R15

When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above.

When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected.

When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which automatically restore both PC and CPSR. This form of instruction should not be used in User mode.

USING R15 AS AN OPERANDY

If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift

amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead.

TEQ, TST, CMP AND CMN OPCODES

NOTES

TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic.

The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead.

The action of TEQP in the ARM920T is to move SPSR_<mode> to the CPSR if the processor is in a privileged mode and to do nothing if in User mode.

INSTRUCTION CYCLE TIMES

Data Processing instructions vary in the number of incremental cycles taken as follows:

Table 3-4. Incremental Cycle Times

Processing Type Cycles

Normal data processing 1S Data processing with register specified shift 1S + 1I Data processing with PC written 2S + 1N Data processing with register specified shift and PC written 2S + 1N +1I

NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.

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ASSEMBLER SYNTAX

•••• MOV,MVN (single operand instructions).

•••• CMP,CMN,TEQ,TST (instructions which do not produce a result).

•••• AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC

where: <Op2> Rm{,<shift>} or,<#expression> {cond} A two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST). Rd, Rn and Rm Expressions evaluating to a register number. <#expression> If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to

match the expression. If this is impossible, it will give an error.

<shift> <Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with

extend).

<shiftname>s ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same

code.)

EXAMPLES ADDEQ R2,R4,R5 ; If the Z flag is set make R2:=R4+R5

TEQS R4,#3 ; Test R4 for equality with 3. ; (The S is in fact redundant as the ; assembler inserts it automatically.) SUB R4,R5,R7,LSR R2 ; Logical right shift R7 by the number in ; the bottom byte of R2, subtract result ; from R5, and put the answer into R4. MOV PC,R14 ; Return from subroutine. MOVS PC,R14 ; Return from exception and restore CPSR ; from SPSR_mode.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

PSR TRANSFER (MRS, MSR)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented

using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the

CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_<mode> register.

The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags (N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR.

OPERAND RESTRICTIONS

•••• In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the

CPSR can be changed. In other (privileged) modes the entire CPSR can be changed.

•••• Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor will

enter an unpredictable state.

•••• The SPSR register which is accessed depends on the mode at the time of execution. For example, only

SPSR_fiq is accessible when the processor is in FIQ mode.

•••• You must not specify R15 as the source or destination register.

•••• Also, do not attempt to access an SPSR in User mode, since no such register exists.

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MRS (transfer PSR contents to a register)

31 2227 1528 16 11122123

Cond 000000000000

00010 Rd

001111

[15:12] Destination Register [22] Source PSR

0 = CPSR 1 = SPSR_<current mode>

[31:28] Condition Field

MSR (transfer register contents to PSR)

31 222728 11122123

Cond 00000000

00010

101001111

43 0

[3:0] Source Register [22] Destination PSR

0 = CPSR 1 = SPSR_<current mode>

[31:28] Condition Field

MSR (transfer register contents or immediate value to PSR flag bits only)

31 222728 11122123

Cond Source operand

26 25 24 0

I1000

101001111

[22] Destination PSR

0 = CPSR 1 = SPSR_<current mode>

[25] Immediate Operand

0 = Source operand is a register 1 = SPSR_<current mode>

[11:0] Source Operand

11 4 3 0

00000000 Rm

[3:0] Source Register [11:4] Source operand is an immediate value

11 087

Rotate Imm

[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm

[31:28] Condition Field

Figure 3-11. PSR Transfer

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RESERVED BITS

Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits.

To ensure the maximum compatibility between ARM920T programs and future processors, the following rules should be observed:

• The reserved bits should be preserved while changing the value in a PSR.

• Programs should not rely on specific values from the reserved bits while checking the PSR status, since they

may read as one or zero in future processors.

A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction.

EXAMPLES

The following sequence performs a mode change: MRS R0,CPSR ; Take a copy of the CPSR.

BIC R0,R0,#0x1F ; Clear the mode bits. ORR R0,R0,#new_mode ; Select new mode MSR CPSR,R0 ; Write back the modified CPSR.

When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N,Z,C and V flags:

MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state ; (does not affect any control bits).

No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits.

INSTRUCTION CYCLE TIMES

PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle).

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ASSEMBLY SYNTAX

•••• MRS - transfer PSR contents to a register

MRS{cond} Rd,<psr>

•••• MSR - transfer register contents to PSR

MSR{cond} <psr>,Rm

•••• MSR - transfer register contents to PSR flag bits only

MSR{cond} <psrf>,Rm

The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.

•••• MSR - transfer immediate value to PSR flag bits only

MSR{cond} <psrf>,<#expression>

The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C and V flags respectively.

Key:

{cond} Two-character condition mnemonic. See Table 3-2.. Rd and Rm Expressions evaluating to a register number other than R15 <psr> CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR

and SPSR_all)

<psrf> CPSR_flg or SPSR_flg <#expression> Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field

to match the expression. If this is impossible, it will give an error.

EXAMPLES

In User mode the instructions behave as follows: MSR CPSR_all,Rm ; CPSR[31:28] <- Rm[31:28]

MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28] MSR CPSR_flg,#0xA0000000 ; CPSR[31:28] <- 0xA (set N,C; clear Z,V) MRS Rd,CPSR ; Rd[31:0] <- CPSR[31:0]

In privileged modes the instructions behave as follows: MSR CPSR_all,Rm ; CPSR[31:0] <- Rm[31:0]

MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28] MSR CPSR_flg,#0x50000000 ; CPSR[31:28] <- 0x5 (set Z,V; clear N,C) MSR SPSR_all,Rm ; SPSR_<mode>[31:0]<- Rm[31:0] MSR SPSR_flg,Rm ; SPSR_<mode>[31:28] <- Rm[31:28] MSR SPSR_flg,#0xC0000000 ; SPSR_<mode>[31:28] <- 0xC (set N,Z; clear C,V) MRS Rd,SPSR ; Rd[31:0] <- SPSR_<mode>[31:0]

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12.

The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.

31 27 19 15

28 16 111221 20

Cond

SRd Rn

87 43 0

Rs RmA000000

1001

[15:12][11:8][3:0] Operand Registers [19:16] Destination Register

[20] Set Condition Code

0 = Do not after condition codes 1 = Set condition codes

[21] Accumulate

0 = Multiply only 1 = Multiply and accumulate

[31:28] Condition Field

Figure 3-12. Multiply Instructions

The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers.

The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits - the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies.

For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

If the Operands Are Interpreted as Signed

Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38.

If the Operands Are Interpreted as Unsigned

Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38.

Operand Restrictions

The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register.

All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

CPSR FLAGS

Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected.

INSTRUCTION CYCLE TIMES

MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.

m The number of 8 bit multiplier array cycles is required to complete the multiply, which is

controlled by the value of the multiplier operand specified by Rs. Its possible values are

as follows 1 If bits [32:8] of the multiplier operand are all zero or all one. 2 If bits [32:16] of the multiplier operand are all zero or all one. 3 If bits [32:24] of the multiplier operand are all zero or all one. 4 In all other cases.

ASSEMBLER SYNTAX

MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn

{cond} Two-character condition mnemonic. See Table 3-2.. {S} Set condition codes if S present Rd, Rm, Rs and Rn Expressions evaluating to a register number other than R15.

EXAMPLES MUL R1,R2,R3 ; R1:=R2*R3

MLAEQS R1,R2,R3,R4 ; Conditionally R1:=R2*R3+R4, Setting condition codes.

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13.

The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations.

31 27 19 15

28 16 11122123

Cond

00 001

S RdHi RdLo

[11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers

[20] Set Condition Code

0 = Do not alter condition codes 1 = Set condition codes

[21] Accumulate

0 = Multiply only 1 = Multiply and accumulate

[22] Unsigned

0 = Unsigned 1 = Signed

[31:28] Condition Field

Figure 3-13. Multiply Long Instructions

87 43 0

Rs RmA

1001

The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi.

The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi.

The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

OPERAND RESTRICTIONS

• R15 must not be used as an operand or as a destination register.

• RdHi, RdLo, and Rm must all specify different registers.

CPSR FLAGS

Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values.

INSTRUCTION CYCLE TIMES

MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs.

Its possible values are as follows:

For Signed INSTRUCTIONS SMULL, SMLAL:

•••• If bits [31:8] of the multiplier operand are all zero or all one.

•••• If bits [31:16] of the multiplier operand are all zero or all one.

•••• If bits [31:24] of the multiplier operand are all zero or all one.

•••• In all other cases.

For Unsigned Instructions UMULL, UMLAL:

•••• If bits [31:8] of the multiplier operand are all zero.

•••• If bits [31:16] of the multiplier operand are all zero.

•••• If bits [31:24] of the multiplier operand are all zero.

•••• In all other cases.

S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLER SYNTAX

Table 3-5. Assembler Syntax Descriptions

Mnemonic Description Purpose

UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply & Accumulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply Long 32 x 32 = 64 SMLAL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply & Accumulate Long 32 x 32 + 64 = 64

where: {cond} Two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present RdLo, RdHi, Rm, Rs Expressions evaluating to a register number other than R15.

EXAMPLES UMULL R1,R4,R2,R3 ; R4,R1:=R2*R3

UMLALS R1,R5,R2,R3 ; R5,R1:=R2*R3+R5,R1 also setting condition codes

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

SINGLE DATA TRANSFER (LDR, STR)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14.

The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.

The result of this calculation may be written back into the base register if auto-indexing is required.

31 27 19 15 0

28 16 11122123

Cond

26 2425

01 I P U OffsetW

LRn Rd

[15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit

0 = Store to memory 1 = Load from memory

[21] Write-back Bit

0 = No write-back 1 = Write address into base

[22] Byte/Word Bit

0 = Transfer word quantity 1 = Transfer byte quantity

[23] Up/Down Bit

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset before transfer

[25] Immediate Offset

0 = Offset is an immediate value

[11:0] Offset

Immediate

[11:0] Unsigned 12-bit immediate offset

Shift

[3:0] Offset register [11:4] Shift applied to Rm

43 0

[31:28] Condition Field

Figure 3-14. Single Data Transfer Instructions

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OFFSETS AND AUTO-INDEXING

The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address.

The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit forces nonprivileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware.

SHIFTED REGISTER OFFSET

The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5.

BYTES AND WORDS

This instruction class may be used to transfer a byte (B=1) or a word (B=0) between an ARM920T register and memory.

The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM920T core. The two possible configurations are described below.

Little-Endian Configuration

A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8, if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2.

A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through

0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will

cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that halfwords accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits.

A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

A+3 A+2 A+1

memory

LDR from word aligned address

memory

LDR from address offset by 2

Figure 3-15. Little-Endian Offset Addressing

Big-Endian Configuration

A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1.

A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through

0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will

cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8.

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USE OF R15

Write-back must not be specified if R15 is specified as the base register (Rn). While using R15 as the base register, you must remember it contains an address of 8 bytes on from the address of the current instruction.

R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the

instruction plus 12. Restriction are made depending on the use of base register When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets

updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the

abort handler starts. Sometimes it may be impossible to calculate the initial value.

EXAMPLE: LDR R0,[R1],R1

Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used.

DATA ABORTS

A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.

INSTRUCTION CYCLE TIMES

Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

ASSEMBLER SYNTAX

<LDR|STR>{cond}{B}{T} Rd,<Address> where: LDR Load from memory into a register

STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. {B} If B is present then byte transfer, otherwise word transfer {T} If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged

mode for the transfer cycle. T is not allowed when a pre-indexed addressing mode is

specified or implied. Rd An expression evaluating to a valid register number. Rn and Rm Expressions evaluating to a register number. If Rn is R15 then the assembler will

subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-back should not be specified.

<Address>can be: 1 An expression which generates an address:

The assembler will attempt to generate an instruction using the PC as a base and a

corrected immediate offset to address the location given by evaluating the expression.

This will be a PC relative, pre-indexed address. If the address is out of range, an error

will be generated.

2 A pre-indexed addressing specification:

[Rn] offset of zero

[Rn,<#expression>]{!} offset of <expression> bytes

[Rn,{+/-}Rm{,<shift>}]{!} offset of +/- contents of index register, shifted

by <shift> 3 A post-indexed addressing specification:

[Rn],<#expression> offset of <expression> bytes

[Rn],{+/-}Rm{,<shift>} offset of +/- contents of index register, shifted as

by <shift>. <shift> General shift operation (see data processing instructions) but you cannot specify the shift

amount by a register.

{!} Writes back the base register (set the W bit) if! is present.

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EXAMPLES STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers)

; and write back address to R2. STR R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back. LDR R1,[R2,R3,LSL#2] ; Load R1 from contents of R2+R3*4. LDREQB R1,[R6,#5] ; Conditionally load byte at R6+5 into ; R1 bits 0 to 7, filling bits 8 to 31 with zeros. STR R1,PLACE ; Generate PC relative offset to address PLACE. PLACE

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16.

These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required.

31 27 19 15

28 16 11122123

Cond

2425

000 P U 0000W

LRn Rd

[3:0] Offset Register [6][5] S H

0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword

[15:12] Source/Destination Register [19:16] Base Register [20] Load/Store

0 = Store to memory 1 = Load from memory

[21] Write-back

0 = No write-back 1 = Write address into base

[23] Up/Down

0 = Down: subtract offset from base 1 = Up: add offset to base

876543 0

1RmSH1

[24] Pre/Post Indexing

0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer

[31:28] Condition Field

Figure 3-16. Halfword and Signed Data Transfer with Register Offset

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31 27 19 15

28 16 11122123

Cond

2425

000 P U OffsetW

LRn Rd

[3:0] Immediate Offset (Low Nibble) [6][5] S H

0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword

[11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store

0 = Store to memory 1 = Load from memory

[21] Write-back

0 = No write-back 1 = Write address into base

876543 0

1 OffsetSH1

[23] Up/Down

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing

0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer

[31:28] Condition Field

Figure 3-17. Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing

OFFSETS AND AUTO-INDEXING

The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (postindexed, P=0) the base register is used as the transfer address.

The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base.

The Write-back bit should not be set high (W=1) when post-indexed addressing is selected.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

HALFWORD LOAD AND STORES

Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible

configurations are described in the section below.

Signed byte and halfword loads

The S bit controls the loading of sign-extended data. When S=1 the H bit selects between Bytes (H=0) and Halfwords (H=1). The L bit should not be set low (Store) when Signed (S=1) operations have been selected.

The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit.

The LDRSH instruction loads the selected Half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit.

The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the following section.

Endianness and byte/halfword selection

Little-Endian Configuration

A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-2.

A halfword load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary, (A[1]=1).The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword.

A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour.

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Big-Endian Configuration

A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1.

A halfword load (LDRSH or LDRH) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary, (A[1]=1). The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword.

Note

Please note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable

behavior.

USE OF R15

Write-back should not be specified if R15 is specified as the base register (Rn). While using R15 as the base register you must remember it contains address 8 bytes on from the address of the current instruction.

R15 should not be specified as the register offset (Rm). When R15 is the source register (Rd) of a Half-word store (STRH) instruction, the stored address will be address

of the instruction plus 12.

DATA ABORTS

A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from the main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.

INSTRUCTION CYCLE TIMES

Normal LDR(H,SH,SB) instructions take 1S + 1N + 1I. LDR(H,SH,SB) PC take 2S + 2N + 1I incremental cycles. S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STRH instructions take 2N incremental cycles to execute.

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ASSEMBLER SYNTAX

<LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load from memory into a register

STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2.. H Transfer halfword quantity SB Load sign extended byte (Only valid for LDR) SH Load sign extended halfword (Only valid for LDR) Rd An expression evaluating to a valid register number.

<address> can be: 1 An expression which generates an address:

The assembler will attempt to generate an instruction using the PC as a base and a

corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated.

2 A pre-indexed addressing specification:

[Rn] offset of zero

[Rn,<#expression>]{!} offset of <expression> bytes

[Rn,{+/-}Rm]{!} offset of +/- contents of index register

3 A post-indexed addressing specification:

[Rn],<#expression> offset of <expression> bytes

[Rn],{+/-}Rm offset of +/- contents of index register.

4 Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the

assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-back should not be specified.

{!} Writes back the base register (set the W bit) if ! is present.

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EXAMPLES LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address

; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back. LDRSB R8,[R2],#-223 ; Load R8 with the sign extended contents of the byte ; address contained in R2 and write back R2-223 to R2. LDRNESH R11,[R0] ; Conditionally load R11 with the sign extended contents ; of the halfword address contained in R0. HERE ; Generate PC relative offset to address FRED. STRH R5, [PC,#(FRED-HERE-8)]; Store the halfword in R5 at address FRED FRED

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

BLOCK DATA TRANSFER (LDM, STM)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18.

Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.

THE REGISTER LIST

The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on.

Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty.

Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12.

31 27 19 15

28 162123

Cond

2425

24 0

100 P U W

LRn

[19:16] Base Register [20] Load/Store Bit

0 = Store to memory 1 = Load from memory

[21] Write-back Bit

0 = No write-back 1 = Write address into base

[22] PSR & Force User Bit

0 = Do not load PSR or user mode 1 = Load PSR or force user mode

[23] Up/Down Bit

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer

[31:28] Condition Field

Figure 3-18. Block Data Transfer Instructions

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ADDRESSING MODES

The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed.

In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. (Please check the meaning again)*****

ADDRESS ALIGNMENT

The address should normally be a word aligned quantity and non-word aligned addresses should not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system.

0x100C

Rn R1

R5 R1

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

R7 R5 R1

Figure 3-19. Post-Increment Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

0x100C

0x1000

0x0FF4

0x100C R5 R1

0x1000

0x0FF4

R7Rn R5 R1

Figure 3-20. Pre-Increment Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

R5 R1

0x100C

0x1000

0x0FF4

R7 R5 R1

Figure 3-21. Post-Decrement Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

USE OF THE S BIT

0x100C

0x1000

R7 R5 R1

R5 R1

0x0FF4

0x100C

0x1000

0x0FF4

Figure 3-22. Pre-Decrement Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

When the S bit is set in a LDM/STM instruction it depends on R15 is available in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode.

LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_<mode> is transferred to CPSR at the same time as R15 is loaded.

STM with R15 in Transfer List and S Bit Set (User Bank Transfer)

The registers transferred are taken from the User bank rather than the bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed.

R15 not in List and S Bit Set (User Bank Transfer)

For both LDM and STM instructions, the User bank registers are transferred rather than the register bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed.

When the instruction is LDM, care must be taken not to read from a banked register during the following cycle (inserting a dummy instruction such as MOV R0, R0 after the LDM will ensure safety).

USE OF R15 AS THE BASE

R15 should not be used as the base register in any LDM or STM instruction.

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Samsung S3C2440A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

2 PROGRAMMER'S MODEL

3 ARM INSTRUCTION SET