Samsung S3C2440A User Manual
S3C2440A
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
PRELIMINARY
Revision 0.14
(June 30, 2004)
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
This user’s manual describes SAMSUNG's S3C2440A 16/32- bit RISC m icroproc essor . SAMSUNG’s S3C2440A is
designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.
The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a m emory complier. Its lowpower, simple, elegant and fully static design is partic ularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2440A offers outstanding f eatures with its CPU core, a 16/32-bit ARM920T RISC process or designed by
Advanced RISC Machines, Ltd. The ARM920T im plements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals , the S3C2440A minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-c hip func tions that are des cribed in this
document include:
• Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-
Cache/MMU
• External memory controller (SDRAM Control and Chip Select logic)
• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA
• 4-ch DMA controllers with external request pins
• 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
• 2-ch SPls
• IIC bus interface (multi-master support)
• IIS Audio CODEC interface
• AC’97 CODEC interface
• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible
• 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)
• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
• 8-ch 10-bit ADC and Touch screen interface
• RTC with calendar function
• Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)
• 130 General Purpose I/O ports / 24-ch external interrupt source
• Power control: Normal, Slow, Idle and Sleep mode
• On-chip clock generator with PLL
1-1
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
FEATURES
Architecture
• Integrated system for hand-held devices and
general embedded applications.
• 16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core.
• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
• ARM920T CPU core supports the ARM debug
architecture.
• Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).
System Manager
• Little/Big Endian support.
• Support Fast bus mode and Asynchronous bus
mode.
• Address space: 128M bytes for each bank (total
1G bytes).
• Supports programmable 8/16/32-bit data bus
width for each bank.
• Fixed bank start address from bank 0 to bank 6.
• Programmable bank start address and bank size
for bank 7.
• Eight memory banks:
– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/
Synchronous DRAM.
• Complete Programmable access cycles for all
memory banks.
• Supports external wait signals to expand the bus
cycle.
NAND Flash Boot Loader
• Supports booting from NAND flash memory.
• 4KB internal buffer for booting.
• Supports storage memory for NAND flash
memory after booting.
• Supports Advanced NAND flash
Cache Memory
• 64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).
• 8words length per line with one valid bit and two
dirty bits per line.
• Pseudo random or round robin replacement
algorithm.
• Write-through or write-back cache operation to
update the main memory.
• The write buffer can hold 16 words of data and
four addresses.
Clock & Power Manager
• On-chip MPLL and UPLL:
UPLL generates the clock to operate USB
Host/Device.
MPLL generates the clock to operate MCU at
maximum 400Mhz @ 1.3V.
• Clock can be fed selectively to each function
block by software.
• Power mode: Normal, Slow, Idle, and Sleep
mode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLL
Idle mode: The clock for only CPU is stopped.
Sleep mode: The Core power including all
peripherals is shut down.
• Woken up by EINT[15:0] or RTC alarm interrupt
from Sleep mode
• Supports self-refresh mode in SDRAM for power-
down.
• Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, and others).
1-2
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
FEATURES (Continued)
Interrupt Controller
• 60 Interrupt sources
(One Watch dog timer, 5 timers, 9 UARTs, 24
external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC,
2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1
NAND and 2 Camera), 1 AC97
• Level/Edge mode on external interrupt source
• Programmable polarity of edge and level
• Supports Fast Interrupt request (FIQ) for very
urgent interrupt request
Timer with Pulse Width Modulation (PWM)
• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based
operation
• Programmable duty cycle, frequency, and polarity
• Dead-zone generation
• Supports external clock sources
RTC (Real Time Clock)
• Full clock feature: msec, second, minute, hour,
date, day, month, and year
• 32.768 KHz operation
• Alarm interrupt
• Time tick interrupt
General Purpose Input/Output Ports
• 24 external interrupt ports
• 130 Multiplexed input/output ports
gray levels, 256 colors and 4096 colors for STN
LCD
• Supports multiple screen size
– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4 Mbytes.
– Maximum virtual screen size in 256 color mode:
4096x1024, 2048x2048, 1024x4096 and others
TFT(Thin Film Transistor) Color Displays Feature
• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette
color displa ys for color TFT
• Supports 16, 24 bpp non-palette true-color
displays for color TFT
• Supports maximum 16M color TFT at 24 bpp
mode
• LPC3600 Timing controller embedded for
LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait /
256K-color/ Reflective a-Si TFT LCD)
• LCC3600 Timing controller embedded for
LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait /
256K-color/ Transflective a-Si TFT LCD)
• Supports multiple screen size
– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4Mbytes.
– Maximum virtual screen size in 64K color mode :
2048x1024, and others
UART
DMA Controller
• 4-ch DMA controller
• Supports memory to memory, IO to memory,
memory to IO, and IO to IO transfers
• Burst transfer mode to enhance the transfer rate
LCD Controller STN LCD Displays Feature
• Supports 3 types of STN LCD panels: 4-bit dual
scan, 4-bit single scan, 8-bit single scan display
type
• Supports monochrome mode, 4 gray levels, 16
1-3
• 3-channel UART with DMA-based or interrupt-
based operation
• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive (Tx/Rx)
• Supports external clocks for the UART operation
(UEXTCLK)
• Programmable baud rate
• Supports IrDA 1.0
• Loopback mode for testing
• Each channel has internal 64-byte Tx FIFO and
64-byte Rx FIFO.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
FEATURES (Continued)
A/D Converter & Touch Screen Interface
• 8-ch multiplexed ADC
• Max. 500KSPS and 10-bit Resolution
• Internal FET for direct Touch screen interface
Watchdog Timer
• 16-bit Watchdog Timer
• Interrupt request or system reset at time-out
IIC-Bus Interface
• 1-ch Multi-Master IIC-Bus
• Serial, 8-bit oriented and bi-directional data
transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.
IIS-Bus Interface
• 1-ch IIS-bus for audio interface with DMA-based
operation
• Serial, 8-/16-bit per channel data transfers
• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx
• Supports IIS format and MSB-justified data format
AC97 Audio-CODEC Interface
• Support 16-bit samples
• 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs
• DMA burst4 access support(only word transfer)
• Compatible with SD Memory Card Protocol
version 1.0
• Compatible with SDIO Card Protocol version 1.0
• 64 Bytes FIFO for Tx/Rx
• Compatible with Multimedia Card Protocol version
2.11
SPI Interface
• Compatible with 2-ch Serial Peripheral Interface
Protocol version 2.11
• 2x8 bits Shift register for Tx/Rx
• DMA-based or interrupt-based operation
Camera Interface
• ITU-R BT 601/656 8-bit mode support
• DZI (Digital Zoom In) capability
• Programmable polarity of video sync signals
• Max. 4096 x 4096 pixels input support ( 2048 x
2048 pixel input support for scaling)
• Image mirror and rotation (X-axis mirror, Y-axis
mirror, and 180° rotation)
• Camera output format (RGB 16/24-bit and YCbCr
4:2:0/4:2:2 format)
1-ch MIC input
USB Host
• 2-port USB Host
• Complies with OHCI Rev. 1.0
• Compatible with USB Specification version 1.1
USB Device
• 1-port USB Device
• 5 Endpoints for USB Device
• Compatible with USB Specification version 1.1
SD Host Interface
• Normal, Interrupt and DMA data transfer
mode(byte, halfword, word transfer)
1-4
Operating Voltage Range
• Core : 1.20V for 300MHz
1.30V for 400MHz
Memory:1.8V/ 2.5V/3.0V/3.3V
• I/O : 3.3V
Operating Frequency
• Fclk Up to 400MHz
• Hclk Up to 136MHz
• Pclk Up to 68MHz
Package
• 289-FBGA
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
BLOCK DIAGRAM
ARM920T
IVA[31:0]
JTAG
Clock Generator
(MPLL)
IPA[31:0]
Instruction
MMU
C13
ARM9TDMI
Processor core
(Internal Embedded ICE)
C13
Data
MMU
LCD
CONT.
USB Host CONT.
ExtMaster
NAND Ctrl.
NAND Flash Boot
Loader
DPA[31:0]
LCD
DMA
Instruction
CACHE
(16KB)
ID[31:0]
CP15
DD[31:0]
DVA[31:0]DVA[31:0]
Data
CACHE
(16KB)
A
H
B
B
U
S
Bridge & DMA (4Ch)
External
Coproc
Interface
Write
Buffer
WriteBack
PA Tag
RAM
BUS CONT.
Arbitor/Decode
Interrupt CONT.
Power
Management
Camera
Interface
Memory CONT.
SRAM/NOR/SDRAM
AMBA
Bus
I/F
WBPA[31:0]
UART 0, 1, 2
USB Device
I2C
I2S
A
SDI/MMC
Watchdog
Timer
BUS CONT.
Arbitor/Decode
SPI 0, 1
SPI
P
B
B
U
S
Figure 1-1. S3C2440A Block Diagram
1-5
GPIO
RTC
ADC
Timer/PWM
0 ~ 3, 4(Internal)
AC97
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
PIN ASSIGNMENTS
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1234567891011121314151617
BOTTOM VIEW
Figure 1-2. S3C2440A Pin Assignments (289-FBGA)
1-6
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
A1 VDDi C1 VDDMOP E1 nFRE/GPA20
A2 SCKE C2 nGCS5/GPA16 E2 VSSMOP
A3 VSSi C3 nGCS2/GPA13 E3 nGCS7
A4 VSSi C4 nGCS3/GPA14 E4 nWAIT
A5 VSSMOP C5 nOE E5 nBE3
A6 VDDi C6 nSRAS E6 nWE
A7 VSSMOP C7 ADDR4 E7 ADDR1
A8 ADDR10 C8 ADDR11 E8 ADDR6
A9 VDDMOP C9 ADDR15 E9 ADDR14
A10 VDDi C10 ADDR21/GPA6 E10 ADDR23/GPA8
A11 VSSMOP C11 ADDR24/GPA9 E11 DATA2
A12 VSSi C12 DATA1 E12 DATA20
A13 DATA3 C13 DATA6 E13 DATA19
A14 DATA7 C14 DATA11 E14 DATA18
A15 VSSMOP C15 DATA13 E15 DATA17
A16 VDDi C16 DATA16 E16 DATA21
A17 DATA10 C17 VSSi E17 DATA24
B1 VSSMOP D1 ALE/GPA18 F1 VDDi
B2 nGCS1/GPA12 D2 nGCS6 F2 VSSi
B3 SCLK1 D3 nGCS4/GPA15 F3 nFWE/GPA19
B4 SCLK0 D4 nBE0 F4 nFCE/GPA22
B5 nBE1 D5 nBE2 F5 CLE/GPA17
B6 VDDMOP D6 nSCAS F6 nGCS0
B7 ADDR2 D7 ADDR7 F7 ADDR0/GPA0
B8 ADDR9 D8 ADDR5 F8 ADDR3
B9 ADDR12 D9 ADDR16/GPA1 F9 ADDR18/GPA3
B10 VSSi D10 ADDR20/GPA5 F10 DATA4
B11 VDDi D11 ADDR26/GPA11 F11 DATA5
B12 VDDMOP D12 DATA0 F12 DATA27
B13 VSSMOP D13 DATA8 F13 DATA31
B14 VDDMOP D14 DATA14 F14 DATA26
B15 DATA9 D15 DATA12 F15 DATA22
B16 VDDMOP D16 VSSMOP F16 VDDi
B17 DATA15 D17 VSSMOP F17 VDDMOP
1-7
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 3)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
G1 VSSOP J1 VDDOP L1 LEND/GPC0
G2 CAMHREF/GPJ10 J2 VDDiarm L2 VDDiarm
G3 CAMDATA1/GPJ1 J3 CAMCLKOUT/GPJ11 L3 nXDACK0/GPB9
G4 VDDalive J4 CAMRESET/GPJ12 L4 VCLK/GPC1
G5 CAMPCLK/GPJ8 J5 TOUT1/GPB1 L5 nXBREQ/GPB6
G6 FRnB J6 TOUT0/GPB0 L6 VD1/GPC9
G7 CAMVSYNC/GPJ9 J7 TOUT2/GPB2 L7 VFRAME/GPC3
G8 ADDR8 J8 CAMDATA6/GPJ6 L8 I2SSDI/AC_SDATA_IN
G9 ADDR17/GPA2 J9 SDDAT3/GPE10 L9 SPICLK0/GPE13
G10 ADDR25/GPA10 J10 EINT10/nSS0/GPG2 L10 EINT15/SPICLK1/GPG7
G11 DATA28 J11 TXD2/nRTS1/GPH6 L11 EINT22/GPG14
G12 DATA25 J12 PWREN L12 Xtortc
G13 DATA23 J13 TCK L13 EINT2/GPF2
G14 XTIpll J14 TMS L14 EINT5/GPF5
G15 XTOpll J15 RXD2/nCTS1/GPH7 L15 EINT6/GPF6
G16 DATA29 J16 TDO L16 EINT7/GPF7
G17 VSSi J17 VDDalive L17 nRTS0/GPH1
H1 VSSiarm K1 VSSiarm M1 VLINE/GPC2
H2 CAMDATA7/GPJ7 K2 nXBACK/GPB5 M2 LCD_LPCREV/GPC6
H3 CAMDATA4/GPJ4 K3 TOUT3/GPB3 M3 LCD_LPCOE/GPC5
H4 CAMDATA3/GPJ3 K4 TCLK0/GPB4 M4 VM/GPC4
H5 CAMDATA2/GPJ2 K5 nXDREQ1/GPB8 M5 VD9/GPD1
H6 CAMDATA0/GPJ0 K6 nXDREQ0/GPB10 M6 VD6/GPC14
H7 CAMDATA5/GPJ5 K7 nXDACK1/GPB7 M7 VD16/SPIMISO1/GPD8
H8 ADDR13 K8 SDCMD/GPE6 M8 SDDAT1/GPE8
H9 ADDR19/GPA4 K9 SPIMISO0/GPE11 M9 IICSDA/GPE15
H10 ADDR22/GPA7 K10 EINT13/SPIMISO1/GPG5 M10 EINT20/GPG12
H11 VSSOP K11 nCTS0/GPH0 M11 EINT17/nRTS1/GPG9
H12 EXTCLK K12 VDDOP M12 VSSA_UPLL
H13 DATA30 K13 TXD0/GPH2 M13 VDDA_UPLL
H14 nBATT_FLT K14 RXD0/GPH3 M14 Xtirtc
H15 nTRST K15 UEXTCLK/GPH8 M15 EINT3/GPF3
H16 nRESET K16 TXD1/GPH4 M16 EINT1/GPF1
H17 TDI K17 RXD1/GPH5 M17 EINT4/GPF4
1-8
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 3)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
N1 VSSOP R1 VD3/GPC11 U1 VDDiarm
N2 VD0/GPC8 R2 VD8/GPD0 U2 VDDiarm
N3 VD4/GPC12 R3 VD11/GPD3 U3 VSSOP
N4 VD2/GPC10 R4 VD13/GPD5 U4 VSSiarm
N5 VD10/GPD2 R5 VD18/SPICLK1/GPD10 U5 VD23/nSS0/GPD15
N6 VD15/GPD7 R6 VD21 /GPD13 U6 I2SSDO/AC_SDATA_OUT
N7 VD22/nSS1/GPD14 R7 I2SSCLK/AC_BIT_CLK U7 VSSiarm
N8 SDCLK/GPE5 R8 SDDAT0/GPE7 U8 IICSCL/GPE14
N9 EINT8/GPG0 R9 CLKOUT0/GPH9 U9 VSSOP
N10 EINT18/nCTS1/GPG10 R10 EINT11/nSS1/GPG3 U10 VSSiarm
N11 DP0 R11 EINT14/SPIMOSI1/GPG6 U11 VDDi
N12 DN1/PDN0 R12 NCON U12 EINT19/TCLK1/GPG11
N13 nRSTOUT/GPA21 R13 OM1 U13 EINT23/GPG15
N14 MPLLCAP R14 AIN0 U14 DP1/PDP0
N15 VDD_RTC R15 AIN2 U15 VSSOP
N16 VDDA_MPLL R16 XM/AIN6 U16 Vref
N17 EINT0/GPF0 R17 VSSA_MPLL U17 AIN1
P1 LCD_LPCREVB/GPC7 T1 VSSiarm
P2 VD5/GPC13 T2 VSSiarm
P3 VD7/GPC15 T3 VDDOP
P4 VD12/GPD4 T4 VD17/SPIMOSI1/GPD9
P5 VD14/GPD6 T5 VD19/GPD11
P6 VD20/GPD12 T6 VDDiarm
P7 I2SLRCK/AC_SYNC T7 CDCLK/AC_nRESET
P8 SDDAT2/GPE9 T8 VDDiarm
P9 SPIMOSI0/GPE12 T9 EINT9/GPG1
P10 CLKOUT1/GPH10 T10 EINT16/GPG8
P11 EINT12/LCD_PWREN/GPG4 T11 EINT21/GPG13
P12 DN0 T12 VDDOP
P13 OM2 T13 OM3
P14 VDDA_ADC T14 VSSA_ADC
P15 AIN3 T15 OM0
P16 XP/AIN7 T16 YM/AIN4
P17 UPLLCAP T17 YP/AIN5
1-9
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
F7 ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) t10s
E7 ADDR1 ADDR1 Hi-z O(L) O(L) t10s
B7 ADDR2 ADDR2 Hi-z O(L) O(L) t10s
F8 ADDR3 ADDR3 Hi-z O(L) O(L) t10s
C7 ADDR4 ADDR4 Hi-z O(L) O(L) t10s
D8 ADDR5 ADDR5 Hi-z O(L) O(L) t10s
E8 ADDR6 ADDR6 Hi-z O(L) O(L) t10s
D7 ADDR7 ADDR7 Hi-z O(L) O(L) t10s
G8 ADDR8 ADDR8 Hi-z O(L) O(L) t10s
B8 ADDR9 ADDR9 Hi-z O(L) O(L) t10s
A8 ADDR10 ADDR10 Hi-z O(L) O(L) t10s
C8 ADDR11 ADDR11 Hi-z O(L) O(L) t10s
B9 ADDR12 ADDR12 Hi-z O(L) O(L) t10s
H8 ADDR13 ADDR13 Hi-z O(L) O(L) t10s
E9 ADDR14 ADDR14 Hi-z O(L) O(L) t10s
C9 ADDR15 ADDR15 Hi-z O(L) O(L) t10s
D9 ADDR16/GPA1 ADDR16 Hi-z/– O(L)/– O(L) t10s
G9 ADDR17/GPA2 ADDR17 Hi-z/– O(L)/– O(L) t10s
F9 ADDR18/GPA3 ADDR18 Hi-z/– O(L)/– O(L) t10s
H9 ADDR19/GPA4 ADDR19 Hi-z/– O(L)/– O(L) t10s
D10 ADDR20/GPA5 ADDR20 Hi-z/– O(L)/– O(L) t10s
C10 ADDR21/GPA6 ADDR21 Hi-z/– O(L)/– O(L) t10s
H10 ADDR22/GPA7 ADDR22 Hi-z/– O(L)/– O(L) t10s
E10 ADDR23/GPA8 ADDR23 Hi-z/– O(L)/– O(L) t10s
C11 ADDR24/GPA9 ADDR24 Hi-z/– O(L)/– O(L) t10s
G10 ADDR25/GPA10 ADDR25 Hi-z/– O(L)/– O(L) t10s
D11 ADDR26/GPA11 ADDR26 Hi-z/– O(L)/– O(L) t10s
R14 AIN0 AIN0 – – AI r10
U17 AIN1 AIN1 – – AI r10
R15 AIN2 AIN2 – – AI r10
P15 AIN3 AIN3 – – AI r10
T16 YM/AIN4 AIN4 –/– –/– AI r10
T17 YP/AIN5 YP –/– –/– AI r10
R16 XM/AIN6 AIN6 –/– –/– AI r10
1-10
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
P16 XP/AIN7 XP –/– –/– AI r10
H6 CAMDATA0/GPJ0 GPJ0 –/– Hi-z/– I t8
G3 CAMDATA1/GPJ1 GPJ1 –/– Hi-z/– I t8
H5 CAMDATA2/GPJ2 GPJ2 –/– Hi-z/– I t8
H4 CAMDATA3/GPJ3 GPJ3 –/– Hi-z/– I t8
H3 CAMDATA4/GPJ4 GPJ4 –/– Hi-z/– I t8
H7 CAMDATA5/GPJ5 GPJ5 –/– Hi-z/– I t8
J8 CAMDATA6/GPJ6 GPJ6 –/– Hi-z/– I t8
H2 CAMDATA7/GPJ7 GPJ7 –/– Hi-z/– I t8
G5 CAMPCLK/GPJ8 GPJ8 –/– Hi-z/– I t8
G7 CAMVSYNC/GPJ9 GPJ9 –/– Hi-z/– I t8
G2 CAMHREF/GPJ10 GPJ10 –/– Hi-z/– I t8
J3 CAMCLKOUT/GPJ11 GPJ11 –/– O(L)/– I t8
J4 CAMRESET/GPJ12 GPJ12 –/– O(L)/– I t8
D12 DATA0 DATA0 Hi-z Hi-z,O(L) I b12s
C12 DATA1 DATA1 Hi-z Hi-z,O(L) I b12s
E11 DATA2 DATA2 Hi-z Hi-z,O(L) I b12s
A13 DATA3 DATA3 Hi-z Hi-z,O(L) I b12s
F10 DATA4 DATA4 Hi-z Hi-z,O(L) I b12s
F11 DATA5 DATA5 Hi-z Hi-z,O(L) I b12s
C13 DATA6 DATA6 Hi-z Hi-z,O(L) I b12s
A14 DATA7 DATA7 Hi-z Hi-z,O(L) I b12s
D13 DATA8 DATA8 Hi-z Hi-z,O(L) I b12s
B15 DATA9 DATA9 Hi-z Hi-z,O(L) I b12s
A17 DATA10 DATA10 Hi-z Hi-z,O(L) I b12s
C14 DATA11 DATA11 Hi-z Hi-z,O(L) I b12s
D15 DATA12 DATA12 Hi-z Hi-z,O(L) I b12s
C15 DATA13 DATA13 Hi-z Hi-z,O(L) I b12s
D14 DATA14 DATA14 Hi-z Hi-z,O(L) I b12s
B17 DATA15 DATA15 Hi-z Hi-z,O(L) I b12s
C16 DATA16 DATA16 Hi-z Hi-z,O(L) I b12s
E15 DATA17 DATA17 Hi-z Hi-z,O(L) I b12s
E14 DATA18 DATA18 Hi-z Hi-z,O(L) I b12s
1-11
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
E13 DATA19 DATA19 Hi-z Hi-z,O(L) I b12s
E12 DATA20 DATA20 Hi-z Hi-z,O(L) I b12s
E16 DATA21 DATA21 Hi-z Hi-z,O(L) I b12s
F15 DATA22 DATA22 Hi-z Hi-z,O(L) I b12s
G13 DATA23 DATA23 Hi-z Hi-z,O(L) I b12s
E17 DATA24 DATA24 Hi-z Hi-z,O(L) I b12s
G12 DATA25 DATA25 Hi-z Hi-z,O(L) I b12s
F14 DATA26 DATA26 Hi-z Hi-z,O(L) I b12s
F12 DATA27 DATA27 Hi-z Hi-z,O(L) I b12s
G11 DATA28 DATA28 Hi-z Hi-z,O(L) I b12s
G16 DATA29 DATA29 Hi-z Hi-z,O(L) I b12s
H13 DATA30 DATA30 Hi-z Hi-z,O(L) I b12s
F13 DATA31 DATA31 Hi-z Hi-z,O(L) I b12s
P12 DN0 DN0 – – AI us
N11 DP0 DP0 – – AI us
N12 DN1/PDN0 DN1 –/– – AI us
U14 DP1/PDP0 DP1 –/– – AI us
N17 EINT0/GPF0 GPF0 –/– Hi-z/– I t8
M16 EINT1/GPF1 GPF1 –/– Hi-z/– I t8
L13 EINT2/GPF2 GPF2 –/– Hi-z/– I t8
M15 EINT3/GPF3 GPF3 –/– Hi-z/– I t8
M17 EINT4/GPF4 GPF4 –/– Hi-z/– I t8
L14 EINT5/GPF5 GPF5 –/– Hi-z/– I t8
L15 EINT6/GPF6 GPF6 –/– Hi-z/– I t8
L16 EINT7/GPF7 GPF7 –/– Hi-z/– I t8
N9 EINT8/GPG0 GPG0 –/– Hi-z/– I t8
T9 EINT9/GPG1 GPG1 –/– Hi-z/– I t8
J10 EINT10/nSS0/GPG2 GPG2 –/–/– Hi-z/Hi-z/– I t8
R10 EINT11/nSS1/GPG3 GPG3 –/–/– Hi-z/Hi-z/– I t8
P11 EINT12/LCD_PWREN/GPG4 GPG4 –/–/– Hi-z/O(L)/– I t8
K10 EINT13/SPIMISO1/GPG5 GPG5 –/–/– Hi-z/Hi-z/– I t8
R11 EINT14/SPIMOSI1/GPG6 GPG6 –/–/– Hi-z/Hi-z/– I t8
L10 EINT15/SPICLK1/GPG7 GPG7 –/–/– Hi-z/Hi-z/– I t8
1-12
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
T10 EINT16/GPG8 GPG8 –/– Hi-z/– I t8
M11 EINT17/nRTS1/GPG9 GPG9 –/–/– Hi-z/O(H)/– I t8
N10 EINT18/nCTS1/GPG10 GPG10 –/–/– Hi-z/Hi-z/– I t8
U12 EINT19/TCLK1/GPG11 GPG11 –/–/– Hi-z/Hi-z/– I t12
M10 EINT20/GPG12 GPG12 –/– Hi-z/– I t12
T11 EINT21/GPG13 GPG13 –/– Hi-z/– I t12
L11 EINT22/GPG14 GPG14 –/– Hi-z/– I t12
U13 EINT23/GPG15 GPG15 –/– Hi-z/– I t12
H12 EXTCLK EXTCLK – – AI is
P17 UPLLCAP UPLLCAP – – AI r50
N14 MPLLCAP MPLLCAP – – AI r50
H14 nBATT_FLT nBATT_FLT – – I is
D4 nBE0 nBE0 Hi-z Hi-z,O(H) O(H) t10s
B5 nBE1 nBE1 Hi-z Hi-z,O(H) O(H) t10s
D5 nBE2 nBE2 Hi-z Hi-z,O(H) O(H) t10s
E5 nBE3 nBE3 Hi-z Hi-z,O(H) O(H) t10s
R12 NCON NCON – – I is
G6 FRnB FRnB – Hi-z,O(L) I d2s
F3 nFWE/GPA19 GPA19 O(H)/– Hi-z,O(H)/– O(H) t10s
E1 nFRE/GPA20 GPA20 O(H)/– Hi-z,O(H)/– O(H) t10s
F4 nFCE/GPA22 GPA21 O(H)/– Hi-z,O(H)/– O(H) t10s
F5 CLE/GPA17 GPA17 O(L)/– Hi-z,O(L)/– O(L) t10s
D1 ALE/GPA18 GPA18 O(L)/– Hi-z,O(L)/– O(L) t10s
N13 nRSTOUT/GPA21 GPA21 –/– O(L)/– O(L) b8
C5 nOE nOE Hi-z Hi-z,O(H) O(H) t10s
H16 nRESET nRESET – – I is
F6 nGCS0 nGCS0 Hi-z Hi-z,O(H) O(H) t10s
B2 nGCS1/GPA12 GPA12 Hi-z/– Hi-z,O(H)/– O(H) t10s
C3 nGCS2/GPA13 GPA13 Hi-z/– Hi-z,O(H)/– O(H) t10s
C4 nGCS3/GPA14 GPA14 Hi-z/– Hi-z,O(H)/– O(H) t10s
D3 nGCS4/GPA15 GPA15 Hi-z/– Hi-z,O(H)/– O(H) t10s
C2 nGCS5/GPA16 GPA16 Hi-z/– Hi-z,O(H)/– O(H) t10s
D2 nGCS6 nGCS6 Hi-z Hi-z,O(H) O(H) t10s
1-13
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
E3 nGCS7 nGCS7 Hi-z Hi-z,O(H) O(H) t10s
D6 nSCAS nSCAS Hi-z Hi-z,O(H) O(H) t10s
C6 nSRAS nSRAS Hi-z Hi-z,O(H) O(H) t10s
H15 nTRST nTRST I – I is
E4 nWAIT nWAIT – Hi-z,O(L) I d2s
E6 nWE nWE Hi-z Hi-z,O(H) O(H) t10s
J6 TOUT0/GPB0 GPB0 –/– O(L)/– I t8
J5 TOUT1/GPB1 GPB1 –/– O(L)/– I t8
J7 TOUT2/GPB2 GPB2 –/– O(L)/– I t8
K3 TOUT3/GPB3 GPB3 –/– O(L)/– I t8
K4 TCLK0/GPB4 GPB4 –/– –/– I t8
K2 nXBACK/GPB5 GPB5 –/– O(H)/– I t8
L5 nXBREQ/GPB6 GPB6 –/– –/– I t8
K7 nXDACK1/GPB7 GPB7 –/– O(H)/– I t8
K5 nXDREQ1/GPB8 GPB8 –/– –/– I t8
L3 nXDACK0/GPB9 GPB9 –/– O(H)/– I t8
K6 nXDREQ0/GPB10 GPB10 –/– –/– I t8
T15 OM0 OM0 – – I is
R13 OM1 OM1 – – I is
P13 OM2 OM2 – – I is
T13 OM3 OM3 – – I is
J12 PWREN PWREN O(H) O(L) O(H) b8
K11 nCTS0/GPH0 GPH0 –/– –/– I t8
L17 nRTS0/GPH1 GPH1 –/– O(H)/– I t8
K13 TXD0/GPH2 GPH2 –/– O(H)/– I t8
K14 RXD0/GPH3 GPH3 –/– –/– I t8
K16 TXD1/GPH4 GPH4 –/– O(H)/– I t8
K17 RXD1/GPH5 GPH5 –/– –/– I t8
J11 TXD2/nRTS1/GPH6 GPH6 –/–/– O(H)/O(H)/– I t8
J15 RXD2/nCTS1/GPH7 GPH7 –/–/– Hi-z/Hi-z/– I t8
K15 UEXTCLK/GPH8 GPH8 –/– Hi-z/– I t8
R9 CLKOUT0/GPH9 GPH9 –/– O(L)/– I t12
P10 CLKOUT1/GPH10 GPH10 –/– O(L)/– I t12
1-14
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
A2 SCKE SCKE Hi-z O(L) O(H) t10s
B4 SCLK0 SCLK0 Hi-z O(L) O(SCLK) t12s
B3 SCLK1 SCLK1 Hi-z O(L) O(SCLK) t12s
P7 I2SLRCK/AC_SYNC GPE0 –/– Hi-z/– I t8
R7 I2SSCLK/AC_BIT_CLK GPE1 –/– Hi-z/– I t8
T7 CDCLK/AC_nRESET GPE2 –/– Hi-z/– I t8
L8 I2SSDI/AC_SDATA_IN GPE3 –/–/– Hi-z/Hi-z/– I t8
U6 I2SSDO/AC_SDATA_OUT GPE4 –/–/– O(L)/Hi-z/– I t8
N8 SDCLK/GPE5 GPE5 –/– O(L)/– I t8
K8 SDCMD/GPE6 GPE6 –/– Hi-z/– I t8
R8 SDDAT0/GPE7 GPE7 –/– Hi-z/– I t8
M8 SDDAT1/GPE8 GPE8 –/– Hi-z/– I t8
P8 SDDAT2/GPE9 GPE9 –/– Hi-z/– I t8
J9 SDDAT3/GPE10 GPE10 –/– Hi-z/– I t8
K9 SPIMISO0/GPE11 GPE11 –/– Hi-z/– I t8
P9 SPIMOSI0/GPE12 GPE12 –/– Hi-z/– I t8
L9 SPICLK0/GPE13 GPE13 –/– Hi-z/– I t8
U8 IICSCL/GPE14 GPE14 –/– Hi-z/– I d8
M9 IICSDA/GPE15 GPE15 –/– Hi-z/– I d8
J13 TCK TCK I – I is
H17 TDI TDI I – I is
J16 TDO TDO O O O ot
J14 TMS TMS I – I is
L1 LEND/GPC0 GPC0 –/– O(L)/– I t8
L4 VCLK/GPC1 GPC1 –/– O(L)/– I t8
M1 VLINE/GPC2 GPC2 –/– O(L)/– I t8
L7 VFRAME/GPC3 GPC3 –/– O(L)/– I t8
M4 VM/GPC4 GPC4 –/– O(L)/– I t8
M3 LCD_LPCOE/GPC5 GPC5 –/– O(L)/– I t8
M2 LCD_LPCREV/GPC6 GPC6 –/– O(L)/– I t8
P1 LCD_LPCREVB/GPC7 GPC7 –/– O(L)/– I t8
N2 VD0/GPC8 GPC8 –/– O(L)/– I t8
L6 VD1/GPC9 GPC9 –/– O(L)/– I t8
1-15
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
N4 VD2/GPC10 GPC10 –/– O(L)/– I t8
R1 VD3/GPC11 GPC11 –/– O(L)/– I t8
N3 VD4/GPC12 GPC12 –/– O(L)/– I t8
P2 VD5/GPC13 GPC13 –/– O(L)/– I t8
M6 VD6/GPC14 GPC14 –/– O(L)/– I t8
P3 VD7/GPC15 GPC15 –/– O(L)/– I t8
R2 VD8/GPD0 GPD0 –/– O(L)/– I t8
M5 VD9/GPD1 GPD1 –/– O(L)/– I t8
N5 VD10/GPD2 GPD2 –/– O(L)/– I t8
R3 VD11/GPD3 GPD3 –/– O(L)/– I t8
P4 VD12/GPD4 GPD4 –/– O(L)/– I t8
R4 VD13/ GPD5 GPD5 –/–/– O(L)/O/– I t8
P5 VD14/GPD6 GPD6 –/–/– O(L)/O/– I t8
N6 VD15/GPD7 GPD7 –/–/– O(L)/O/– I t8
M7 VD16/SPIMISO1/GPD8 GPD8 –/–/– O(L)/Hi-z/– I t8
T4 VD17/SPIMOSI1/GPD9 GPD9 –/–/– O(L)/Hi-z/– I t8
R5 VD18/SPICLK1/GPD10 GPD10 –/–/– O(L)/Hi-z/– I t8
T5 VD19//GPD11 GPD11 –/–/– O(L)/Hi-z/– I t8
P6 VD20/ GPD12 GPD12 –/–/– O(L)/Hi-z/– I t8
R6 VD21/ GPD13 GPD13 –/–/– O(L)/Hi-z/– I t8
N7 VD22/nSS1/GPD14 GPD14 –/–/– O(L)/Hi-z/– I t8
U5 VD23/nSS0/GPD15 GPD15 –/–/– O(L)/Hi-z/– I t8
U16 Vref Vref – – AI ia
G14 XTIpll XTIpll – – AI m26
M14 Xtirtc Xtirtc – – AI nc
G15 XTOpll XTOpll – – AO m26
L12 Xtortc Xtortc – – AO nc
N15 VDD_RTC VDD_RTC P P P drtc
P14 VDDA_ADC VDDA_ADC P P P d33th
N16 VDDA_MPLL VDDA_MPLL P P P d12t
M13 VDDA_UPLL VDDA_UPLL P P P d12t
G4 VDDalive VDDalive P P P d12i
J17 VDDalive VDDalive P P P d12i
1-16
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
A1 VDDi VDDi P P P d12c
A10 VDDi VDDi P P P d12c
A16 VDDi VDDi P P P d12c
A6 VDDi VDDi P P P d12c
B11 VDDi VDDi P P P d12c
F1 VDDi VDDi P P P d12c
F16 VDDi VDDi P P P d12c
U11 VDDi VDDi P P P d12c
L2 VDDiarm VDDiarm P P P d12c
T6 VDDiarm VDDiarm P P P d12c
T8 VDDiarm VDDiarm P P P d12c
U1 VDDiarm VDDiarm P P P d12c
J2 VDDiarm VDDiarm P P P d12c
U2 VDDiarm VDDiarm P P P d12c
A9 VDDMOP VDDMOP P P P d33o
B12 VDDMOP VDDMOP P P P d33o
B14 VDDMOP VDDMOP P P P d33o
B16 VDDMOP VDDMOP P P P d33o
B6 VDDMOP VDDMOP P P P d33o
C1 VDDMOP VDDMOP P P P d33o
F17 VDDMOP VDDMOP P P P d33o
J1 VDDOP VDDOP P P P d33o
T12 VDDOP VDDOP P P P d33o
T3 VDDOP VDDOP P P P d33o
K12 VDDOP VDDOP P P P d33o
T14 VSSA_ADC VSSA_ADC P P P sth
R17 VSSA_MPLL VSSA_MPLL P P P st
M12 VSSA_UPLL VSSA_UPLL P P P st
A12 VSSi VSSi P P P si
A3 VSSi VSSi P P P si
A4 VSSi VSSi P P P si
B10 VSSi VSSi P P P si
C17 VSSi VSSi P P P si
1-17
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9 of 9)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O Type
F2 VSSi VSSi P P P si
G17 VSSi VSSi P P P si
H1 VSSiarm VSSiarm P P P si
K1 VSSiarm VSSiarm P P P si
T1 VSSiarm VSSiarm P P P si
T2 VSSiarm VSSiarm P P P si
U10 VSSiarm VSSiarm P P P si
U4 VSSiarm VSSiarm P P P si
U7 VSSiarm VSSiarm P P P si
A11 VSSMOP VSSMOP P P P so
A15 VSSMOP VSSMOP P P P so
A5 VSSMOP VSSMOP P P P so
A7 VSSMOP VSSMOP P P P so
B1 VSSMOP VSSMOP P P P so
B13 VSSMOP VSSMOP P P P so
D16 VSSMOP VSSMOP P P P so
D17 VSSMOP VSSMOP P P P so
E2 VSSMOP VSSMOP P P P so
G1 VSSOP VSSOP P P P so
N1 VSSOP VSSOP P P P so
U15 VSSOP VSSOP P P P so
U3 VSSOP VSSOP P P P so
U9 VSSOP VSSOP P P P so
H11 VSSOP VSSOP P P P so
1-18
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
NOTE:
1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.
2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.
3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.
4. AI/AO means analog input/analog output.
5. P, I, and O mean power, input and output respectively.
6. The I/O state @nRESET shows the pin status in the @nRESET duration below.
@nRESET4 OSCin
nRESET
FCLK
1-19
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS.
Input (I)/Output (O) Type Descriptions
d12i(vdd12ih) 1.2V Vdd for alive power
d12c(vdd12ih_core), si(vssih) 1.2V Vdd/Vss for internal logic
d33o(vdd33oph), so(vssoph) 3.3V Vdd/Vss for external logic
d33th(vdd33th_abb)
,sth(vssbbh_abb)
3.3V Vdd/Vss for analog circuitry
d12t(vdd12t_abb), st(vssbb_abb) 1.2V Vdd/Vss for analog circuitry
drtc(vdd30th_rtc) 3.0V Vdd for RTC power
t8(phbsu100ct8sm)
Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io=8mA
is(phis) Input pad, LVCMOS schmitt-trigger level
us(pbusb0) USB pad
t10(phtot10cd) 5V tolerant Output pad, Tri-state .
ot(phot8) Output pad, tri-state, Io=8mA
b8(phob8) Output pad, Io=8mA
t16(phot16sm) Output pad, tri-state, medium slew rate, Io=16mA
r10(phiar10_abb) Analog input pad with 10-ohm resistor
ia(phia_abb) Analog input pad
gp(phgpad_option) Pad for analog pin
m26(phsoscm26_2440a) Oscillator cell with enable and feedback resistor
t12(phbsu100ct12sm)
Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io=12mA
d8(phbsd8sm) Bi-directional pad, LVCMOS schmitt-trigger, Open Drain, Io=8mA
t10s(phtot10cd_10_2440a)
b12s(phtbsu100ct12cd_12_2440a)
d2s(phtbsd2_2440a)
output pad, LVCMOS , tri -state, output drive strenth control,
Io=4,6,8,10mA
Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up
resistor with control, tri -state,output drive strenth control, Io=6,8,10,12mA
Bi-directional pad, LVCMOS schmitt-trigger, open-drain, output
drive strenth ignore,
r50(phoar50_abb) Analog Output pad, 50Kohm resistor, Separated bulk-bias
t12s(phtot12cd_12_2440a)
output pad, LVCMOS , tri -state, output drive strenth control,
Io=6,8,10,12mA
nc(phnc) No connection pad
1-20
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
SIGNAL DESCRIPTIONS
Table 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6)
Signal Input/Output Descriptions
Bus Controller
OM[1:0] I OM[1:0] sets S3C2440A in the TEST mode, which is used only at fabrication.
Also, it determines the bus width of nGCS0. The pull-up/down resistor
determines the logic level during RESET cycle.
00:Nand-boot 01:16-bit 10:32-bit 11:Test mode
ADDR[26:0] O ADDR[26:0] (Address Bus) outputs the memory address of the corresponding
bank .
DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16/32-bit.
nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is
within the address region of each bank. The number of access cycles and the
bank size can be programmed.
nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle.
nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the
local bus. BACK active indicates that bus control has been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2440A has surrendered
control of the local bus to another bus master.
nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the
current bus cycle cannot be completed.
SDRAM/SRAM
nSRAS O SDRAM Row Address Strobe
nSCAS O SDRAM Column Address Strobe
nSCS[1:0] O SDRAM Chip Select
DQM[3:0] O SDRAM Data Mask
SCLK[1:0] O SDRAM Clock
SCKE O SDRAM Clock Enable
nBE[3:0] O Upper Byte/Lower Byte Enable(In case of 16-bit SRAM)
nWBE[3:0] O Write Byte Enable
NAND Flash
CLE O Command Latch Enable
ALE O Address Latch Enable
nFCE O Nand Flash Chip Enable
nFRE O Nand Flash Read Enable
nFWE O Nand Flash Write Enable
NCON I Nand Flash Configuration
FRnB I Nand Flash Ready/Busy
* If NAND flash controller isn’t used, it has
to be pull-up. (3.3V)
1-21
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-3. S3C2440A Signal Descriptions (Sheet 2 of 6)
Signal Input/Output Descriptions
LCD Control Unit
VD[23:0] O
LCD_PWREN O
VCLK O
VFRAME O
VLINE O
VM O
VSYNC O
HSYNC O
VDEN O
LEND O
STV O
CPV O
LCD_HCLK O
TP O
STH O
LCD_LPCOE O
LCD_LPCREV O
LCD_LPCREVB O
STN/TFT/SEC TFT: LCD Data Bus
STN/TFT/SEC TFT: LCD panel power enable control signal
STN/TFT: LCD clock signal
STN: LCD Frame signal
STN: LCD line signal
STN: VM alternates the polarity of the row and column voltage
TFT: Vertical synchronous signal
TFT: Horizontal synchronous signal
TFT: Data enable signal
TFT: Line End signal
SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TF T: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TF T: Timing control signal for specific TFT LCD
SEC TF T: Timing control signal for specific TFT LCD
SEC TF T: Timing control signal for specific TFT LCD
CAMERA Interface
CAMRESET O Software Reset to the Camera
CAMCLKOUT O Master Clock to the Camera
CAMPCLK I Pixel clock from Camera
CAMHREF I Horizontal sync signal from Camera
CAMVSYNC I Vertical sync signal from Camera
CAMDATA[7:0] I Pixel data for YCbCr
Interrupt Control Unit
EINT[23:0] I External Interrupt request
DMA
nXDREQ[1:0] I External DMA request
nXDACK[1:0] O External DMA acknowledge
1-22
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6)
Signal Input/Output Descriptions
UART
RxD[2:0] I UART receives data input
TxD[2:0] O UART transmits data output
nCTS[1:0] I UART clear to send input signal
nRTS[1:0] O UART request to send output signal
UEXTCLK I External clock input for UART
ADC
AIN[7:0] AI ADC input[7:0]. If it isn’t used pin, it has to be Low (Ground).
Vref AI ADC Vref
IIC-Bus
IICSDA IO IIC-bus data
IICSCL IO IIC-bus clock
IIS-Bus
I2SLRCK IO IIS-bus channel select clock
I2SSDO O IIS-bus serial data output
I2SSDI I IIS-bus serial data input
I2SSCLK IO IIS-bus serial clock
CDCLK O CODEC system clock
AC’97
AC_SYNC
AC_BIT_CLK
AC_nRESET
AC_SDATA_IN
AC_SDATA_OUT
O 48 kHz fixed rate sample sync
IO 12.288 MHz serial data clock
O AC’97 Master H/W Reset
I Serial, time division multiplexed, AC’97 input stream
O Serial, time division multiplexed, AC’97 output stream
Touch Screen
nXPON O Plus X-axis on-off control signal
XMON O Minus X-axis on-off control signal
nYPON O Plus Y-axis on-off control signal
YMON O Minus Y-axis on-off control signal
USB Host
DN[1:0] IO DATA(–) from USB host. (Need to 15K ohm pull-down)
DP[1:0] IO DATA(+) from USB host. (Need to 15K ohm pull-down)
USB Device
PDN0 IO DATA(–) for USB peripheral.
(Need to 470K ohm pull-down for power consumption in sleep mode)
PDP0 IO DATA(+) for USB peripheral. (Need to 1.5K ohm pull-up)
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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6)
Signal Input/Output Description
SPI
SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPICLK[1:0] IO SPI clock
nSS[1:0] I SPI chip select(only for slave mode)
SD
SDDAT[3:0] IO SD receive/transmit data
SDCMD IO SD receive response/ transmit command
SDCLK O SD clock
General Port
GPn[129:0] IO General input/output ports (some ports are output only)
TIMMER/PWM
TOUT[3:0] O Timer output[3:0]
TCLK[1:0] I External timer clock input
JTAG TEST LOGIC
nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger(black ICE) is not used, nTRST pin must be issued by a low active
pulse(Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP
controller's states. A 10K pull-up resistor has to be connected to TMS pin.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
A 10K pull-up resistor must be connected to TCK pin.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.
A 10K pull-up resistor must be connected to TDI pin.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and
data.
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S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6)
Signal Input/Output Description
Reset, Clock & Power
XTOpll AO Crystal Output for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, it has to be a floating pin.
MPLLCAP AI Loop filter capacitor for main clock.
UPLLCAP AI Loop filter capacitor for USB clock.
XTIrtc AI 32 kHz crystal input for RTC. If it isn’t used, it has to be High (3.3V).
XTOrtc AO 32 kHz crystal output for RTC. If it isn’t used, it has to be Float.
CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock
output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
nRESET ST nRESET suspends any operation in progress and places S3C2440A into a
known reset state. For a reset, nRESET must be held to L level for at least 4
OSCin after the processor power has been stabilized.
nRSTOUT O For external device reset control(nRSTOUT = nRESET & nWDTRST &
SW_RESET)
PWREN O 1.2V/1.3V core power on-off control signal
nBATT_FLT I Probe for battery state(Does not wake up at Sleep mode in case of low battery
state). If it isn’t used, it has to be High (3.3V).
OM[3:2] I OM[3:2] determines how the clock is made.
OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.
OM[3:2] = 01b, Crystal is used for MPLL CLK source
and EXTCLK is used for UPLL CLK source.
OM[3:2] = 10b, EXTCLK is used for MPLL CLK source
and Crystal is used for UPLL CLK source.
OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
EXTCLK I External clock source.
When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only.
When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only.
If it isn't used, it has to be High (3.3V).
XTIpll AI Crystal Input for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, XTIpll has to be High (3.3V).
1-25
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6)
Signal Input/Output Description
Power
VDDalive P S3C2440A reset block and port status register VDD.
It should be always supplied whether in normal mode or in Sleep mode.
VDDiarm P S3C2440A core logic VDD for ARM core.
VDDi P S3C2440A core logic VDD for Internal block.
VSSi/VSSiarm P S3C2440A core logic VSS
VDDi_MPLL P S3C2440A MPLL analog and digital VDD.
VSSi_MPLL P S3C2440A MPLL analog and digital VSS.
VDDOP P S3C2440A I/O port VDD(3.3V)
VDDMOP P S3C2440A Memory I/O VDD
3.3V : SCLK up to 135MHz
2.5V : SCLK up to 135MHz
1.8V : SCLK up to 93MHz
VSSOP P S3C2440A I/O port VSS
RTCVDD P RTC VDD (3.0V, Input range: 1.8 ~ 3.6V)
This pin must be connected to power properly if RTC isn't used.
VDDi_UPLL P S3C2440A UPLL analog and digital VDD
VSSi_UPLL P S3C2440A UPLL analog and digital VSS
VDDA_ADC P S3C2440A ADC VDD(3.3V)
VSSA_ADC P S3C2440A ADC VSS
NOTE:
1. I/O means Input/Output.
2. AI/AO means analog input/analog output.
3. ST means schmitt-trigger.
4. P means power.
1-26
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
S3C2440A SPECIAL REGISTERS
Table 1-4. S3C2440A Special Registers (Sheet 1 of 14)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
Memory Controller
BWSCON 0x48000000
←
W R/W Bus Width & Wait Status Control
BANKCON0 0x48000004 Boot ROM Control
BANKCON1 0x48000008 BANK1 Control
BANKCON2 0x4800000C BANK2 Control
BANKCON3 0x48000010 BANK3 Control
BANKCON4 0x48000014 BANK4 Control
BANKCON5 0x48000018 BANK5 Control
BANKCON6 0x4800001C BANK6 Control
BANKCON7 0x48000020 BANK7 Control
REFRESH 0x48000024 DRAM/SDRAM Refresh Control
BANKSIZE 0x48000028 Flexible Bank Size
MRSRB6 0x4800002C Mode register set for SDRAM BANK6
MRSRB7 0x48000030 Mode register set for SDRAM BANK7
1-27
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
Table 1-4. S3C2440A Special Registers (Sheet 2 of 14)
Register Name Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
USB Host Controller
HcRevision 0x49000000
HcControl 0x49000004
HcCommonStatus 0x49000008
←
W Control and Status Group
HcInterruptStatus 0x4900000C
HcInterruptEnable 0x49000010
HcInterruptDisable 0x49000014
HcHCCA 0x49000018 Memory Pointer Group
HcPeriodCuttentED 0x4900001C
HcControlHeadED 0x49000020
HcControlCurrentED 0x49000024
HcBulkHeadED 0x49000028
HcBulkCurrentED 0x4900002C
HcDoneHead 0x49000030
HcRmInterval 0x49000034 Frame Counter Group
HcFmRemaining 0x49000038
HcFmNumber 0x4900003C
HcPeriodicStart 0x49000040
HcLSThreshold 0x49000044
HcRhDescriptorA 0x49000048 Root Hub Group
HcRhDescriptorB 0x4900004C
HcRhStatus 0x49000050
HcRhPortStatus1 0x49000054
HcRhPortStatus2 0x49000058
Interrupt Controller
SRCPND 0X4A000000 ← W R/W Interrupt Request Status
INTMOD 0X4A000004 W Interrupt Mode Control
INTMSK 0X4A000008 R/W Interrupt Mask Control
PRIORITY 0X4A00000C W IRQ Priority Control
INTPND 0X4A000010 R/W Interrupt Request Status
INTOFFSET 0X4A000014 R Interrupt request source offset
SUBSRCPND 0X4A000018 R/W Sub source pending
INTSUBMSK 0X4A00001C R/W Interrupt sub mask
1-28
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-4. S3C2440A Special Registers (Sheet 3 of 14)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
DMA
DISRC0 0x4B000000
DISRCC0 0x4B000004
DIDST0 0x4B000008
DIDSTC0 0x4B00000C
DCON0 0x4B000010
DSTAT0 0x4B000014
DCSRC0 0x4B000018
DCDST0 0x4B00001C
DMASKTRIG0 0x4B000020
DISRC1 0x4B000040
DISRCC1 0x4B000044
DIDST1 0x4B000048
DIDSTC1 0x4B00004C
DCON1 0x4B000050
DSTAT1 0x4B000054
DCSRC1 0x4B000058
DCDST1 0x4B00005C
DMASKTRIG1 0x4B000060
DISRC2 0x4B000080
DISRCC2 0x4B000084
DIDST2 0x4B000088
DIDSTC2 0x4B00008C
DCON2 0x4B000090
DSTAT2 0x4B000094
DCSRC2 0x4B000098
DCDST2 0x4B00009C
DMASKTRIG2 0x4B0000A0
DISRC3 0x4B0000C0
DISRCC3 0x4B0000C4
DIDST3 0x4B0000C8
DIDSTC3 0x4B0000CC
DCON3 0x4B0000D0
DSTAT3 0x4B0000D4
DCSRC3 0x4B0000D8
DCDST3 0x4B0000DC
DMASKTRIG3 0x4B0000E0
←
←
Acc.
Unit
Read/
Write
Function
W R/W DMA 0 Initial Source
DMA 0 Initial Source Control
DMA 0 Initial Destination
DMA 0 Initial Destination Control
DMA 0 Control
R DMA 0 Count
DMA 0 Current Source
DMA 0 Current Destination
R/W DMA 0 Mask Trigger
DMA 1 Initial Source
DMA 1 Initial Source Control
DMA 1 Initial Destination
DMA 1 Initial Destination Control
DMA 1 Control
R DMA 1 Count
DMA 1 Current Source
DMA 1 Current Destination
R/W DMA 1 Mask Trigger
DMA 2 Initial Source
DMA 2 Initial Source Control
DMA 2 Initial Destination
DMA 2 Initial Destination Control
DMA 2 Control
R DMA 2 Count
DMA 2 Current Source
DMA 2 Current Destination
R/W DMA 2 Mask Trigger
W R/W DMA 3 Initial Source
DMA 3 Initial Source Control
DMA 3 Initial Destination
DMA 3 Initial Destination Control
DMA 3 Control
R DMA 3 Count
DMA 3 Current Source
DMA 3 Current Destination
R/W DMA 3 Mask Trigger
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