Samsung Bremen-L3, NP-E352, NP-R528, NP-R530, NP-R728 Schematic
...
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
8-1
D
D
Bremen-L3
CPU :
Chip Set :
C
Remarks :
Model Name : Bremen-L3
PBA Name :
PCB Code :
B
Dev. Step : PV
Revision :
T.R. Date :
Design CHECK
Intel Penryn
Intel Cantiga & ICH9M
Montevina Platform
MAIN
GCE : BA41-01226A
NY : BA41-01227A
HST : BA41-01228A
1.0
2009.10.27
APPROVAL
C
B
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
A A
Signature :
X
3
4
Owner :
SEC Mobile R & D
DRAW
CHECK
APPROVAL
MODULE CODE
2
Jun PARK
YM.AHN
HJ.KIM
DATE
DEV. STEP
REV
LAST EDIT
10/10/2008
TITLE
PV
1.0
Bremen-L3
MAIN
COVER
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
PART NO.
8. Block Diagram and Schematic
SAMSUNG
ELECTRONICS
BA41-xxxxxA
OFPAGE
591
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
4 3
LED LCD
17.3" HD+ / 15.6"
Page 36
CRT
Page 37
CLOCK
CK-505M
Page 12
LVDS(15" Single, 17" Dual)
FAN
Page 8
CPU
Thermistor
EMC2112
Page 8
Intel Pentium
Intel Core2Duo
Page 9~11
FSB ~1067MHz
External -
Cantiga-PM45
Cantiga-GM45
Channel A (Reverse)
Dual channel
Channel B (Reverse)
BREMEN-L
BLOCK DIAGRAM
DDR II 800
DDR2-SODIMM x 2
Page 18~19
12
R530/R730
D
C
0.3M
Page 35
Page 42
P 2
P 4, 6
P 5
P 8(17")
P 9(15")
USB 2.0
P 4
Single USB Port
Dual USB Port
ANT
Bluetooth
TBD
B
3-in-1
CARDREADER
ALCOR AU6336
SPI ROM
16Mbit
ALC269
Page 39~40
A
4 3
L R
Internal -
Cantiga-GL40
Page 13~17
ICH9-M
RTC
Page 30~34
MEC1308
High Definition
BREMEN-UL
MICOM
Page 45
Space bar
KEYBOARD
Page 46
SATA
PCIe
10/100 LAN
Controller
RTL8040
Transformer
TOUCHPAD
PEX4
SENTELIC
For 17"
For 15"
SATA0
2.5" HDD
SATA1
FFC
PEX1
DRAW
CHECK
APPROVAL
MODULE CODE LAST EDIT
2
Page 44
12.7mm ODD
WLAN
( Half Type)
Page 43
RJ45
Page 41
nVidia
N11M-GE
Page 20~24
Page 44
DATE
Jun PARK
DEV. STEP
YM.AHN
REV
HJ.KIM
undefined
9/23/2008
TITLE
PV
1.0
gDDR3
Page 25~28
Bremen-L3
MAIN
BLOCK DIAGRAM
October 27, 2009 14:27:43 PM
SAMSUNG
ELECTRONICS
PART NO.
BA41-xxxxxA
PAGE
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
592
OF
C
B
A
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
8-2
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
BOARD INFORMATION
8-3
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
I C / SMB Address
suBxeHsserddAseciveD
Clock, Unused Clock Output DisableD2hCK-505M (Clock Generator) 1101 001X
-A0hSODIMM0
Port Number ASSIGNED TO
6
7
8
9
10
11
USB PORT (RIGHT, SUB)
CAMERA(17")
CAMERA(15")
UHCI_3
UHCI_4
UHCI_5
MICOM
EMC2102 7Ah0111 101X
C
USB PORT Assignation
Port Number ASSIGNED TO
UHCI_0
UHCI_1
UHCI_2
1
2
3
5
1010 000X
Master
USB PORT (RIGHT, SUB)0
USB PORT (LEFT)
CARD READER(AU6336)4
BLUETOOTH(TBD)
retsaMM9HCI SMBUS Master
A4hX100 01011MMIDOS
16hX110 1000YRETTAB
SATA Assignation
Port Number ASSIGNED TO
HDDSATA0 SATA1
-SATA2 SATA3 -
B
Port Number ASSIGNED TO
ODD
PCI EXPRESS Assignation
Port Number
ASSIGNED TO
WLANPCIe1 PCIe2
-PCIe3 PCIe4 -
Port Number ASSIGNED TO
Wired LAN
Voltage Rails
Power Rail Descriptions
VDC_ADPT
VDC
PRTC_BAT 3.3V supply for the RTC well.
P5.0V_ALW 5.0V always power well
P12.0V_ALW 12.0V always power well
P1.7V_VREF Power Chip Reference
P2.0V_VREF Power Chip Reference
P5.0V_VREF_FILT Power Chip Reference
P3.3V_MICOM
LCD_VDD3V
KBC3_CHG4.2V
P1.2V_LAN
P2.5V_LAN
P3.3V_MCD 3.3V (3-in-1 Socket)
Primary DC system power supply (9 to 19V)
Charger Reference Voltage SourceVDC_CHG
Output voltage of RT8205AGQW
(if VDC is removed, it will be off)
3.3V (LED LCD)
To charge battery
Internal Regulator’s Power of LAN Controller
Power Rail Descriptions
P1.05V_PEG P1.05V (Direct Media Interface Compensation)
P5.0V
P3.3V
P1.05
P0.9V DDR2 Termination
P5.0V_AUX
P3.3V_AUX
P1.8_AUX 1.8V Power Rail (off in S4-S5)
CPU_CORE
P5.0V_STB
EGFX_CORE nVidia Graphic Chip power
P1.5V
P1.5_AUX
P1.8V
5.0V Power Rail (off in S3-S5)
3.3V Power Rail (off in S3-S5)
1.05V Power Rail (off in S3-S5)
5.0V Power Rail (off in S4-S5)
3.3V Power Rail (off in S4-S5)
Core Voltage for CPU
5.0V supply for AudioAUD_P5V
Auido Analog VoltageP4.75V_AUD
To charge USB device at sleep status
5.0V supply at SUB_ODD BoardP5.0V_ODD
1.5V Power Rail (off in S3-S5)
1.5V Power Rail (off in S4-S5)
1.8V Power Rail (off in S3-S5)
Power source of External
D
C
B
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
Crystal / Oscillator
TYPE PREQUENCY
A
Crystal MICOM
32.768KHzCrystal ICH9-M
10MHz
14.318MHzCrystal CLOCK-Generator
25MHzCrystal LAN
4
EGASUECIVED
8. Block Diagram and Schematic
REVISION HISTORY
See rev notes for more information.
A
OF
R530/R730
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
MAIN
BOARD INFO
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
3 59
PAGE
ELECTRONICS
BA41-xxxxxA
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
POWER DIAGRAM
R530/R730
D
C
B
AC ADAPTER
DC BATTERY
VDC
P12.0V_ALW
RT8205
APW7141
APW7141
TPS51620
SC471
P3.3V_MICOM
MICOM, LEDs
SPI ROM,
P5.0V_STB
KBC3_SUSPWR KBC3_PWRON
(CHP3_S4_STATE*)
P5.0V_ALW
USB, Swithched Power
P5.0V_AUX
GL40
(CHP3_SLPS3*)
P5.0V
P5.0V_AUD
EMC2112
GL40
CRT
HDD
ALC269Q
P3.3V_AUX
ICH9M, LED, Wire LAN, LED LCD
RTL8103EL,
EMC2112
P3.3V
CK505M
GL40
DDR2
ICH9M
P3.3V_MCD
P1.8V_AUX
GL40,
DDR II
P1.8V
P0.9V
P1.5V
P1.05V
CPU_CORE
EGFX_CORE
N11M-GE
DDR II Termination
PENTIUM CPU
CK505M
GL40
ALC269Q
PENTIUM CPU
GL40
ICH9M
PENTIUM CPU
P1.2V_LAN
P2.5V_LAN
N11M-GE
ODD
TOUTCHPAD
CAMERA
FAN
80 PORT
LED LCD
ALC269Q
AU6336
3-in-1 Socket
88E8040
gDDR3
ICH9M
KBC3_VRON
WLAN
LEDs
HDD
MICOM
LID SW
D
C
B
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
S5-S4 S0
A
4
8. Block Diagram and Schematic
S3
A
594
OF
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
MAIN
POWER DIAGRAM
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-xxxxxA
8-4
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
POWER
S/W
6
C
ADAPTER
BATTERY
2-1) P12.0V_ALW
B B
3) P5.0V_ALW
14) KBC3_PWRON
14-1
4
4) P3.3V_MICOM
16) P3.3V
KBC
6) KBC3_PWRSW#
Sheet 45
4) P3.3V_MICOM
VDC_ADPT /
VDC_CHG
BQ24751
2
2) VDC
P3.3V_AUX & P5V_ALW
3
RT8205
0 OHM
5
5) P5.0V_STB
9) P3.3V_AUX
8) P5.0V_AUX
14) KBC3_PWRON
14-1) KBC3_PWRON_INV#
10) P1.8V_AUX
14) KBC3_PWRON
22) KBC3_CPURST#
11) CHP3_SLPS5#/4#/3#
12) KBC3_RSMRST#
14) KBC3_PWRBTN#
23) KBC3_PWRGD
20) VRM3_CPU_PWRGD
7) KBC3_SUSPWR
** KBC3_USBCHG **
9) P3.3V_AUX
8) P5.0V_AUX
4) P3.3V_MICOM
AO6409L
Sheet 56
AP4435GM
Sheet 56
AO6409L
Sheet 56
22
25) PLT3_RST#
7) KBC3_SUSPWR
14) KBC3_PWRON
(KBC3_VRON)
10) P1.8V_AUX
10 KOHM
MEM1_VREF
10 KOHM
9
8
4
16) P3.3V
15) P5.0V
P1.8V
12
11
13
23
7
7) KBC3_SUSPWR
14) KBC3_PWRON
14) KBC3_PWRON
14) KBC3_PWRON
16
15
(After P1.05V)
3
14
2) VDC
2) VDC
2) VDC
8) P5.0V_AUX
CHP3_DPRSLPVR
CPU1_DPRSTP#
19) VCCP3_PWRGD
GCORE3_PWRGD
14) KBC3_PWRON
34
25) CHP3_SUSSTAT#
25
P1.8V_AUX
APW7141
Sheet 52
P1.5V
APW7141
Sheet 53
P1.5V
APW7141
Sheet 53
P0.9V
APL5336
Sheet 52
2) VDC
TPS51620
Sheet 43
2) VDC
CPU_CORE
Sheet 30~34
10) P1.8V_AUX
17) P1.5V
18) P1.05V
P0.9V
EGFX_CORE
SC471
RTC
Battery
PRTC_BAT
ICH9-M
9) P3.3V_AUX
16) P3.3V
17) P1.5V
18) P1.05V
VRMPWRGD
PWROK
10
17
18
19) CPU_CORE
20) VRM3_CPU_PWRGD
19
20
EGFX_CORE
2
PRTC_BAT
CHP3_RTCRST#
16) P1.5V
21
21) CLK3_PWRGD
24) CPU1_PWRGDCPU
26) PLT3_RST#
20) VRM3_CPU_PWRGD
19) CPU_CORE
23) KBC3_PWRGD
(Between P3.3V & P1.5V)
17) P3.3V
17) P1.5V
18) P1.05V
26) PLT3_RST#
18) P1.05V
10) P1.8V_AUX
17) P1.5V
16) P3.3V
2
1
24
CPU
Sheet 9~11
10) P1.8V_AUX
MEM1_VREF
16) P3.3V
DRAW
CHECK
APPROVAL
MODULE CODE
POWER SEQUENCE
9) P3.3V_AUX
2) VDC
TITLE
PV
1.0
15) P5.0V
4) P3.3V_MICOM
LCD_VDD3V
VDD_LED
16) P3.3V
15) P5.0V
P5.0V_AUD
P4.75V_AUD
17) P1.5V
16) P3.3V
9) P3.3V_AUX
16) P3.3V
16) P3.3V
15) P5.0V
16) P3.3V
15) P5.0V
15) P5.0V
4) P3.3V_MICOM
16) P3.3V
9) P3.3V_AUX
POWER SEQUENCE
October 27, 2009 14:27:43 PM
CK-505M
Sheet 12
26
27) CPU1_CPURST#
PWROK
CL_PWROK
PM45
Sheet 13~17
Jun PARK
undefined
Sheet 18~19
YM.AHN
HJ.KIM
9) P3.3V_AUX
27
DDR2
DATE
DEV. STEP
REV
LAST EDIT
15) P5.0V
P5.0V_AUD
9/23/2008
1
EMC21112
Sheet 8
MX25L
Sheet 35
LED LCD
Sheet 36
CRT
Sheet 37
ALC 269
Sheet 39
88E8040
Sheet 41
AU6336
Sheet 42
WLAN
Sheet 43
ODD
Sheet 44
2.5" HDD
Sheet 44
TOUCHPAD
Sheet 46
LED
Sheet 47
Bremen-L3
MAIN
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
P3.3V_MCD
SAMSUNG
ELECTRONICS
PART NO.
BA41-xxxxxA
OFPAGE
595
8-5
D
C
AA
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
BSEL
2
CLOCK DISTRIBUTION
333/400 MHz
333/400 MHz
333/400 MHz
333/400 MHz
CLK1_MCLK0/0#
CLK1_MCLK1/1#
CLK1_MCLK3/3#
CLK1_MCLK4/4#
MIN3_CLKREQ*#
100 MHz (SRC 6)
667/800 MHz
SODIMM #0
SODIMM #1
CLK1_MINIPCIE/MINIPCIE#
1
WLAN
3
CLK0_HCLK1/HCLK1#
PCI Express Gfx
MCH3_CLKREQ#
CLK1_DREFCLK/DREFCLK#
CLK1_DREFSSCCLK/DREFSSCCLK#
PEG
3HCM/LLPG3HCM_1KLC)4CRS( zHM 001
CPU
FSB
HPLL
MPLL
Cantiga
#LLPG
PCIE PLL
DPLLA
DPLLB
MCH
DMI
P3.3V
4
FS(2:0)
266 MHz CLK0_HCLK/CLK#
1
MUX
Main PLL
SSC
266 MHz
100 MHz (SRC0)
CLK1_DREFSSCLK/DREFSSCLK#
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
CLK3_PWRGD*
ITP_EN
CPU_STP*
MUX
96 MHz
C
SS(96/100) SEL
PLL3
SSC
100 MHz
100 MHz (SRC 6,9)
R530/R730
C
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
CLK1_PCIEICH/PCIEICH#100 MHz (SRC 3)
48MHz PLL
MUX
xSLG8SP513r05)
B
14.318 MHz
CLK3_USB4848 MHz
CHP3_SATACLKREQ#
CLK1_SATA/SATA#100 MHz (SRC 2)
CLK3_PCLKICH33 MHz
CK-505M (w/ CLKREQ* & SSDC)
33 MHz CLK3_PCLKMICOM
KBC
3
10 MHz
14 MHz
OSC
4
33 MHz
Buffer
Page 8
PCI_STP*
A A
14.318 MHz
PCIEPLL
USBPLL
SATAPLL
32.768 KHz
OSC
RTC Clock
32.768 KHz
ICH9-M
AUD3_BCLK
KBC3_SPI_CLK
17.86 MHz
2
HD Audio
DRAW
CHECK
APPROVAL
MODULE CODE
SPI
Jun PARK
YM.AHN
HJ.KIM
undefined
LOM3_CLKREQ*#
CLK1_PCIELOM/PCIELOM#100 MHz (SRC 9)
DATE
9/23/2008
DEV. STEP
PV
REV
1.0
LAST EDIT
TITLE
October 27, 2009 14:27:43 PM
WIRED LAN
Bremen-L3
MAIN
CLOCK DIAGRAM
PART NO.
PAGE
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
8. Block Diagram and Schematic
25 MHz
SAMSUNG
ELECTRONICS
BA41-xxxxxA
OF
B
596
8-6
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
8-7
D
C
THERMAL SENSOR & FAN CONTROL
P3.3V_AUX
R568
10K
1%
C562
10000nF-X5R
6.3V
THM3_VDD_5V_MN THM3_VDD_3V_MN
C559
100nF
10V
R566
nostuff
7-B2
7-B2
0
THM3_SHDN_SEL_MN
THM3_TRIP_SET_MN
R564
1.5K
1%
TRIP_SET 1500 : 95 degree
FAN5_VDD
FAN3_FDBACK#
C564
100nF
10V
P3.3V_AUXP5.0V
R567
49.9
1%
U503
EMC2112-BP-TR
1
VDD_3V
16
VDD_5V_1
19
VDD_5V_2
9
RESET#
17
FAN_1
18
FAN_2
20
TACH
10
ADDR_SEL
6
SHDN_SEL
7
TRIP_SET
SMDATA
SMCLK
ALERT#
SYS_SHDN#
DP3_DN2
DN3_DP2
THERMAL_PAD
1209-001887
SMBUS Address 7Ah
DN1
DP1
CLK
GND
nostuff
nostuff
14
15
12
8
2
3
THM3_THERMDN_MN
4
THM3_THERMDP_MN
5
11
13
21
P3.3V
1%
10K
R549
P3.3V_AUX
nostuff
1%
10K
R550
C566
2.2nF
50V
1%
Check if PU is doubled to Micom Side.
10K
R558
19-D1,44-B3
19-D1,44-B3
31-C3,44-C3
44-D1
9-C4
C565
9-C4
2.2nF
50V
2
MMBT3904
1
Q12
3
1%
10K
R548
Opposite side of CPU.
KBC3_THERM_SMDATA
KBC3_THERM_SMCLK
THM3_ALERT#
THM3_STP#
CPU2_THERMDC
CPU2_THERMDA
3
1
C615
2.2nF
50V
2
Opposite side of GPU.
C1048
1000nF-X5R
6.3V
10mil width and 10mil spacing.
For Intel 45nm(From penryn)
19-D2
0
R578
Q506
MMBT3904
19-D2
0
R579
nostuff
nostuff
nostuff
nostuff
To remove glitch when system is booted up.
GFX3_THERMDN
GFX3_THERMDP
B
P3.3V
C62
10000nF-X5R
6.3V
R43
10K
1%
J2
HDR-4P-1R-SMD
1
2
3
4
5
MNT1
6
MNT2
3711-000456
DESIGN
CHECK
APPROVAL
MODULE CODE
Jun PARK
YM.AHN
HJ.KIM
2
HIGH Z
0
1
SHDN_SEL MODE
INTEL TR MODE
AMD CPU/DIODE MODE
EXT.DIODE 2 MODE
FAN3_FDBACK#
FAN5_VDD
Line Width = 20 mil
7-C3
7-C3
ADDRESSS_SEL MODE
0
HIGH Z
A
1
4
0101 111xb
0111 101xb (7A)
0101 110xb
3
DATE
DEV. STEP
REV
LAST EDIT
M504
HEAD
DIA
LENGTH
BA61-01090A
9/23/2008
TITLE
PV
1.0
M502
HEAD
DIA
LENGTH
BA61-01090A
Bremen-L3
THERMAL SENSOR
THERMAL SENSOR EMC2112
October 27, 2009 14:27:43 PM
M503
HEAD
DIA
LENGTH
BA61-01090A
To support heatsink
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
7 59
PAGE
M505
HEAD
DIA
LENGTH
BA61-01090A
ELECTRONICS
BA41-xxxxxA
D
C
B
A
OF
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4 3
2
1
R530/R730
D
D
P1.05V
R571
CPU1-1
CPU1_A#(16:3)
C
CPU1_ADSTB0#
CPU1_A#(35:17) CPU1_DBI2#
CPU1_ADSTB1#
12-D1
12-C1
12-D1
12-C1
B
PENRYN
1 / 4
3
J4
A3#
4
L5
A4#
5
L4
A5#
6
K5
A6#
7
M3
A7#
8
N2
A8#
9
J1
A9#
10
N3
A10#
11
P5
A11#
12
P2
A12#
13
L2
A13#
14
P4
A14#
15
P1
A15#
16
R1
A16#
M1
ADSTB0#
17
Y2
A17#
18
U5
A18#
19
R3
A19#
20
W6
A20#
21
U4
A21#
22
Y5
A22#
23
U1
A23#
R4
A24#
25
T5
A25#
26
T3
A26#
27
W2
A27#
28
W5
A28#
29
Y4
A29#
30
U2
A30#
31
V4
A31#
32
W3
A32#
33
AA4
A33#
34
AB2
A34#
35
AA3
A35#
V1
ADSTB1#
0143854500|bga_479p_sock
0
ADDR GROUP
CONTROL
1
ICH
ADDR GROUP
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
DBSY#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HITM#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
56
CPU1_IERR#_MN
0
1
2
3
4
12-C1
CPU1_ADS#
12-C1
CPU1_BNR#
12-C1
CPU1_BPRI#
12-C1
CPU1_BREQ#
12-C1
CPU1_DEFER#
12-B1
CPU1_DRDY#
12-B1
CPU1_DBSY#
29-C1
CPU1_INIT#
12-B1
CPU1_LOCK#
12-A1
CPU1_RS0#
12-A1
CPU1_RS1#
12-A1
CPU1_RS2#
12-B1
CPU1_TRDY#
12-B1
CPU1_HIT#
12-B1
CPU1_HITM#
29-C1
CPU1_A20M#
29-C1
CPU1_FERR#
29-C1
CPU1_IGNNE#
29-B1
CPU1_STPCLK#
29-B1
CPU1_NMI
29-B1
CPU1_SMI#
12-B1
CPU1_REQ#(4:0)
12-B4
CPU1_CPURST#
29-C1
CPU1_INTR
H1
E2
G5
F1
H5
F21
E1
D20
B3
H4
C1
F3
F4
G3
G2
G6
HIT#
E4
A6
A5
C4
D5
C6
B4
A3
K3
H2
K2
J3
L1
CPU1_D#(15:0)
CPU1_DSTBN0#
CPU1_DSTBP0#
CPU1_D#(31:16)
CPU1_DSTBN1#
CPU1_DBI0#
CPU1_DBI1#
12-D4
12-B1
12-B1
12-B1
12-D4
12-B1
12-B1
12-B1
CPU1-2
PENRYN
2 / 4
0
E22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
K22
H23
H26
H25
N22
K25
P26
R23
M24
M23
P25
P23
P22
T24
R24
T25
N25
M26
N24
DATA GRP 0
D13#
D14#
D15#
J26
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
L23
D20#
D21#
L22
D22#
D23#
D24#
D25#
D26#
D27#
D28#
DATA GRP 1
L25
D29#
D30#
D31#
L26
DSTBN1#
DSTBP1#
DINV1#
0143854500|bga_479p_sock
DATA GRP 2
DSTBN2#
DSTBP2#
DATA GRP 3
DSTBN3#
DSTBP3#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV3#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
12-D4
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
5424
55
56
57
58
59
60
61
62
63
CPU1_D#(47:32)
C
12-B1
CPU1_DSTBN2#
12-B1
CPU1_DSTBP2#
12-B1
12-D4
CPU1_D#(63:48)
12-B1
CPU1_DSTBN3#
12-B1
CPU1_DSTBP3#CPU1_DSTBP1#
12-B1
CPU1_DBI3#
B
CPU Socket : 3704-001153
M501
SUPLECODE
1
MNT1
2
MNT2
3
MNT3
4
MNT4
BA75-01937A
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
A
4
8. Block Diagram and Schematic
CPU bracket
A
OF
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
CPU
PENRYN (1/3)
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-xxxxxA
8 59
8-8
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
4
CLK0_HCLK0
CLK0_HCLK0#
CPU1_SLP#
CPU1_DPSLP#
CPU1_DPRSTP#
CPU1_DPWR#
CPU1_PWRGDCPU
CPU1_PSI#
CPU1_VID(6:0)
P1.05V
R572
56
C
P1.05V
CPU1_THRMTRIP#
R519
1K
1%
CPU1_GTLREF_MN
R517
2K
1%
CPU1_PROCHOT#_MN
CPU2_THERMDA
CPU2_THERMDC
C531
100nF
10V
nostuff
CPU1_VCCSENSE
CPU1_VSSSENSE
7-C2
7-C2
13-B1,29-B1
CPU1_BSEL2
CPU1_BSEL1
CPU1_BSEL0
R538
R531
R553
R555
54.9
27.4
54.9
27.4
SI team request
B
P1.05V
1%
1%
54.9
54.9
R524
1%
54.9
1%
R526
54.9
near the CPU
9-C3
9-C3
9-C3
9-C3
CPU1_TDI
CPU1_TMS
CPU1_TCK
CPU1_TRST#
A
R521
R518
4
11-C1
11-C1
12-B4
29-C1
12-B1
29-C1
54-D4
54-C4
11-C4,12-A3
11-C4,12-A3
11-C4,12-A3
CPU1_COMP3_MN
1%
CPU1_COMP2_MN
1%
CPU1_COMP1_MN
1%
CPU1_COMP0_MN
1%
10-C4,54-A4
10-B4,54-A4
54-C413-B1,29-C1
6
5
4
3
2
1
0
A22
A21
D24
AE6
D21
A24
B25
C21
B23
B22
AD26
AA1
U26
R26
AF7
AE7
C23
D25
C24
AF26
AF1
A26
FSC
0
0
0
CPU1-3
PENRYN
3 / 4
BCLK0
BCLK1
D7
SLP#
B5
DPSLP#
E5
DPRSTP#
DPWR#
D6
PWRGOOD
PSI#
AE2
VID_6
AF3
VID_5
AE3
VID_4
AF4
VID_3
AE5
VID_2
AF5
VID_1
AD6
VID_0
PROCHOT#
THRMDA
THRMDC
C7
THERMTRIP#
BSEL2
BSEL1
BSEL0
GTLREF
Y1
COMP3
COMP2
COMP1
COMP0
VCCSENSE
VSSSENSE
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
C3
TEST7
0143854500|bga_479p_sock
FSB
FSA
0
0
0
1
1
1
BSEL
FSB 1067 MHz
FSB 800 MHz
H CLK
THERMAL
XDP/ITP SIGNALS
RSVD
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_8
VCCP_9
VCCP_10
VCCP_11
VCCP_12
VCCP_13
VCCP_14
VCCP_15
VCCP_16
PREQ#
PRDY#
BPM3#
BPM2#
BPM1#
BPM0#
TDO
TMS
TRST#
DBR#
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21
AC1
AC2
AC4
AD1
AD3
AD4
AC5
TCK
AA6
TDI
AB3
AB5
AB6
C20
M4
N5
T2
V3
B2
D2
D22
D3
F6
B26
VCCA_1
C26
VCCA_2
CPU Socket : 3704-001153
FRQ
266M
200M
166M
Pull-down
BSEL0, BSEL1, BSEL2
BSEL0, BSEL2
3
C582
10nF
25V
P1.05V
-> delete and change layout (ECAE)
3
P1.5V
EC502
220uF
2.5V
nostuff
C580
10000nF-X5R
6.3V
9-A4
9-A4
9-A4
9-A4
31-D3
C560
C557
100nF
100nF
10V
10V
nostuff
CPU1_TCK
CPU1_TDI
CPU1_TMS
CPU1_TRST#
ITP3_DBRESET#
C563
100nF
10V
C569
100nF
10V
C571
100nF
10V
nostuff
C567
100nF
10V
2
CPU Core Voltage Table
Active Mode
VID(6:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0 1
1
0
1
0
0
1
1
0
0
1
1 1
DPRSLPVR
DPRSTP*
PSI2*
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRAW
CHECK
APPROVAL
MODULE CODE
Voltage
0
1.5000 V
0
0
1.4875 V
1
0
0
0
1
1.4750 V
0
1.4625 V
1
0
1
1.4500 V
0
0
1
1
1
1.4375 V
0
1
1.4250 V
1
0
1
1.4125 V
1
1
1
1
0
0
1.4000 V
0
1
0
0
1.3875 V
0
0
1.3750 V
1
1.3625 V
1
0
1
1.3500 V
0
1
0
1
1
1.3375 V
0
0
1
1
1.3250 V
1.3125 V
1
1
1
1.3000 V
0
0
0
0
0
1
1.2875 V
0
1.2750 V
1
1
1
1.2625 V
0
0
0
1.2500 V
1
0
1.2375 V
1
1
0
1.2250 V
1
1
1
1
1
1
1.2125 V
1
0
0
1.2000 V
0
0
1.1875 V
1
0
1.1750 V
0
1
0
1.1625 V
1
0
1
0
1
0
1.1500 V
1
0
1
1.1375 V
1
1.1250 V
1
0
1
1
1.1125 V
1
1.1000 V
0
0
0
0
1
0
1.0875 V
0
0
1 1
1.0750 V
0
1
1
1.0625 V
0
0
1
1.0500 V
0
1
1
1.0375 V
100
1
1.0250 V
1
1
1
1
1.0125 V
Active
0
1
0 or 1
GTLREF : Keep the Voltage divider within 0.5"
of the first GTLREF0 pin with Zo=55ohm trace.
Minimize coupling of any switching signals to this net.
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
trace shorter than 1/2" to their respective Banias socket pins.
GND test points within 100mil of the VCC/VSSsense at the end of the line.
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
(preferred 50mil) from any other signal. And GND via 100mil away
from each of the VCC/VSS test point vias.
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
VID(6:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DPRSLPVR
DPRSTP*
PSI2*
9/23/2008
IMVP-6
Active/Deeper Sleep
Dual Mode Region
1
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
1
1
010
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1 1
0
1
0
1
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
Deeper Slp
1
0
0 or 1
TITLE
PV
1.0
1
Deeper Sleep/Extended Deeper Sleep
Dual Mode Region
VID(6:0)
Voltage
1
1.0000 V
0
1
0.9875 V
0
0.9750 V
0.9625 V
1
0.9500 V
0
1
0.9375 V
0
0.9250 V
1
0.9125 V
1
0
0.9000 V
1
0.8875 V
0
0.8750 V
0.8625 V
1
0
0.8500 V
1
0.8375 V
0
0.8250 V
0.8125 V
1
0
0.8000 V
1
0.7875 V
0.7750 V
0
0.7625 V
1
0
0.7500 V
1
0.7375 V
0.7250 V
0
1
1
0.7125 V
0.7000 V
0
1
0.6875 V
0
0.6750 V
0.6625 V
1
0.6500 V
0
1
0.6375 V
0
0.6250 V
1
0.6125 V
0
0.6000 V
0.5875 V
1
0.5750 V
0
0.5625 V
0.5500 V
0
0.5375 V
1
0
0.5250 V
1
0.5125 V
0.5000 V
0
Bremen-L3
PENRYN (2/3)
October 27, 2009 14:27:43 PM
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
00
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
*"1111111" : 0V power good asserted.
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
CPU
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
0
0
0
0
1
0
0
1
00
0
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
0
0
1
0
1 1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
SAMSUNG
PART NO.
9 59
PAGE
Voltage
0.4875 V
1
0.4750 V
0
1
0.4625 V
0
0.4500 V
1
0.4375 V
0
0.4250 V
0.4125 V
1
0
0.4000 V1
1
0.3875 V
0
0.3750 V
0.3625 V
1
0.3500 V
0
0.3375 V
1
0
0.3125 V
1
0.3000 V
1
0.2875 V
0.2750 V
0
0.2625 V
10
0.2500 V
0
0.2375 V
1
0.2250 V
0
0.2125 V
1
0.2000 V
1
0
1
0.1875 V
0
0.1750 V
1
0.1625 V
0.1500 V
0
1
0.1375 V
0
0.1250 V
1
0.1125 V
0.1000 V
0
0.0875 V
1
0
0.0750 V
1
0.0625 V
0
0.0500 V
0.0375 V
1
0.0250 V
0
1
0.0125 V
0.0000 V
0
1
0.0000 V
0
0.0000 V
0.0000 V
1
0.0000 V
0
0.0000 V
1
0.0000 V
0
1
0.0000 V
ELECTRONICS
BA41-xxxxxA
8-9
D
V 0523.01
C
A
OF
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
R530/R730
D
A11
VSS_1
A14
VSS_2
A16
VSS_3
A19
VSS_4
A2
VSS_5
A23
VSS_6
A25
VSS_7
A4
VSS_8
A8
VSS_9
AA11
VSS_10
AA14
VSS_11
AA16
VSS_12
AA19
CPU_CORE
C
CPU1_VCCSENSE
CPU1_VSSSENSE
9-C4,54-A4
9-C4,54-A4
R516
R515
100 1%
6.3V
6.3V
10000nF-X5R
10000nF-X5R
10000nF-X5R
10000nF-X5R
C543
C542
C541
C540
6.3V
10000nF-X5R
10000nF-X5R
10000nF-X5R
C545
C546
C544
10000nF-X5R
10000nF-X5R
10000nF-X5R
10000nF-X5R
C576
C573
C526
C547
10000nF-X5R
10000nF-X5R
10000nF-X5R
10000nF-X5R
10000nF-X5R
C577
C578
C527
C575
C574
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
100 1%
Prodlizer & Cbulk common used(Socket inside)
B B
AA22
AA25
AB11
AB13
AB16
AB19
AB26
AC11
AC14
AC16
AC19
AC21
AC24
AD11
AD13
AD16
AD19
AD22
AB23
AD25
AE11
AE14
AE16
AE19
AE23
AE26
AF11
AF13
AF16
AF19
AF21
VSS_13
AA2
VSS_14
VSS_15
VSS_16
AA5
VSS_17
AA8
VSS_18
AB1
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
AB4
VSS_25
AB8
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
AC3
VSS_33
AC6
VSS_34
AC8
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
AD2
VSS_40
VSS_41
VSS_42
VSS_43
AD5
VSS_44
AD8
VSS_45
AE1
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
AE4
VSS_53
AE8
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
AF2
VSS_59
VSS_60
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AC10
AC12
AC13
AC15
AC17
AC18
AD10
AD12
AD14
AD15
AD17
AD18
AE10
AE12
AE13
AE15
AE17
AE18
AE20
L21
L24
K23
K26
VSS_122K4VSS_123
VSS_124
VSS_121
A10
VCC_1
A12
VCC_2
A13
VCC_3
A15
VCC_4
A17
VCC_5
A18
VCC_6
A20
VCC_7
A7
VCC_8
A9
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
AA7
VCC_17
AA9
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
AB7
VCC_26
AB9
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
AC7
VCC_34
AC9
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
AD7
VCC_42
AD9
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VSS_161Y3VSS_162Y6VSS_163
VSS_160
Y24
Y21
W26
L3
L6
M22
M25
VSS_132
VSS_125
VSS_126
VSS_127M2VSS_128
VSS_129
VSS_130M5VSS_131
CPU1-4
PENRYN
4 / 4
0143854500|bga_479p_sock
VSS_151V2VSS_152
VSS_153
VSS_154V5VSS_155W1VSS_156
VSS_157
VSS_158W4VSS_159
U6 N1
V22
V25
W23
N23
N26
VSS_133
VSS_150
U3
U24
P21
P24
VSS_134N4VSS_135
VSS_136
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VSS_148
VSS_149
T26
U21
R2
R22
VSS_137P3VSS_138P6VSS_139
VSS_140
AE9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
AF9
B10
B12
B14
B15
B17
B18
B20
B7
B9
C10
C12
C13
C15
C17
C18
C9
D10
D12
D14
D15
D17
D18
D9
E10
E12
E13
E15
E17
E18
E20
E7
E9
F10
F12
F14
F15
F17
F18
F20
F7
F9
VSS_145
VSS_146T4VSS_147
T23
R25
VSS_141
CPU_CORECPU_CORE
VSS_142R5VSS_143T1VSS_144
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_99
VSS_98
VSS_97
VSS_96
VSS_95
VSS_94
VSS_93
VSS_92
VSS_91
VSS_90
VSS_89
VSS_88
VSS_87
VSS_86
VSS_85
VSS_84
VSS_83
VSS_82
VSS_81
VSS_80
VSS_79
VSS_78
VSS_77
VSS_76
VSS_75
VSS_74
VSS_73
VSS_72
VSS_71
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_65
VSS_64
VSS_63
VSS_62
VSS_61
K1
J5
J25
J22
J2
H6
H3
H24
H21
G4
G26
G23
G1
F8
F5
F25
F22
F2
F19
F16
F13
F11
E8
E6
E3
E24
E21
E19
E16
E14
E11
D8
D4
D26
D23
D19
D16
D13
D11
D1
C8
C5
C25
C22
C2
C19
C16
C14
C11
B8
B6
B24
B21
B19
B16
B13
B11
AF8
AF6
AF25
D
C
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
A
4
8. Block Diagram and Schematic
A
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
CPU
PENRYN (3/3)
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-xxxxxA
OF
5910
8-10
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
8-11
CK505M
D
C
B
A
FSA
BSEL0
0
0 0
0
0
1
1
1
CLK REQ
CLK REQ A
CLK REQ B
CLK REQ E
CLK REQ F
SEL_LCDCLK*
LOW
HIGH
FSB
FSC
BSEL1
BSEL2
1
1
0
0
1
1
CHP3_SATACLKREQ#
DEVICE
SATA
GMCH
MINI CARD
EXP3_CLKREQ#
Pin 20/21
DOT_96/DOT_96#
SRC_0/SRC_0#
HOST CLK
266 MHz
00
333 MHz
1
0
200 MHz
400 MHz
1
133 MHz
0
1
100 MHz1
0
166 MHz
1
RSVD
CLK3_MMC48
CLK3_USB48
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CLK3_ICH14
CHP3_CPUSTP#
CHP3_PCISTP#
CLK3_PWRGD
CLK3_PCLKICH
CLK3_DBGLPC
CLK3_PCLKMICOM
MCH3_CLKREQ#
SMB3_CLK
SMB3_DATA
SRC PORT
SRC2
SRC4
SRC6
SRC8
PEG_CLK/PEG_CLK#
4
Pin 24/25
27M & 27M_SS
41-C3
31-A3
9-C4,12-A3
9-C4,12-A3
9-C4,12-A3
31-A3
31-C3
31-C3
31-B3
30-C2
34-A4
44-B4
13-A1
31-B3
C123
0.018nF
50V
Place 14.318MHz within
500mils of CK-505
R107
R103
R100
R699
R689
R692
R693
R691
R690
R701
31-B417-B4,18-B4
31-B417-B4,18-B4
Y2
1
14.31818MHz
2801-004874
->delete and change layout? (ECAE)
VDD_SRC_IO
6.3V
10000nF-X5R
C851
nostuff
1%
33
1%
33
2.2K
1%
10K
1%33
22
22
22
475
1%
475
1%
nostuff
nostuff
nostuff
2
C122
0.018nF
50V
VDD_CPU_IO
10V
6.3V
10000nF-X5R
100nF
C865
C877
nostuff
50V
0.033nF
C822
VDD_PLL3_IO VDD_IO
10V
10000nF-X5R
100nF
C849
C844
nostuff
C134
0.022nF
50V
nostuff
50V
50V
0.033nF
0.033nF
C823
C821
nostuff
10V
6.3V
100nF
P3.3V
1%
10K
R684
1%
1%
10K
R703
3
6.3V
10000nF-X5R
C152
C869
CLK3_VDD_SRC_IO_MN
1%
10K
nostuff
R683
CLK3_USB48_R_MN
CLK3_ICH14_R_MN
CLK3_PCLKICH_R_MN
CLK3_DBGLPC_R_MN
CLK3_PCLKMICOM_R_MN
MCH3_CLKREQ#_R_MN
CHP3_SATACLKREQ#_R_MN
CLK_XTAL_IN_MN
CLK_XTAL_OUT_MN
10K
R702
P1.5V
B522
BLM18PG181SN1
U9
SLG8SP513
19
VDD_IO
33
VDD_SRC_IO1
43
VDD_SRC_IO2
52
VDD_SRC_IO3
56
VDD_CPU_IO
27
VDD_PLL3_IO
55
NC
17
USB_FS_A
64
FSB_TESTMODE
5
REF_FS_C_TEST_SEL
44
CPUSTOP#
45
PCISTOP#
63
CLKPWRGD_PWRDN#
14
PCIF_5_ITP_EN
13
PCI_4_SEL_LCDCLK#
12
PCI_3
11
PCI_2
10
PCI_1_CLKREQ_B#
8
PCI_0_CLKREQ_A#
7
SCL
6
SDA
3
XTAL_IN
2
XTAL_OUT
18
VSS_48
59
VSS_CPU
22
VSS_IO
15
VSS_PCI
26
VSS_PLL3
1
VSS_REF
30
VSS_SRC1
36
VSS_SRC2
49
VSS_SRC3
1205-003156
THERM_GND
65
This part is 64pin QFN package.
IDT : 1205-003159
SL : 1205-003533
CLK3_VDD_REF_MN
VDD_REF
VDD_48
VDD_PCI
VDD_PLL3
VDD_SRC
VDD_CPU
CPU0
CPU0#
CPU1_MCH
CPU1_MCH#
SRC11_CLKREQH#
SRC11#_CLKREQG#
SRC10
SRC10#
SRC9
SRC9#
SRC8_ITP
SRC8#_ITP#
SRC7_CLKREQF#
SRC7#_CLKREQE#
SRC6
SRC6#
SRC4
SRC4#
SRC3_CLKREQC#
SRC3#_CLKREQD#
SRC2
SRC2#
LCDCLK_27M
LCDCLK#_27M_SS
SRC0_DOT96
SRC0#_DOT96#
4
16
9
23
46
62
61
60
58
57
40
39
41
42
37
38
54
53
51
50
48
47
34
35
31
32
28
29
24
25
20
21
2
P3.3V
B521
BLM18PG181SN1
VDD_REF
CLK1_27M_R_MN
CLK1_27M_SS_R_MN
DRAW
CHECK
APPROVAL
MODULE CODE
D
4700nF->10uF (Y5V->X5R)
VDD_48
VDD_PCI
10V
10V
100nF
C837
100nF
C847
6.3V
10000nF-X5R
C843
10V
100nF
C872
VDD_PLL3
VDD_SRC
10V
100nF
C838
VDD_CPU
6.3V
10000nF-X5R
C834
C
9-D4
CLK0_HCLK0
9-D4
CLK0_HCLK0#
12-B1
CLK0_HCLK1
12-B1
CLK0_HCLK1#
40-C4
LAN3_CLKREQ#
40-C4
CLK1_PCIELOM
40-C4
CLK1_PCIELOM#
B
R108
R110
42-C3
MIN3_CLKREQ#
42-C3
CLK1_MINIPCIE
42-C3
CLK1_MINIPCIE#
13-B1
CLK1_MCH3GPLL
13-B1
CLK1_MCH3GPLL#
31-C1
CLK1_PCIEICH
31-C1
CLK1_PCIEICH#
29-B1
CLK1_SATA
29-B1
CLK1_SATA#
19-B2
22
22
19-B2
19-C4
19-C4
CLK1_27M
CLK1_27M_SS
CLK1_PEG
CLK1_PEG#
A
Jun PARK
YM.AHN
HJ.KIM
undefined
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
MAIN_CLOCK_CIRCUIT
CK_Clock_505M
October 27, 2009 14:27:43 PM
SAMSUNG
ELECTRONICS
PART NO.
BA41-xxxxxA
11 59
PAGE
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
OF
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
D
P1.05V
R580
221
1%
R585
100
1%
C635
100nF
10V
12-B4
C
P1.05V
R592
1K
1%
R588
2K
1%
12-A4
B
*POCAFEB-12 Only (Remove in MP Model)
CFG#
A
CFG(5)
CFG(6)
CFG(7)
CFG(9)
CFG(10)
CFG(16)
CFG(19)
CFG(20)
Current Setting
Low
DMIx2
iTPM Host Interface Enable
ME Crypto no confidentiality
PEG Reversal (def.)
PCIE Loop Back Enable
Dynamic ODT Disabled
DMI Lane Normal (def.)
SDVO or PCIE X1
Only(def.)
(def. : default Option)
DMIx4 (def.)
iTPM Host Interface Disable (def.)
ME Crypto confidentiality (def.)
Normal
PCIE Loop Back Disable(def)
Dynamic ODT
DMI Lane Reversal
SDVO and PCIE X1
Simultaneously
4
CPU1_D#(63:0)
MCH1_HXSWING
MCH1_HVREF
CPU1_CPURST#
CPU1_SLP#
MCH1_HXSWING
MCH1_HVREF
High
Enabled (def.)
8-C1
8-C3
9-D4
12-C4
R67
12-B4
MCH1_VTTLF1_MN
MCH1_VTTLF2_MN
MCH1_VTTLF3_MN
nostuff
MCH1_H_RCOMP_MN
24.9
1%
EC504
220uF
2.5V
AD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1608
470nF
C646
470nF
C778
470nF
C92
16V
C724
10000nF-X5R
6.3V
M11
N12
P13
N10
AD14
Y10
Y12
Y14
AA8
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C12
E11
B11
A11
AB2
16V
16V
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
W2
Y9
C5
E3
A8
L1
P1.05V
C818
100nF
10V
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_CPURST#
H_CPUSLP#
H_SWING
H_RCOMP
H_DVREF
H_AVREF
VTTLF_1
VTTLF_2
VTTLF_3
C759
100nF
10V
9-C4,11-C4
9-C4,11-C4
9-C4,11-C4
3
C740
100nF
10V
AA33
AA28
VCC_1
HOST DATA BUS
VTTLF
CFG_0
CFG_1
T25
P25
R25
3
AA34
VCC_2
CFG_2
P20
AB34
VCC_3
CFG_3
P24
AC26
VCC_4
CFG_4
C25
AC28
VCC_5
CFG_5
N24
AC33
AC34
AE26
AE33
VCC_6
VCC_7
VCC_8
VCC_9
CFG
CFG_6
CFG_7
CFG_8
CFG_9
E21
C24
C23
M24
MCH1_CFG6_MN
R633
2.2K
nostuff
iTPM option
AF23
VCC_10
VCC_11
CFG_10
CFG_11
N21
AF25
VCC_12
CFG_12
P21
AF28
VCC_13
CFG_13
T21
AF33
VCC_14
CFG_14
R20
AG24
VCC_15
CFG_15
M20
AG25
AG26
VCC_16
VCC CORE
CFG_16
CFG_17
L21
H21
AG33
VCC_17
VCC_18
CFG_18
P29
AG34
AH23
VCC_19
CFG_19
T28
R28
AH25
VCC_20
VCC_21
CFG_20
AH28
AA29
AK33
AJ23
AJ26
AJ33
VCC_25
VCC_22
VCC_23
VCC_24
VCC_NCTF_4
VCC_NCTF_3
VCC_NCTF_2
VCC_NCTF_1
AB30
AA32
AA30
AC29
AM33
T32
U33
U34
V33
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
U7-1
EB88CTPM
1 OF 5
0904-002376
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
AE29
AE30
AE32
AC30
AC32
Y34
V34
W33
Y33
VCC_35
VCC_31
VCC_32
VCC_33
VCC_34
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_10
VCC_NCTF_11
AF30
AG30
AG32
AG29
2
T11
T10
VTT_2
VTT_1
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
AJ29
AH29
AH30
AH32
2
T2
T12
T13
VTT_6T5VTT_7T6VTT_8T7VTT_9
VTT_3
VTT_4
VTT_5
VCC_NCTF_22
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
AJ32
AK23
AK24
AK25
T8
VTT_10T9VTT_11U1VTT_12
NC
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
AK26
AK28
AK29
AK30
DRAW
CHECK
APPROVAL
MODULE CODE
U10
U11
U12
VTT_13
VTT_14
VTT
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
AL26
AL28
AL29
AK32
U13
U5
VTT_15
VTT_16U2VTT_17U3VTT_18
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_31
AL32
AL30
AM30
AM32
Jun PARK
YM.AHN
HJ.KIM
undefined
U6
U9
VTT_19
VTT_20U7VTT_21U8VTT_22
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
V29
V30
U30
U32
DATE
DEV. STEP
REV
LAST EDIT
V1
VTT_23V2VTT_24V3VTT_25
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
Y29
W29
W30
W32
9/23/2008
PV
1.0
P1.05V
C794
1000nF-X5R
6.3V
HOST ADDRESS BUS
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
H_DBSY#
H_DPWR#
H_DRDY#
H_LOCK#
H_TRDY#
HPLL_CLK
HPLL_CLK#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
HOST CONTROL
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
VCC_NCTF_43
VCC_NCTF_44
Y30
Y32
TITLE
MCH_CANTIGA_GM_DDR2
October 27, 2009 14:27:43 PM
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_HIT#
H_HITM#
H_RS#_0
H_RS#_1
H_RS#_2
Bremen-L3
CANTIGA (1/5)
1
nostuff
C809
10000nF-X5R
6.3V
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
J11
F9
H9
E12
H11
C9
AH7
AH6
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
P1.05V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
0
1
2
3
4
C766
10000nF-X5R
6.3V
3
4
5
6
7
8
9
11-C1
11-B1
8-C3
8-C4
8-B4
8-C3
8-C3
8-C3
8-C3
8-C3
9-D4
8-C3
8-C3
8-C3
8-C3
8-C3
8-C2
8-B2
8-C1
8-B1
8-C2
8-B2
8-C1
8-B1
8-C2
8-B2
8-C1
8-B1
8-B3
8-C3
8-C3
8-C3
EC503
220uF
2.5V
AD
8-C4
CPU1_ADS#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_DEFER#
CPU1_DBSY#
CPU1_DPWR#
CPU1_DRDY#
CPU1_HIT#
CPU1_HITM#
CPU1_LOCK#
CPU1_TRDY#
CLK0_HCLK1
CLK0_HCLK1#
CPU1_DBI0#
CPU1_DBI1#
CPU1_DBI2#
CPU1_DBI3#
CPU1_DSTBN0#
CPU1_DSTBN1#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP0#
CPU1_DSTBP1#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_REQ#(4:0)
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
nostuff
CPU1_A#(35:3)
SAMSUNG
PART NO.
12 59
PAGE
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
R530/R730
D
C
B
A
ELECTRONICS
BA41-xxxxxA
OF
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
8-12
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
D
C
B
A
4
H32
J32
J29
L29
E28
G28
J28
E29
G29
C31
E32
F25
H25
K25
H24
K33
J33
M32
M33
M29
G32
L32
H47
E46
G40
A40
H48
D45
F40
B40
C40
C41
A41
H38
G37
J37
B42
G38
F37
K37
A37
B37
C44
B43
E37
E38
B28
A28
B30
B29
C29
PEG1_RXN(15:0)
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_TVO_IREF
CRT_IRTN
TV_DCONSEL_0
TV_DCONSEL_1
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
L_VDD_EN
L_BKLT_EN
L_BKLT_CTRL
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSA_CLK
LVDSA_CLK#
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
LVDSB_CLK
LVDSB_CLK#
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
HDA_BCLK
HDA_SYNC
HDA_RST#
HDA_SDI
HDA_SDO
AGVVT
LVDSHDA
19-C4
1 9
H44
J46
L44
PEG_RX#_0
PEG_RX#_1
NC_1
NC_2
A46
A44
A43
3
10
Y48
T43
U43
Y43
Y36
N44
PEG_RX#_8
PEG_RX#_9
PEG_RX#_6
PEG_RX#_7
PEG_RX#_10
PEG_RX#_11
AA23
AA24
AA25
AA21
AA20
AA15
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_3
VCC_AXG_2
VCC_AXG_1
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
AF16
AF17
AF19
AE16
AE17
AE19
NC_10
NC_11
NC_12
NC_8
NC_9
B48
B45
B47
BC1
BC48
14
AA43
AD37
AC47
PEG_RX#_12
PEG_RX#_13
AB20
AB23
AB15
VCC_AXG_8
VCC_AXG_7
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
AG16
AG17
AG19
NC_13
NC_14
BE2
BD1
BD48
4
32 0
L40
N41
P48
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
NC_5
NC_4
NC_3
NC_6B4NC_7
A5
A6
A47
3
19-C4
1
H43
J44
AD39
PEG_RX_0
PEG_RX#_14
PEG_RX#_15
2
4765
3
L43
L41
PEG_RX_3
PEG_RX_1
PEG_RX_2
5
60
N40
P47
N43
PEG_RX_4
PEG_RX_5
PEG_RX_6
8
7118
T42
U42
PEG_RX_7
PEG_RX_8
0151
1112
9
Y42
W47
PEG_RX_9
PEG_RX_10
1312 15
14
Y37
AA42
AD36
PEG_RX_11
PEG_RX_12
PEG_RX_13
AC48
0
10V
100nF
C688
J41
AD40
PEG_TX#_0
PEG_RX_14
PEG_RX_15
2
1
10V
10V
10V
100nF
100nF
100nF
C654
C685
C656
M47
M40
M46
PEG_TX#_2
PEG_TX#_1
PEG1_RXP(15:0)
6
4
5
10V
10V
10V
100nF
100nF
100nF
C722
C708
C100
M42
R48
N38
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PCIE GFX
U7-2
EB88CTPM
AH20
AJ15
AJ21
AL15
AM14
AM15
AN14
T14
T16
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
0904-002376
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
V16
V17
V19
U20
U21
U16
U19
NC_36
NC_37
NC_38D2NC_39
NC_34
NC_35
C3
C46
C48
D47
BH6
T17
VCC_AXG_34
VCC_AXG_NCTF_41
V21
NC_40E1NC_41
E48
AE21
AE23
AE24
AE25
AF15
AF20
AG15
AG21
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
AH15
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_27
VCC_AXG_25
VCC_AXG_26
AB25
AC20
AC21
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
AC23
AC24
AE15
AE20
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
GFX VCC
2 OF 5
GFX VCC NCTF
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
AL16
BG48
AL19
NC_26
BH2
AL21
NC_27
BH3
AM16
NC_28
BH43
AM17
NC_29
BH44
VCC_AXG_NCTF_34
AM19
AM20
AM21
NC_30
NC_31
NC_32
NC_33
BH5
BH46
BH47
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
AJ16
AJ19
AK16
AK17
AK19
AK20
AK21
VCC_AXG_NCTF_26
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
AH16
AH17
AH19
NC RSVD
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
BF1
BF3
BG1
BG2
BG4
BF46
BF48
BE47
BG45
BG47
12
13
119
8
7
10V
10V
10V
10V
10V
10V
10V
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C749
C723
C748
C765
C729
C108
C731
T40
U37
U40
AA46
AA37
AA40
Y40
PEG_TX#_8
PEG_TX#_9
PEG_TX#_6
PEG_TX#_7
PEG_TX#_11
PEG_TX#_12
PEG_TX#_10
U14
U15
V15
Y15
Y21
Y24
Y26
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_35
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
V26
V28
V23
V24
V25
W16
W17
NC_42
NC_43
RSVD_2
RSVD_1
F1
F48
AH12
AH13
AH10
ME Debug Port
2
19-A4
2103 8
15
14
0
1
10V
10V1310V
10V
10V
100nF
100nF
100nF
100nF
100nF
C655
C686
C777
C687
C776
M48
J42
L46
AD43
AC46
PEG_TX_0
PEG_TX_1
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
AA19
AA16
VCC_AXG_42
VCC_AXG_NCTF_1
GFX VCC NCTF
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
W19
W20
W21
W23
W24
W25
RSVD12
RSVD11
RSVD10
RSVD13
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
AH9
AL34
AK34
AY21
AN35
AM35
2
PEG1_TXN(15:0)
5
6 9
4
7
10V
10V
10V
10V
10V
10V
10V
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C657
C728
C702
C730
C732
C101
C707
M39
M43
R47
N37
T39
U36
U39
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_2
AC16
AC17
AB19
AB17
AB16
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_5
VCC_AXG_NCTF_4
VCC_AXG_NCTF_3
VCC_AXG_NCTF_2
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_55
Y16
Y17
Y19
W26
W28
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
B2
B31
K12
BF18
BF23
BH18
BG23
DRAW
CHECK
APPROVAL
MODULE CODE
11
10
10V
10V
100nF
100nF
C104
C758
Y39
Y46
PEG_TX_9
PEG_TX_10
RSVD_17
RSVD_16
M1
M36
213
15
13
14
10V
10V
10V
100nF
100nF
100nF
C782
C757
C744
AA36
AA39
AD42
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
RSVD_18
RSVD_19
RSVD_20
RSVD_21
T24
N36
R33
19-B4
10V
100nF
C783
AD46
PEG_TX_15
PCIE GFX
RSVD_22
T33
P3.3V
Jun PARK
YM.AHN
HJ.KIM
undefined
PEG1_TXN1_MN
PEG1_TXN0_MN
R622
DEV. STEP
REV
LAST EDIT
PEG1_TXP(15:0)
PEG1_TXN6_MN
PEG1_TXN3_MN
PEG1_TXN2_MN
PEG1_TXN5_MN
PEG1_TXN4_MN
PEG_COMPO
DMICLKMEPMMISC
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
10K
9/23/2008
PEG1_TXN11_MN
PEG1_TXN10_MN
PEG1_TXN12_MN
PEG1_TXN7_MN
PEG1_TXN9_MN
PEG1_TXN8_MN
PEG_COMPI
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
PEG_CLK
PEG_CLK#
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
PM_SYNC#
DPRSLPVR
PWROK
RSTIN#
THERMTRIP#
CLKREQ#
ICH_SYNC#
TSATN#
11-B4
MCH3_CLKREQ#
TETAD
ELTI
PV
MCH_CANTIGA_GM_DDR2
1.0
PEG1_TXN14_MN
PEG1_TXN13_MN
PEG1_TXN15_MN
PEG1_TXP0_MN
PEG1_TXP1_MN
PEG1_TXP2_MN
PEG1_TXP3_MN
PEG1_TXP4_MN
MCH1_COMPIO_R_MN
31-D1
31-D1
31-D1
31-C1
31-D1
31-D1
31-D1
31-C1
31-D1
31-D1
31-D1
31-C1
31-D1
31-D1
31-D1
31-C1
11-B1
11-B1
31-C1
31-C1
31-B3,44-C4
31-C1
31-D3
54-C4 9-D4,29-C1
31-C3,54-C4
31-B3,44-C4
PLT3_RST#_R_MN
MCH3_EXTTS0#_MN
MCH3_EXTTS1#_MN
R599
0
MCH3_TSATN#_MN
R595
1608
DMI1_TXN_0
DMI1_TXN_1
DMI1_TXN_2
DMI1_TXN_3
DMI1_TXP_0
DMI1_TXP_1
DMI1_TXP_2
DMI1_TXP_3
DMI1_RXN_0
DMI1_RXN_1
DMI1_RXN_2
DMI1_RXN_3
DMI1_RXP_0
DMI1_RXP_1
DMI1_RXP_2
DMI1_RXP_3
MCH1_CL_VREF_MN
nostuff
T37
T36
B33
B32
G33
F33
E33
C34
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
B38
A38
E41
F41
F43
E43
AH37
AH36
AN36
AJ35
AH34
R29
B7
R32
AT40
AT11
T20
N33
P32
N28
M28
G36
E36
K36
H36
B12
Bremen-L3
CANTIGA (2/5)
October 27, 2009 14:27:43 PM
1
PEG1_TXP11_MN
PEG1_TXP13_MN
PEG1_TXP12_MN
PEG1_TXP15_MN
PEG1_TXP14_MN
PEG1_TXP10_MN
PEG1_TXP5_MN
PEG1_TXP6_MN
PEG1_TXP7_MN
PEG1_TXP9_MN
PEG1_TXP8_MN
P1.05V_PEG
CLK1_MCH3GPLL
CLK1_MCH3GPLL#
CHP3_CL_CLK_0
CHP3_CL_DATA_0
KBC3_PWRGD
CHP3_CL_RST_0#
CHP3_PM_SYNC#
CPU1_DPRSTP#
CHP3_DPRSLPVR
KBC3_PWRGD
9-C4,29-B1
10K
R638
10K
R639
MCH3_CLKREQ#
11-B4
MCH3_ICHSYNC#
31-B3
P1.05V
56
PART NO.
PAGE
1%49.9
P1.05V
C810
100nF
10V
R704
100
1%
PLT3_RST#
19-D4,30-C1
34-A4,40-D4
42-C2,44-B3
CPU1_THRMTRIP#
P3.3V
1%
1%
SAMSUNG
ELECTRONICS
BA41-xxxxxA
13 59
OF
R679
1K
1%
R671
499
1%
R664
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
8-13
D
C
B
A
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
4
MEM1_ABS(2:0)
MEM1_ADM(7:0)
MEM1_ADQS#(7:0)
MEM1_ADQS(7:0)
C
MEM1_AMA(14:0)
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
MEM1_CS0#
MEM1_CS1#
MEM1_ODT0
B
P1.8V_AUX
R716
80.6
1%
R720
80.6
1%
MEM1_ODT1
MEM1_CKE0
MEM1_CKE1
CLK1_MCLK0
CLK1_MCLK0#
CLK1_MCLK1
CLK1_MCLK1#
MCH1_SM_RCOMP_MN
MCH1_SM_RCOMP#_MN
P1.8V_AUX
R708
1K
10nF->100nF
1%
C852
C866
100nF
10V
C874
100nF
10V
2200nF-X5R
10V
C873
2200nF-X5R
10V
R715
A
3.01K
1%
R719
1K
1%
4
17-C2
17-B4
17-A4
17-B4
17-D2
17-C2
17-B4
17-B4
17-C2
17-C2
17-B4
17-B4
17-C2
17-C2
17-C4
17-C4
17-C4
17-C4
MCH1_SM_RCOMP_V_OH_MN
MCH1_SM_RCOMP_V_OL_MN
Route as short as possible
nostuff
nostuff
MEM1_ADQ(63:0)
0
BD21
SA_BS_0
1
BG18
SA_BS_1
2
AT25
SA_BS_2
0
AM37
SA_DM_0
1
AT41
SA_DM_1
2
AY41
SA_DM_2
3
AU39
SA_DM_3
4
BB12
SA_DM_4
5
AY6
SA_DM_5
6
AT7
SA_DM_6
7
AJ5
SA_DM_7
0
AJ43
SA_DQS#_0
1
AT43
SA_DQS#_1
2
BA44
SA_DQS#_2
3
BD37
SA_DQS#_3
4
AY12
SA_DQS#_4
5
BD8
SA_DQS#_5
6
AU9
SA_DQS#_6
7
AM8
SA_DQS#_7
0
AJ44
SA_DQS_0
1
AT44
SA_DQS_1
2
BA43
SA_DQS_2
3
BC37
SA_DQS_3
4
AW12
SA_DQS_4
5
BC8
SA_DQS_5
6
AU8
SA_DQS_6
7
AM7
SA_DQS_7
0
BA21
SA_MA_0
1
BC24
SA_MA_1
2
BG24
SA_MA_2
3
BH24
SA_MA_3
4
BG25
SA_MA_4
5
BA24
SA_MA_5
6
BD24
SA_MA_6
7
BG27
SA_MA_7
8
BF25
SA_MA_8
9
AW24
SA_MA_9
10
BC21
SA_MA_10
11
BG26
SA_MA_11
12
BH26
SA_MA_12
13
BH17
SA_MA_13
14
AY25
SA_MA_14
BD20
SA_CAS#
BB20
SA_RAS#
AY20
SA_WE#
BA17
SA_CS#_0
AY16
SA_CS#_1
BD17
SA_ODT_0
AY17
SA_ODT_1
BC28
SA_CKE_0
AY28
SA_CKE_1
AP24
SA_CK_0
AR24
SA_CK#_0
AT21
SA_CK_1
AR21
SA_CK#_1
BG22
SM_RCOMP
BH21
SM_RCOMP#
BF28
SM_RCOMP_V_OH
BH28
SM_RCOMP_V_OL
Cantiga
DDR2
17-D4
0
8 10 62
4 5 21
2 186
1
3
AM44
AM42
AJ40
AJ36
AM38
AN38
AJ38
AJ41
SA_DQ_6
SA_DQ_7
SA_DQ_5
SA_DQ_4
SA_DQ_3
SA_DQ_2
SA_DQ_0
SA_DQ_1
SYSTEM MEMORY A
SB_DQ_5
SB_DQ_4
SB_DQ_3
SB_DQ_2
SB_DQ_0
SB_DQ_1
AJ48
AJ46
AP46
AP47
AK47
AH46
4 7
6
1
0
5
SM_RCOMP : 80 ohm to P1.8V_AUX
SM_RCOMP# : 80 ohm to VSS
3
AN43
AN44
SA_DQ_8
SA_DQ_9
SB_DQ_7
SB_DQ_6
AP48
AM48
8
3
11
AU40
AT38
AN41
SA_DQ_10
SA_DQ_11
SB_DQ_8
SB_DQ_9
BA48
AU47
AU46
10
11
9
13
15
14
AN39
AU44
AU42
SA_DQ_12
SA_DQ_13
SA_DQ_14
SB_DQ_10
SB_DQ_11
SB_DQ_12
AT47
AY48
AR47
13
12
1415
23
717
16
19
2221 61
20
AY44
BA40
BD43
AV41
AY43
BB41
AV39
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_15
SA_DQ_16
31
24 53
BC40
SA_DQ_23
AV37
AY37
BD38
SA_DQ_24
SA_DQ_25
28
27
AT36
AY38
SA_DQ_27
SA_DQ_28
SA_DQ_26
3025
BB38
AV36
AW36
SA_DQ_29
SA_DQ_30
32
SA_DQ_31
3334
BD13
AU11
SA_DQ_32
SA_DQ_33
36
35
BC11
BA12
SA_DQ_34
SA_DQ_35
37
3839
AU13
AV13
BD12
SA_DQ_36
SA_DQ_37
40344229
41
BC12
BB9
SA_DQ_38
SA_DQ_39
SA_DQ_40
43
44
BA9
AU10
AV9
SA_DQ_41
SA_DQ_42
SA_DQ_43
459
46
BA11
BD9
SA_DQ_44
SA_DQ_45
AY8
SYSTEM MEMORY A
U7-3
EB88CTPM
3 OF 5
0904-002376
SYSTEM MEMORY B
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_15
SB_DQ_13
SB_DQ_14
BA47
BC47
BC46
165218
17
SB_DQ_16
SB_DQ_17
SB_DQ_18
BF43
BC44
BG43
2021 4019
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
BG35
28
SB_DQ_34
BG8
BH11
BH40
BH34
BH14
BG39
BG34
BG12
31
32
33
36
30
35
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
BF38
BF40
BF41
BE45
BH35
BC41
BG38
27
26 55
24
23
SB_DQ_43
BF6
BF8
AY3
AY1
BC5
BC6
BG7
BF11
BH12
3839
43
37
44
42
45
2
47
48
49
BA6
AV5
AV7
SA_DQ_46
SA_DQ_47
SA_DQ_48
SB_DQ_44
SB_DQ_45
SB_DQ_46
BF5
BA1
BD3
48
47
4641
2
5126
50
AT9
AN8
SA_DQ_49
SA_DQ_50
SA_DQ_51
SB_DQ_47
SB_DQ_48
SB_DQ_49
AV2
AU3
49
50
54
AU5
AU6
AT5
SA_DQ_52
SA_DQ_53
SB_DQ_50
SB_DQ_51
AY2
AR3
AN2
51
5225
532922
DRAW
CHECK
APPROVAL
MODULE CODE
55
56
5758
AN10
AM11
SA_DQ_56
SA_DQ_54
SA_DQ_55
SB_DQ_54
SB_DQ_52
SB_DQ_53
AP3
AV1
54
59
AM5
AJ9
AJ8
SA_DQ_57
SA_DQ_58
SB_DQ_55
SB_DQ_56
AL1
AL2
AR1
5657
58
60
AN12
AM13
AJ11
SA_DQ_59
SA_DQ_60
SA_DQ_61
SB_DQ_57
SB_DQ_58
SB_DQ_59
AJ1
AH1
AM2
59
61
602 3
Jun PARK
63
AJ12
SA_DQ_62
SA_DQ_63
SB_DQ_60
SB_DQ_61
SB_DQ_62
AH3
AM3
62
63
YM.AHN
HJ.KIM
SM_DRAMRST#
SM_PWROK
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SYSTEM MEMORY B
SB_DQ_63
AJ3
18-D4
DATE
DEV. STEP
REV
LAST EDIT
SM_REXT
SM_VREF
SB_CAS#
SB_RAS#
SB_WE#
SB_CS#_0
SB_CS#_1
SB_ODT_0
SB_ODT_1
SB_CKE_0
SB_CKE_1
SB_CK_0
SB_CK#_0
SB_CK_1
SB_CK#_1
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_BS_0
SB_BS_1
SB_BS_2
9/23/2008
MEM1_SM_REXT_MN
BF17
AV42
BC36
AR36
BG16
AU17
BF14
AV16
AR13
BF15
AY13
AY36
BB36
AV24
AU24
AU20
AV20
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
BC16
BB17
BB33
MEM1_BDQ(63:0)
TITLE
PV
1.0
1
MEM1_VREF
499
1%
R714
51-B1 17-C3,18-C3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
MCH_CANTIGA_GM_DDR2
October 27, 2009 14:27:43 PM
18-C1
18-B4
18-B4
18-C1
18-C1
18-B4
18-B4
18-C1
18-C1
18-C4
18-C4
18-C4
18-C4
18-B4
18-A4
MEM1_BDQS#(7:0)
18-B4
MEM1_BDQS(7:0)
18-D1
MEM1_BMA(14:0)
18-C1
MEM1_BBS(2:0)
Bremen-L3
CANTIGA (3/5)
MEM1_VREF
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
MEM1_CS2#
MEM1_CS3#
MEM1_ODT2
MEM1_ODT3
MEM1_CKE2
MEM1_CKE3
CLK1_MCLK2
CLK1_MCLK2#
CLK1_MCLK3
CLK1_MCLK3#
MEM1_BDM(7:0)
1
PLACE EACH CAP NEAR AV42 PIN
51-B117-C3,18-C3
C830
C839
100nF
100nF
10V
10V
nostuff
nostuff
SM_PWROK
DDR2 : GND
DDR3 : Connect to VRM.
SAMSUNG
ELECTRONICS
PART NO.
BA41-xxxxxA
OFPAGE
R530/R730
D
C
B
A
5914
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
8-14
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
D
nostuff
P1.8V_AUX
EC506
220uF
2.5V
AD
C826
10000nF-X5R
6.3V
22uF->10uF
C827
10000nF-X5R
3
C841
C845
100nF
100nF
10V
6.3V
10V
2
1
8-15
D
P1.05V
MCH1_P1.05V_AXF_MN
C650
C645
10000nF-X5R
1000nF-X5R
6.3V
6.3V
nostuff
A21
AF48
AG47
AH47
AH48
B21
B22
B27
A26
A25
A24
B24
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VCCA_TV_DAC_1
VCCA_TV_DAC_2
VCC AXG
VCC AXGCRT / TV POWERLVDS POWER
P1.05V_PEG
C793
100nF
10V
C
P1.5V
C658
100nF
10V
MCH1_P1.5V_TVDAC_MN
C667
10nF
25V
B
A
M25
VCCD_TVDAC
L28
VCCD_QDAC
J48
VCCA_LVDS
L37
VCCD_LVDS_1
M38
VCCD_LVDS_2
K47
VCC_TX_LVDS VSS_AXG_SENSE
10V
100nF
C842
C840
C836
C825
C835
C815
C819
1000nF-X5R
220nF
1000nF-X5R
220nF
470nF
100nF
6.3V
16V
6.3V
16V
16V
10V
P1.8V_AUX
B523
BLM18PG181SN1
4
AW16
BA36
BB21
BB24
BD16
VCC_SM_NC_3
VCC_SM_NC_4
VCC_SM_NC_5
VCC_SM_NC_6
VCC_SM_NC_7
VCC_SM_LF_6
VCC_SM_LF_7
VCC_SM_LF_4
VCC_SM_LF_5
AY5
BA37
BB13
AV21
AV44
C875
10000nF-X5R
6.3V
AT13
AW13
BH31
BH32
VCC_SM_35
VCC_SM_NC_1
VCC_SM_NC_2
VCC_SM_LF_1
VCC_SM_LF_2
VCC_SM_LF_3
AM10
AM40
R721
1
3
BF31
BF32
BH29
BG30
BG31
BG32
BG29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_28
VCC_SM_29
EB88CTPM
VCC_SM_CKVCC_SM_LF
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VCC_SM_CK_1
BF20
BF21
BH20
BG20
MCH1_P1.8VAUX_SM_CK_MN
C870
100nF
10V
BF29
BC29
BC32
BD29
BD32
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM
U7-4
4 OF 5
0904-002376
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
AM25
AM26
AM28
BB29
BB32
AY29
AY32
BA29
BA32
AW29
AW32
VCC_SM_20
VCC_SM_21
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
AL25
AL23
AL24
AP28
AM23
AM24
C828
C817
100nF
2200nF-X5R
10V
10V
nostuff
AT32
AV29
AV32
AU32
AU29
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
AP25
AN24
AN25
AN28
C750
10000nF-X5R
6.3V
AT29
AR29
AR32
VCC_SM_8
VCC_SM_6
VCC_SM_7
VCCA_SMVCCA_SM_CKVCCA_SM_CK_NCTF
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
AT16
AR20
P1.05V
AP32
AP33
AP29
VCC_SM_4
VCC_SM_5
VCC_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
AP20
AR17
AR16
22uF->10uF
AN33
AN32
VCC_SM_2
VCC_SM_1
VCCA_SM_2
VCCA_SM_3
AP16
AP17
AN20
C795
1000nF-X5R
6.3V
VCCA_SM_1
AN17
2
VCC HADVCC_HVPEG POWER
PLL POWER
VCC_AXG_SENSE
AXG SENSE
C816
10000nF-X5R
6.3V
VCC_HDA
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCCA_PEG_BG
VCCA_PEG_PLL
VCCD_PEG_PLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCD_HPLL
C824
10000nF-X5R
6.3V
Y5V -> X5R
22uF->10uF
DRAW
CHECK
APPROVAL
MODULE CODE
HDMI OPTION
A32
A35
B35
C35
U46
U47
U48
V47
V48
AD48
AA48
AA47
F47
L48
AD1
6.3V
MCH1_P1.05V_MPLL_MN
AE1
AF1
100
R680
AJ14
100
R672
AH14
nostuff
nostuff
MCH1_VCC_AXG_SENSE_MN
MCH1_VSS_AXG_SENSE_MN
C751
22000nF-X5R
20%
6.3V
DATE
Jun PARK
DEV. STEP
YM.AHN
REV
HJ.KIM
LAST EDIT
P3.3V
C644
100nF
10V
P1.5V
Cantiga : 1.5V
C784
100nF
10V
MCH1_P1.05V_PEG_PLL_MN
C767
10000nF-X5R
P1.05V
1%
C796
100nF
10V
1%
C801
100nF
10V
P1.05V
EC505
220uF
2.5V
nostuff
AD
nostuff
TITLE
9/23/2008
PV
1.0
R109
2A routing
C121
10000nF-X5R
6.3V
Y5V -> X5R
C785
100nF
10V
R673
1
MCH_CANTIGA_GM_DDR2
P1.05V
MCH1_P3.3V_HV_R_MN
12.1
2
1%
BAT54A
P1.05V_PEG
C120
10000nF-X5R
6.3V
Y5V -> X5R
22uF->10uF
C113
100nF
10V
BLM18PG181SN1
B515
R674
1
C811
10000nF-X5R
6.3V
22uF->10uF
MCH1_P1.05V_MPLL_R_MN
Bremen-L3
CANTIGA (4/5)
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
3
1
30V
D11
INSTPAR
SHORT502
INSTPAR
SHORT503
B10
BLM18PG181SN1
R80
1
C112
10000nF-X5R
6.3V
PAGE
P1.05V
P1.05V
P1.05V
SAMSUNG
ELECTRONICS
PART NO.
BA41-xxxxxA
OF
C
B
A
5915
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
R530/R730
D
A12
VSS_1
A15
VSS_2
A18
VSS_3
A20
VSS_4
A23
VSS_5
A29
VSS_6
A31
VSS_7
A34
VSS_8
AA1
VSS_9
AA10
VSS_10
AA12
VSS_11
AA14
VSS_12
AA26
VSS_13
AA35
VSS_14
AA38
VSS_15
AA41
VSS_16
AA44
VSS_17
AA7
VSS_18
AB21
VSS_19
AB24
VSS_20
AB26
VSS_21
AB28
VSS_22
AB33
VSS_23
AB47
VSS_24
AC15
VSS_25
AC2
C
B
AC25
AD12
AD38
AD41
AD47
AE10
AE13
AE28
AE34
AE36
AE39
AE42
AF21
AF24
AF26
AF34
AF47
AG20
AG23
AG28
AH11
AH21
AH24
AH26
AH33
AH35
AH38
AH41
AH44
AJ10
AJ13
AJ20
AJ24
VSS_26
VSS_27
VSS_28
AD2
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
AD5
VSS_34
AD9
VSS_35
VSS_36
VSS_37
AE2
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
AE7
VSS_44
AF2
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
AH2
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
AH5
VSS_64
AH8
VSS_65
VSS_66
VSS_67
AJ2
VSS_68
VSS_69
VSS_70
AJ39
AJ42
AJ47
AJ7
AK15
AL3
AL33
AL48
AM1
VSS_76
VSS_77
VSS_78
VSS_79
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4C1VSS_SCB_5
A48
BH1
BH48
VSS_80
VSS_81
AM12
AM34
VSS_82
VSS_83
VSS_84
VSS_NCTF_2
VSS_NCTF_1
AB29
AB32
AA17
AM36
VSS_85
VSS_NCTF_3
AC19
AJ25
AJ28
AJ34
AJ37
VSS_75
VSS_71
VSS_72
VSS_73
VSS_74
VSS
TV & LVDS
VSS SCB VSS NCTF VSS
VSS
VSSA_DAC_BG
VSSA_LVDS
A3
J47
B25
AM46
AM39
AM41
AM43
VSS_86
VSS_87
VSS_88
VSS_89
F38
F44
F46
F5
G11
G13
G16
G21
G24
G25
G41
G47
G9
H1
H17
H28
H29
H33
H37
H40
H46
H5
J12
J21
J24
J25
J36
J38
J43
J5
J7
K16
K2
K20
K24
K28
K29
K32
L12
L13
L24
L25
L33
L36
L39
L42
L47
L5
L8
M10
M17
M2
M21
M41
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
AJ17
AJ30
AF29
AF32
AM6
AM9
AN11
VSS_90
VSS_91
VSS_92
VSS_93
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_NCTF_9
VSS_NCTF_8
VSS_NCTF_10
VSS_NCTF_11
AL17
AL20
AM29
AN13
AN16
AN21
AN29
AN37
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
U7-5
EB88CTPM
5 OF 5
0904-002376
VSS
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_12
VSS_NCTF_13
V20
V32
U26
U17
U23
AN40
VSS_99
AN42
AN47
VSS_100
VSS_349
AJ6
BG21
AN7
AN9
VSS_101
VSS_102
VSS
VSS_206
VSS_207
BG28
BG33
AP2
AP21
VSS_103
VSS_104
VSS_208
VSS_209
BG36
BG40
AR2
AR25
VSS_105
VSS_106
VSS_210
VSS_211
BG6
BG42
AR28
AR33
VSS_107
VSS_108
VSS_212
VSS_213
BH23
BH25
AR46
AR48
VSS_110
VSS_109
VSS
VSS_214
VSS_215
BH8
BH38
AT10
AT12
VSS_111
VSS_112
VSS_216
VSS_217
C11
C14
AT17
VSS_113
VSS_114
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_218
VSS_219
C17
AT20
AT24
VSS_115
VSS_220
C20
C26
AT28
AT37
VSS_116
VSS_117
M44
M6
N11
N13
N16
N20
N25
N29
N32
N39
N42
N47
N7
P1
P28
P3
P33
P36
P46
R17
R21
R24
R3
R46
T29AD44
T35
T38
T41
T44
T47
U24
U25
U28
U29
U35
U38
U41
U44
V46
W15
W34
Y11
Y2
Y20
Y23
Y25
Y28
Y35
Y38
Y41
Y44
Y47
Y5
Y8
VSS_221
VSS_222
C28
C32
AT42
AT39
VSS_118
VSS_119
VSS_223
VSS_224
C37
C38
AT6
AT8
VSS_120
VSS_121
VSS_225
VSS_226C6VSS_227
C43
AU16
AU2
VSS_122
VSS_123
VSS_228
E13
E16
AU21
AU36
VSS_124
VSS_125
VSS_230
VSS_229
E24
E25
AU38
AU41
VSS_126
VSS_127
VSS_231
VSS_232E8VSS_233
E40
AU48
AU43
VSS_128
VSS_129
VSS_234
F24
F20
AU7
AV10
VSS_130
VSS_131
VSS_235
VSS_236
F28
F29
AV12
AV25
AV28
VSS_132
VSS_133
VSS_134
VSS_237F3VSS_238
VSS_239
F32
F36
VSS_135
VSS
VSS_240
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
AV3
AV33
AV40
AV43
AV46
AV6
AV8
AW17
AW2
AW20
AW21
AW37
AW47
AY11
AY24
AY42
AY46
AY7
B23
B26
B34
B36
B39
B41
B8
B9
BA13
BA16
BA2
BA20
BA28
BA33
BA38
BA46
BA5
BB11
BB25
BB37
BB40
BB47
BB8
BC13
BC17
BC20
BC3
BC33
BC38
BC43
BC9
BD11
BD25
BD28
BD36
BD41
BD46
BD6
BE4
BF12
BF24
BF26
BF34
BF37
BF44
BF9
BG10
BG13
BG14
BG15
BG17
BG19
D
C
B
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
A
4
8. Block Diagram and Schematic
A
DRAW
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
DEV. STEPCHECK
REV
LAST EDIT
9/23/2008
TITLEDATE
PV
MCH_CANTIGA_GM_DDR2
1.0
Bremen-L3
CANTIGA (5/5)
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
16 59
PAGE
ELECTRONICS
BA41-xxxxxA
OF
8-16
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
DDR2 SO-DIMM #0
Height : 4mm (Standard)
3
2
1
8-17
D
C
B
A
DDR2M_SA00_MN
DDR2M_SA01_MN
MEM1_ADQ(63:0)
MEM1_AMA(14:0)
MEM1_ABS(2)
MEM1_ABS(0)
MEM1_ABS(1)
MEM1_CS0#
MEM1_CS1#
CLK1_MCLK0
CLK1_MCLK0#
CLK1_MCLK1
CLK1_MCLK1#
MEM1_CKE0
MEM1_CKE1
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
R846
R847
SMB3_CLK
SMB3_DATA
MEM1_ODT0
MEM1_ODT1
MEM1_ADM(7:0)
MEM1_ADQS(7:0)
MEM1_ADQS#(7:0)
4
14-D3
14-C4,17-D2
14-D4,17-C2
14-D4,17-C2
14-D4,17-C2
14-B4,17-C2
14-B4,17-C2
14-B4
14-B4
14-B4
14-B4
14-B4,17-C2
14-B4,17-C2
14-B4,17-C2
14-B4,17-C2
14-B4,17-C2
1%10K
1%10K
11-B4,18-B4 31-B4
11-B4,18-B4 31-B4
14-B4,17-C2
14-B4,17-C2
14-D4
14-C4
14-D4
DDR2M2-1
DDR2-SODIMM-200P-STD
1/2
0
102
A0
1
101
A1
2
100
A2
3
99
A3
4
98
A4
5
97
A5
6
94
A6
7
92
A7
8
93
A8
9
91
A9
10
105
A10_AP
11
90
A11
12
89
A12
13
116
A13
14
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
110
S0*
115
S1*
30
CK0
32
CK0*
164
CK1
166
CK1*
79
CKE0
80
CKE1
113
CAS*
108
RAS*
109
WE*
198
SA0
200
SA1
197
SCL
195
SDA
114
ODT0
119
ODT1
0
10
DM0
1
26
DM1
2
52
DM2
3
67
DM3
4
130
DM4
5
147
DM5
6
170
DM6
7
185
DM7
0
13
DQS0
1
31
DQS1
2
51
DQS2
3
70
DQS3
4
131
DQS4
5
148
DQS5
6
169
DQS6
7
188
DQS7
0
11
DQS*0
1
29
DQS*1
2
49
DQS*2
3
68
DQS*3
4
129
DQS*4
5
146
DQS*5
6
167
DQS*6
7
186
DQS*7
3709-001573|sodimm-200p-s-4-1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D
MEM1_AMA(14:0)
0
5
DQ0
1
7
DQ1
2
17
DQ2
3
19
DQ3
4
4
DQ4
5
6
DQ5
6
14
DQ6
7
16
DQ7
8
23
DQ8
9
25
DQ9
10
35
11
37
12
20
13
22
14
36
15
38
16
43
17
45
18
55
19
57
20
44
21
46
22
56
23
58
24
61
25
63
73
27
75
28
62
29
64
30
74
31
76
32
123
33
125
34
135
35
137
36
124
37
126
38
134
39
136
40
141
41
143
42
151
43
153
44
140
45
142
46
152
47
154
48
157
49
159
50
173
51
175
52
158
53
160
54
174
55
176
56
179
57
181
58
189
59
191
60
180
61
182
62
192
63
194
MEM1_VREF
P3.3V
C997
100nF
10V
14-D1,18-C3
C978
100nF
10V
C996
2200nF-X5R
10V
51-B1
P1.8V_AUX
C962
2200nF-X5R
10V
nostuff
DDR2M2-2
DDR2-SODIMM-200P-STD
2/2
112
VDD1
111
VDD2
117
VDD3
96
VDD4
95
VDD5
118
VDD6
81
VDD7
82
VDD8
87
VDD9
103
VDD10
88
VDD11
104
VDD12
199
VDDSPD
83
NC1
120
NC2
50
NC3
69
NC4
163
NCTEST
1
VREF
201
GND0
202
GND1
47
VSS1
133
VSS2
183
VSS3
77
VSS4
12
VSS5
48
VSS6
184
VSS7
78
VSS8
71
VSS9
72
VSS10
121
VSS11
122
VSS12
196
VSS13
193
VSS14
8
VSS15
3709-001573|sodimm-200p-s-4-1
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
MEM1_CS0#
MEM1_CS1#
MEM1_CKE0
MEM1_CKE1
MEM1_ODT0
MEM1_ODT1
MEM1_ABS(0)
MEM1_ABS(1)
MEM1_ABS(2)
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
P0.9V
C1009
100nF
10V
P1.8V_AUX
EC508
220uF
2.5V
AD
nostuff
14-C4,17-D4
0
R858
1
R832
2
R857
3
R831
4
R856
5
R830
6
R855
7
R854
8
R829
9
R827
10
R833
11
R853
12
R828
13
R863
14
R852
14-B4,17-C4
R861
14-B4,17-C4
R838
14-B4,17-C4
R825
14-B4,17-C4
R851
14-B4,17-B4
R862
14-B4,17-B4
R837
14-D4,17-C4
R834
14-D4,17-C4
R859
14-D4,17-C4
R826
14-B4,17-C4
R836
14-B4,17-B4
R860
14-B4,17-B4
R835
Place one cap close to every 2 pull-up resistors terminated to P0.9V
C981
C979
100nF
100nF
10V
10V
ME POWER RAIL UNDER ME ENABLE
C964
100nF
10V
C1005
100nF
10V
Place near SO-DIMM0
C1013
C993
2200nF-X5R
10V
2200nF-X5R
10V
C991
2200nF-X5R
10V
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
C1010
100nF
10V
C992
2200nF-X5R
10V
P0.9V
C1004
100nF
C1011
2200nF-X5R
10V
C1006
100nF
10V
nostuff26nostuff
nostuff
C994
100nF
10V
C1008
100nF
10V
C1012
100nF
10V
nostuff
C1007
100nF
10V10V
C990
10V
C1000
100nF
10V
C995
100nF100nF
10V
nostuff
C974
100nF
10V
nostuff
C980
100nF
10V
C
B
A
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
Jun PARK
YM.AHN
HJ.KIM
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
SODIMM_DDR2
SODIMM_DDR2 #1
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
17 59
PAGE
ELECTRONICS
BA41-xxxxxA
OF
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
R530/R730
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
DDR2 SO-DIMM #1
Height : 4mm (Reverse)
3
2
1
R530/R730
14-B1,18-D1
10K 1%
10K 1%
11-B4,17-B4
14-A1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14-B1,18-C1
14-B1,18-C1
14-B1,18-C1
14-D1,18-C1
14-D1,18-C1
14-C1
14-C1
14-C1
14-C1
14-C1,18-C1
14-C1,18-C1
14-D1,18-C1
14-D1,18-C1
14-D1,18-C1
14-D1,18-C1
14-C1,18-C1
14-C1
14-C1
14-C1
102
101
100
105
116
107
106
110
115
164
166
113
108
109
198
200
31-B4
197
31-B411-B4,17-B4
195
114
119
0
1
2
3
4
130
5
147
6
170
7
185
0
1
2
3
4
131
5
148
6
169
7
188
0
1
2
3
4
129
5
146
6
167
7
186
DDR2M1-1
DDR2-SODIMM-200P-RVS
1/2
A0
A1
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
A10_AP
90
A11
89
A12
A13
86
A14
84
A15
85
A16_BA2
BA0
BA1
S0*
S1*
30
CK0
32
CK0*
CK1
CK1*
79
CKE0
80
CKE1
CAS*
RAS*
WE*
SA0
SA1
SCL
SDA
ODT0
ODT1
10
DM0
26
DM1
52
DM2
67
DM3
DM4
DM5
DM6
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
DQS4
DQS5
DQS6
DQS7
11
DQS*0
29
DQS*1
49
DQS*2
68
DQS*3
DQS*4
DQS*5
DQS*6
DQS*7
3709-001572|sodimm-200p-r-1-1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
MEM1_BMA(14:0)
P1.8V_AUX
nostuff
112
111
117
96
95
118
81
82
87
103
88
104
199
83
120
50
69
163
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
DDR2M1-2
DDR2-SODIMM-200P-RVS
2/2
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
1
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
8
VSS15
3709-001572|sodimm-200p-r-1-1
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
P0.9V
C971
100nF
10V
MEM1_CS2#
MEM1_CS3#
MEM1_CKE2
MEM1_CKE3
MEM1_ODT2
MEM1_ODT3
MEM1_BBS(0)
MEM1_BBS(1)
MEM1_BBS(2)
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
C937
100nF
10V
P1.8V_AUX
EC507
C969
220uF
2200nF-X5R
2.5V
AD
10V
nostuff
0
5
DQ0
1
7
DQ1
2
17
DQ2
3
19
DQ3
4
4
DQ4
5
6
DQ5
6
14
DQ6
7
16
DQ7
8
23
DQ8
9
25
DQ9
10
35
11
37
12
20
13
22
14
36
15
38
16
43
17
45
18
55
19
57
20
44
21
46
22
56
23
58
24
61
25
63
26
73
27
75
28
62
29
64
30
74
31
76
32
123
33
125
34
135
35
137
36
124
37
126
38
134
39
136
40
141
41
143
42
151
43
153
44
140
45
142
46
152
47
154
48
157
49
159
50
173
51
175
52
158
53
160
54
174
55
176
56
179
57
181
58
189
59
191
60
180
61
182
62
192
63
194
MEM1_VREF
P3.3V
C942
100nF
10V
C941
2200nF-X5R
10V
C933
100nF
10V
51-B114-D1,17-C3
C944
2200nF-X5R
10V
14-B1,18-D4
14-D1,18-C4
14-D1,18-C4
14-C1,18-C4
14-C1,18-C4
14-D1,18-B4
14-C1,18-B4
14-B1,18-C4
14-B1,18-C4
14-B1,18-C4
14-D1,18-C4
14-D1,18-B4
14-D1,18-B4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R799
R779
R798
R778
R797
R777
R795
R796
R776
R775
R781
R793
R774
R803
R794
R802
R784
R773
R772
R804
R785
R780
R800
R792
R783
R801
R782
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
Place one cap close to every 2 pull-up resistors terminated to P0.9V
C939
100nF
10V
C935
100nF
10V
C973
100nF
10V
C965
100nF
10V
C963
100nF
10V
nostuff
C934
100nF
10V
nostuff
C938
100nF
10V
nostuff
Place near SO-DIMM1
C923
2200nF-X5R
10V
C921
2200nF-X5R
10V
C968
2200nF-X5R
10V
C970
100nF
10V
C967
100nF
10V
C920
2200nF-X5R
10V
C972
100nF
10V
C922
100nF
10V
nostuff
C940
100nF
10V
C919
100nF
10V
nostuff
C966
100nF
10V
P0.9V
D
MEM1_BDQ(63:0)
MEM1_BMA(14:0)
P3.3V
MEM1_BBS(2)
MEM1_BBS(0)
MEM1_BBS(1)
MEM1_CS2#
MEM1_CS3#
CLK1_MCLK2
CLK1_MCLK2#
CLK1_MCLK3
CLK1_MCLK3#
MEM1_CKE2
MEM1_CKE3
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
R807
R808
SMB3_CLK
SMB3_DATA
MEM1_ODT2
MEM1_ODT3
MEM1_BDM(7:0)
C
DDR2M_SA10_MN
DDR2M_SA11_MN
B
MEM1_BDQS(7:0)
MEM1_BDQS#(7:0)
A
DRAW
CHECK
APPROVAL
MODULE CODE
4
3
2
Jun PARK
YM.AHN
HJ.KIM
DATE
DEV. STEP
REV
LAST EDIT
9/23/2008
TITLE
PV
1.0
Bremen-L3
SODIMM_DDR2
SODIMM_DDR2 #2
October 27, 2009 14:27:43 PM
1
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-xxxxxA
nostuff
OF
C936
100nF
10V
D
C
B
A
5918
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
8-18
Loading...