SAMSUNG My-mp200 Special Circuit Descriptions

IC Internal Diagram

7. IC Internal Diagram

7-1 74LV245 ; SIC6

Philips Semiconductors	Product specification
Octal bus transceiver (3-State)	74LV245

FEATURES

•Wide operating voltage: 1.0 to 5.5 V

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

•Output capability: bus driver

•ICC category: MSI

DESCRIPTION

The 74LV245 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT245.

The 74LV245 is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. The

74LV245 features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	tPHL/tPLH	Propagation delay	CL = 15 pF;	7.0	ns
		An to Bn; Bn to An	VCC = 3.3 V
	CI	Input capacitance		3.5	pF
	CI/O	Input/output capacitance		10	pF
	CPD	Power dissipation capacitance per buffer	VCC = 3.3 V	40	pF
			VI = GND to VCC, note 1
	NOTE:
	1. CPD is used to determine the dynamic power dissipation (PD in W)
	PD = CPD	VCC2 fi ) (CL VCC2 fo) where:
	fi = input frequency in MHz; CL = output load capacitance in pF;
	fo = output frequency in MHz; VCC = supply voltage in V;
	(CL VCC2 fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
20-Pin Plastic DIL	–40°C to +125°C	74LV245 N	74LV245 N	SOT146-1
20-Pin Plastic SO	–40°C to +125°C	74LV245 D	74LV245 D	SOT163-1
20-Pin Plastic SSOP Type II	–40°C to +125°C	74LV245 DB	74LV245 DB	SOT339-1
20-Pin Plastic TSSOP Type I	–40°C to +125°C	74LV245 PW	74LV245PW DH	SOT360-1

PIN DESCRIPTION

PIN NUMBER		SYMBOL		FUNCTION
1		DIR		Direction
2, 3, 4, 5,		A0 to A7		Data inputs/outputs
6, 7, 8, 9
10		GND		Ground (0 V)
18, 17, 16, 15,		B0 to B7		Data inputs/outputs
14, 13, 12, 11
19				Output enable input (active LOW)
		OE
20		VCC		Positive supply voltage

FUNCTION TABLE

				INPUTS			INPUTS/OUTPUT
						DIR	An	Bn
			OE
			L			L	A = B	Inputs
			L			H	Inputs	B = A
			H			X	Z	Z
NOTES:
H	=		HIGH voltage level
L	=		LOW voltage level
X	=		don’t care
Z	=		high impedance OFF-state

1998 Apr 20

2

853–1931 19258

Samsung Electronics

7-1

IC Internal Diagram

Philips Semiconductors	Product specification
Octal bus transceiver (3-State)	74LV245
PIN CONFIGURATION	LOGIC SYMBOL

				1	DIR
DIR	1	20	VCC
					OE
						19
A0	2	19	OE
A1	3	18	B0	2	A0
					B0
A2	4	17	B1			18
					A1
A3	5	16	B2	3
					B1
						17
A4	6	15	B3
					A2
				4
A5	7	14	B4		B2	16
A6	8	13	B5	5	A3
					B3
A7	9	12	B6			15
GND	10	11	B7	6	A4
					B4
						14
		SV00624		7	A5
					B5
						13
LOGIC SYMBOL (IEEE/IEC)				8	A6
					B6	12
19
	G3				A7
1				9
					B7
	3EN1
						11
	3EN2					SV00625

	1
2	18
	2
3	17
4	16
5	15
6	14
7	13
8	12
9	11
	SV00626

1998 Apr 20

3

7-2	Samsung Electronics

IC Internal Diagram

7-2 74LV244 ; SIC7

Philips Semiconductors	Product specification
Octal buffer/line driver (3-State)	74LV244

FEATURES

•Wide operating voltage: 1.0 to 5.5 V

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

•Output capability: bus driver

•ICC category: MSI

DESCRIPTION

The 74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT244.

The 74LV244 is an octal non-inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable

inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LV244 is identical to the 74LV240 but has non-inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	Propagation delay	CL = 15 pF;
tPHL/tPLH	1An to 1Yn;	VCC = 3.3 V	8.0	ns
	2An to 2Yn
CI	Input capacitance		3.5	pF
CPD	Power dissipation capacitance per buffer	VCC = 3.3 V	35	pF
		VI = GND to VCC1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD	VCC2 fi ) (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
20-Pin Plastic DIL	–40°C to +125°C	74LV244 N	74LV244 N	SOT146-1
20-Pin Plastic SO	–40°C to +125°C	74LV244 D	74LV244 D	SOT163-1
20-Pin Plastic SSOP Type II	–40°C to +125°C	74LV244 DB	74LV244 DB	SOT339-1
20-Pin Plastic TSSOP Type I	–40°C to +125°C	74LV244 PW	74LV244PW DH	SOT360-1

PIN CONFIGURATION

			1
1OE						20	VCC
1A0
			2			19
							2OE
2Y0			3			18	1Y0
1A1			4			17	2A0
2Y1			5			16	1Y1
1A2			6			15	2A1
2Y2			7			14	1Y2
1A3			8			13	2A2
2Y3			9			12	1Y3
GND			10			11	2A3

LOGIC SYMBOL

2		1A0							1Y0	18
17		2A0							2Y0	3
4		1A1							1Y1	16
15		2A1							2Y1	5
6		1A2							1Y2	14
13		2A2							2Y2	7
8		1A3							1Y3	12
11		2A3							2Y3	9
1
		1OE
19
		2OE
									SV00621

SV00620

1998 May 20

2

853–1924 19420

Samsung Electronics

7-3

IC Internal Diagram

Philips Semiconductors	Product specification
Octal buffer/line driver (3-State)	74LV244

PIN DESCRIPTION

	PIN	SYMBOL			FUNCTION
	NUMBER
	1				Output enable input (active LOW)
		1OE
	2, 4, 6, 8	1A0 to 1A3			Data inputs
	3, 5, 7, 9	2Y0 to 2Y3			Bus outputs
	10	GND			Ground (0 V)
	17, 15, 13, 11	2A0 to 2A3			Data inputs
	18, 16, 14, 12	1Y0 to 1Y3			Bus outputs
	19				Output enable input (active LOW)
		2OE
	20	VCC			Positive supply voltage

LOGIC SYMBOL (IEEE/IEC)

1

EN

2				18
4				16
6				14
8				12
19
	EN
11
				9
13				7
15				5
17				3
			SV00666

FUNCTIONAL DIAGRAM

2	1A0	1Y0	18
4	1A1	1Y1	16
6	1A2	1Y2	14
8	1A3	1Y3	12
1	1OE
17	2A0	2Y0	3
15	2A1	2Y1	5
13	2A2	2Y2	7
11	2A3	2Y3	9
19	2OE
		SV00622

FUNCTION TABLE

				INPUTS			OUTPUT
		nOE				nAn	nYn
			L			L	L
			L			H	H
			H			X	Z
NOTES:
H	=	HIGH voltage level
L	=	LOW voltage level
X	=	don’t care
Z	=	high impedance OFF-state

1998 May 20

3

7-4	Samsung Electronics

IC Internal Diagram

7-3 DAC3550A ; IC2

DAC 3550A

Stereo Audio DAC

1. Introduction

The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping.

With MICRONAS INTERMETALL’s unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio has been achieved. The DAC 3550A is controlled via I2C bus.

Digital audio input data is received by a versatile I2S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3550A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported.

The DAC 3550A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, etc. The DAC 3550A ideally complements the MPEG 1/2 layer 2/3 audio decoder MAS 3507D.

No crystal required for standard applications with sample rates from 32 to 48 kHz. Crystal required only for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10), and use of clock output CLKOUT.

1.1. Main Features

–no master main input clock required

–integrated stereo headphone amplifier and mono speaker amplifier

–SNR of 103 dBA

–I2C bus, I2S bus

–internal clock oscillator

–full-feature mode by I2C control (three selectable subaddresses)

–reduced feature mode for non-I2C applications

–continuous sample rates from 8 kHz to 50 kHz

–analog deemphasis for 44.1 kHz

–analog volume and balance: +18… 75 dB and mute

–oversampling and multibit noise-shaping technique

–THD better than 0.01 %

–two additional analog stereo inputs (AUX) with source selection and mixing

–supply range: 2.7 V…5.5 V

–low-power mode

–additional line-out

–on-chip op amps for cost-effective external analog sound processing

Analog Inputs

WSI

Inter-

Input

Volume

OUTL

CLI

I2S

polation

DAC

Select

and

and

Headphone

Filter

OUTR

DRI

Mixing

Amplifier

Fig. 1–1: Block diagram of the DAC 3550A

Host

(PC, Controller)

ROM, CD-ROM,

RAM, Flash Mem. ..

demand signal

MPEG clock

MPEG bit stream

MAS	I2S			line out
		DAC

3550A

3507D

14.725 MHz

CLKOUT

Fig. 1–2: Typical application: MPEG Layer 3 Player

	MICRONAS INTERMETALL	3

Samsung Electronics

7-5

IC Internal Diagram

DAC 3550A

Sample Rate

Detection

PLL

CLKOUT 14

XTO 13

Osc.

XTI 12

AUX2L 29

AUX1L 31

DEEML 34

FOPL 38

FOUTL 37

FINL 39

CLI DAI WSI

23 24 25

I2S

Interpolation Filter

Variable S & H

3rd-order Noise Shaper

&

Multibit DAC

Analog Low-pass Filter

Input Select

Switch Matrix

Postfilter Op Amps

Deemphasis Op Amps

Line-Out

Analog Volume

Headphone Amplifier

					5						7
					OUTL						OUTR

					18			Vdd
	Digital Supply
					17			Vss
						9		AVDD0
					10			AVDD1
	Analog					3		AVSS0
						2
	Supply							AVSS1
					44			VREF
						1		AGNDC
					16			SDA
	I2C
					15			SCL
					27			TESTEN
					26			PORQ
	Control				21			DEECTRL
					19			MCS1
					20			MCS2
					32			AUX1R
					30			AUX2R
					35			DEEMR
					42			FOPR
					41			FOUTR
					43			FINR

Fig. 1–3: Block diagram of the DAC 3550A

	4	MICRONAS INTERMETALL

7-6	Samsung Electronics

IC Internal Diagram

DAC 3550A

2. Functional Description

2.1. I2S Interface

The I2S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats.

All modes have two common features:

Automatic Detection

No I2C control is required to switch between 16and 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16and 32-bit mode.

For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available).

1.The MSB is left justified to an I2S frame identification (WSI) transition.

2.Data is valid on the rising edge of the bit clock CLI.

16-bit mode

In this case, the bit clock is 32 × fsaudio. Maximum word length is 16 bit.

32-bit mode

In this case, the bit clock is 64 × fsaudio. Maximum word length is 32 bit.

Left-Right Selection

Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI.

Delay Bit

Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control.

Vh

CLI

Vl

Vh

DAI

Vl

Vh

WSI

Vl

Fig. 2–1:

Vh

CLI

Vl

	15 14 13 12 11 10							9	8	7		6		5	4			3	2	1	0	15 14 13 12 11 10				9	8	7		6	5		4	3	2	1			0
	programmable delay bit																						right 16-bit audio sample
				left 16-bit audio sample

I2S 16-bit mode (LR_SEL=0)

Vh

DAI

Vl

Vh

WSI

Vl

Fig. 2–2:

			31 30 29 28 27 26 25 24								7		6		5	4		3	2	1	0			31 30 29 28 27 26 25 24								7	6		5	4		3	2	1		0
			programmable delay bit
							left 32-bit				audio sample																	right 32-bit				audio sample
I2S 32-bit mode (LR_SEL=0)																								Note: Volume mute should be applied before changing
																										I2S mode in order to avoid audible clicks.

	MICRONAS INTERMETALL	5

Samsung Electronics

7-7