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SAMSUNG TFT-LCD
MODEL: LSF460HN02-A
Samsung Display Co., LTD
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Contents
Revision History ……………………………………………………………………………………………… .(3)
General Description ……………………………………………………………………………………………(4)
General Information ……………………………………………………………………………………………(4)
1. Absolute Maximum Ratings ……………………………………………………………………………….(5)
2. Optical Characteristics ……………………………………………………………………….....................(6)
3. Electrical Characteristics …………………………………………………………………………………….(11)
3.1 TFT LCD Module
4. Block Diagram ………………………………………………………………………………………………( 12)
5. Input Terminal Pin Assignment …………………………………………………………………………….(13)
5.1 Input Signal & Power
5.2 LVDS Interface
5.3 Input Signals, Basic Display Colors and Gray Scale of Each Color
6. Interface ………………………………………………………………………………………………………..(19)
6.1 Timing Parameters (DE only mode)
6.2 Characteristics of LVDS Input data
6.3 Timing Diagrams of interface Signal (DE only mode)
6.4 Power ON/OFF Sequence
7. Outline Dimension ………………………………………………………………….…………………….…..(23)
7.1 The adhesive size of POL
7.2 The drawing sheet for the size of the OLB bonding
7.4 Cross Section of cell
7.5 Source PCB
7.6 FFC cable
7.7 Control PCB
8. Reliability Test ………………………………………………………………………….…………………..…(24)
9. General Precaution ………………………………………………………………………………..….…..….(25)
9.1 Handling
9.2 Storage
9.3 Operation
9.4 Guide for the Operation Condition
9.5 Others
10. Special Precautions………………………………………………………………………………….……...(29)
11. Example ……………………………………………………………………………………………….……..(30)
Appendix1 ……………………………………………………………………………………………… .…….(31)
Appendix2 ……………………………………………………………………………………………….…….(35)
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Date
Rev. No
Page
Summary
19.Nov.2012
000
all
First Issue (First Draft)
28.Nov.2012
001
P.4
P.33
Change the tolerance of Panel size, the Panel mode
29.Nov.2012
002
P.29
P.13, 14
P.25
Change storage condition for packing
Change Input signal& power
Add drawing sheet for the size of the OLB bonding
07.Dec.2012
003
P.6
Change Gdiff. And Wx uni, Wy uni. spec
11.Dec.2012
004
P.4
P.13
Change Glass size tolerance, weight
Delete LVDS_SEL(Pin 45)
12.Dec.2012
005
P.5
P.6
Change Max Humidity for storage,Operating humidity
Change Gdiff, C/R min
The revision history
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General Description
Description
This model uses a liquid crystal display (LCD) of amorphous silicon TFT as switching components. This
model is composed of a TFT LCD panel, a driver circuit, and an ass’y KIT of source PBA. This 46.0”
model has a resolution of a 1920 x 1080 and can display up to 16.7 million colors with the wide viewing
angle of 89° or a higher degree in all directions. This panel is designed to support applications by
providing a excellent performance function of the flat panel display such as home-alone multimedia TFTLCD TV and a high definition TV.
General Information
Features
RoHS compliance (Pb-free)
High contrast ratio & aperture ratio with the wide color gamut
SVA(Super Vertical align) mode
Wide viewing angle (±178°)
High speed response
FHD resolution (16:9)
Low power consumption
DE (Data enable) mode
The interface (2pixel/clock) of 1ch LVDS (Low voltage differential signaling)
Items
Specification
Unit
Note
Active Display Area
1018.08(H) x 572.67(V)
㎜
Switching Components
a-Si TFT Active matrix
Glass Size
TFT : 1036.08(H) x 591.4(V)
CF : 1030.88(H) x 588.7(V)
mm
±0.4mm
Panel Size
1036.08(H) x 591.4(V)
mm
±0.4mm
1.80(D)
mm
±0.1mm
Weight
2,500
g
Display Colors
16.7M (True Display)
1.07B (Dithered 10bit)
color
Number of Pixels
1,920 × 1,080
pixel
16 : 9
Pixel Arrangement
RGB Vertical Stripe
Display Mode
Normally Black
Surface Treatment
AG-POL(Anti Glare),
Haze
2.3 %
±2.1%
Hardness
2H
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1. Absolute Maximum Ratings
If the figures on measuring instruments exceed maximum ratings, it can cause the malfunction or the
unrecoverable damage on the device.
Item
Symbol
Min.
Max.
Unit
Note
Power supply voltage
V
DD
10.8
13.2
V
(1)
Temperature for storage
T
STG
-20
65
℃
(2),(4)
Temperature of glass surface
T
OPR2
0
65 ℃ (2)
Operating temperature
T
OPR
0
50
℃
(2),(5)
Humidity for storage
H
STG
5
95
%RH
(2),(4)
Operating humidity
H
STG
20
95
%RG
(2),(5)
Endurance on static electricity
150
V
(3)
Note (1) The power supply voltage at Ta= 25 ± 2 °C
(2) Temperature and the range of relative humidity are shown in the figure below.
a. 90 % RH Max. (Ta ≤ 39 °C)
b. The relative humidity is 90% or less. (Ta ＞39 °C)
c. No condensation
d. Operating condition with SET
(3) Keep the static electricity under 150V in Polarizer attaching process.
(4) Operating condition with source PCB
(5) Storage temperature condition including glass
(6) Condition without packing. (Unpacking condition)
Fig. Range for temperature and relative humidity
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2. Optical characteristics
The optical characteristics should be measured in the dark room or the space surrounded by the similar
setting.
Measuring equipment : TOPCON RD-80S, TOPCON SR-3 ,ELDIM EZ-Contrast
(Ta = 25 ± 2°C, VDD=12.0V, fv=60Hz, f
DCLK
=148.5MHz, Light source: D65 Standard light)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Light Source
Note
Contrast ratio
(At the center of screen)
C/R
-
5,000
-
Standard
(1)
SR-3
Response
time
G-to-G
Tg
T
PAN,SUR
=29.9℃
- 8 16
msec
Standard
or
VD BLU
(3)
RD-80S
Luminance of white
(At the center of screen)
YL
Normal
qL,R=0
qU,D=0
Viewing
Angle
TBD
TBD
-
cd/m2
VD BLU
(4)
SR-3
Chromaticity
(CIE 1931)
Red
Rx
TYP.
-0.03
0.640
TYP.
+0.03
VD BLU
(5),(6)
SR-3
Ry
0.330
Green
Gx
0.300
Gy
0.600
Blue
Bx
0.150
By
0.060
White
Wx
0.280
Wy
0.290
sRGB Concordance
-
99 %
(5)
SR-3
Color gamut
- - 72 - %
VD BLU
Color
-
7,000
10,000 - K
Viewing
Angle
Hor.
qL
C/R≥10
75
89
-
Degree
Standard
or
VD BLU
(6)
SR-3
EZ-Contrast
qR
75
89
-
Ver.
qU
75
89
-
qD
75
89
-
Brightness uniformity
(9 Points)
B
uni
-
-
TBD
%
Standard
(2)
SR-3
Transmissivity
T
5.49
5.90 - %
Standard
(7)
D65/SR3
Transmissivity Uniformity
T
uni
- - 10
%
Standard
(8)
D65/SR3
Gamma Value
GMA
2.0
2.2
2.4
Standard
or
VD BLU
(9)
SR-3
Gamma variation
Gdiff
(@20G~128G)
-0.14
-
0.14
(11)
SR-3
ACC Linearity
ACC_lin
-0.015
0.0
0.015
Standard
or
VD BLU
(12)
SR-3
5nit Uniformity
Buni_5nit
-30
0.0
30
%
Standard
(38G/255G)
(10)
SR-3
White Color Coordinate
Uniformity
Wx uni
-
0.005
Standard
(13)
SR-3
Wy uni
0.008
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Notice
(a) Setup for test equipment
The measurement should be executed in a stable, windless, and dark room for 40min and 60min after
operating the panel at the given temperature for stabilization of the standard light. (SDC uses the standard
luminance of the D65 media).
This measurement should be measured at the center of screen.
The environment condition: Ta = 25 ± 2 °C
(b) D65 media has the general light source.
The temperature of color is 6847K. The coordinate of color is Wx 0.313, Wy 0.329
The luminance of this product is 7217cd/㎡.
Photo detector
Field
SR-3
2°/1°
RD-80S
1°
(c) The CIE positions D65 as the standard daylight illuminant:
[D65] is intended to represent average daylight and has a correlated color temperature of
approximately 6500 K. CIE standard illuminant D65 should be used in all colorimetric calculations
requiring representative daylight, unless there are specific reasons for using a different illuminant.
- Definition of the test point
Note (1) Definition of contrast ratio (C/R)
: The ratio of gray max (Gmax) & gray min (Gmin) at the center point ⑤ of the panel
The measurement goes in D65 Standard light source
Gmax : The luminance with all white pixels
C R
G
G
/
max
min
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Gmin : The luminance with all black pixels
Note (2) Definition of the brightness uniformity of 9 points (Test pattern : The full white)
The measurement shall be executed with the standard light source of D65 .
Bmax : The maximum brightness
Bmin : The minimum brightness
Note (3) Definition of the response time : Sum of Tr, Tf
※ G-to-G : Average response time between whole gray scale to whole gray scale.
The response time is the value that was measured after it was operated in Samsung's standard BLU for
one hour.( at room temperature)
Note (4) The definition of luminance of white: The luminance of white at the center point ⑤
The measurement shall be executed with the standard light source of D65.
Note (5) The definition of chromaticity (CIE 1931)
The color coordinate of red, green, blue and white at the center point ⑤
The measurement shall be executed with the standard light source of D65.
Note (6) Definition of viewing angle
: The range of viewing angle (C/R ≥10)
The measurement shall be executed with the standard light source of D65.
The response
Of optical instruments
Buni
B B
B
100
( max min)
max
Display data
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Tuni
= 100*
Gamma Value
- 20 ~ 200Gray: 2.2 ±0.2
Buni_5nit
= 100*
Bmax_5nit : The maximum brightness at 5nit Gray
Bmin_5nit : The minimum brightness at 5nit Gray
Vertical 1/6 Point
[Panel Measure Point]
Vertical 1/6 Point
Note (7) Definition of transmissivity
The measurement shall be executed with the standard light source of D65.
Note (8) Definition of the Transmissivity uniformity of 9 points (Test pattern: The full white)
The measurement shall be executed with the standard light source of D65.
Tmax : The maximum Transmissivity
Tmin : The minimum Transmissivity
Note (9) Management Criteria of Gamma Value
Note (10) 5nit Low Gray Uniformity
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255Gray Wx/Wy value basis (a module unit basis)
a. Color coordinate differences are less than 15/1,000 at
Any Point above 30Gray and 255Gray
b. When Wx/Wy coordinates reverse at 0Gray, it permits
an once intersection under, 30Gray
Wx, uni
= Wx max-Wx min
Wx max : The maximum Wx
Wx min : The minimum Wx
Wy, uni
= Wy max-Wy min
Wy max: The maximum Wy
Wy min: The minimum Wy
Note (11) Gamma Variation between Center and Left (or Right)
Gamma measured at 10cm point from the left & right side is more less than 0.14 than Gamma
measured at Center
(Gamma measured at 10cm of the P-4 & P-6 is more less than 0.1 than Gamma measured at P-5)
Note (12) Management Criteria of ACC Linearity
Note (13) White Color Coordinate Uniformity of 9 points (Test pattern: The full white)
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3. Electrical characteristics – Sony Model Attached Reference file
3.1 TFT LCD Module
The connector for the display data & timing signal should be connected.
Ta = 25°C ± 2 °C
Item
Symbol
Min.
Typ.
Max.
Unit
Note
Voltage of power supply
V
DD
10.8
12.0
13.2
V
(1)
Current
of power
supply
(a) Black
I
DD
-
500
700
mA
(2),(3)
(b) White
-
500
750
mA
(c) Sub V-Stripe
-
800
1100
mA
Vsync frequency
f
V
48
60
66
Hz Hsync frequency
f
H
54
67.5
74.25
kHz Main frequency
Fdclk
118.8
148.5
163.35
MHz Rush current
I
RUSH
- - 2
A
(4)
Note (1) The ripple voltage should be controlled fewer than 10% of V
DD
(Typ.) voltage.
(2) fV=60Hz, fDCLK =148.5MHz, VDD = 12.0V, DC Current.
(3) Power dissipation check pattern (LCD Module only)
(4) Conditions for measurement
a) Black pattern b) White pattern c) Sub V-stripe
The rush current, I
RUSH
can be measured during T
RUSH
is 470us
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4. Block diagram
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5. The Pin assignment in the input terminal
5.1. Input signal & power Connector : FI-RE51S-HF (JAE/UJU)
Pin
Description
Pin
Description
1
Vdd (12V)
26
Even
LVDS
Signal
RE[0]P 2 Vdd (12V)
27
RE[1]N 3 Vdd (12V)
28
RE[1]P 4 Vdd (12V)
29
RE[2]N 5 Vdd (12V)
30
RE[2]P 6 No connection
31
GND 7 GND
32
RECLK- 8 GND
33
RECLK+ 9 GND
34
GND
10
Odd
LVDS
Signal
RO[0]N
35
RE[3]N
11
RO[0]P
36
RE[3]P
12
RO[1]N
37
RE[4]N
13
RO[1]P
38
RE[4]P
14
RO[2]N
39
GND
15
RO[2]P
40
No connection
NOTE1
16
GND
41
No connection
17
ROCLK-
42
No connection
18
ROCLK+
43
No connection
19
GND
44
No connection
20
RO[3]N
45
No connection
21
RO[3]P
46
No connection
22
RO[4]N
47
No connection
23
RO[4]P
48
No connection
24
GND
49
No connection
25
Even LVDS
RE[0]N
50
No connection
51
Aging EN
NOTE2
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Note (1) Pin number which starts from the left side.
a. Power GND pins should be connected to the LCD’s metal chassis.
b. All power input pins should be connected together.
c. All NC pins should be separated from other signal or power.
Note(3) Aging Enable PIN / IF this Pin GND → BIST MODE (Rolling Pattern is operated)
Fig . The diagram of connector
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5.2 LVDS Interface
- LVDS receiver : T-con (merged) ( 8Bit)
- Data format
LVDS pin
JEIDA -DATA
Normal-DATA
TxOUT/RxIN0
TxIN/RxOUT0
R2
R0
TxIN/RxOUT1
R3
R1
TxIN/RxOUT2
R4
R2
TxIN/RxOUT3
R5
R3
TxIN/RxOUT4
R6
R4
TxIN/RxOUT6
R7
R5
TxIN/RxOUT7
G2
G0
TxOUT/RxIN1
TxIN/RxOUT8
G3
G1
TxIN/RxOUT9
G4
G2
TxIN/RxOUT12
G5
G3
TxIN/RxOUT13
G6
G4
TxIN/RxOUT14
G7
G5
TxIN/RxOUT15
B2
B0
TxIN/RxOUT18
B3
B1
TxOUT/RxIN2
TxIN/RxOUT19
B4
B2
TxIN/RxOUT20
B5
B3
TxIN/RxOUT21
B6
B4
TxIN/RxOUT22
B7
B5
TxIN/RxOUT24
HSYNC
HSYNC
TxIN/RxOUT25
VSYNC
VSYNC
TxIN/RxOUT26
DEN
DE
TxOUT/RxIN3
TxIN/RxOUT27
R0
R6
TxIN/RxOUT5
R1
R7
TxIN/RxOUT10
G0
G6
TxIN/RxOUT11
G1
G7
TxIN/RxOUT16
B0
B6
TxIN/RxOUT17
B1
B7
TxIN/RxOUT23
RESERVED
RESERVED
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5.3 Input signals, basic display colors and the gray scale of each color. (8bit))
COLOR
DISPLAY
(8bit)
DATA SIGNAL
GRAY
SCALE
LEVEL
RED
GREEN
BLUE
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
BASIC
COLOR
BLACK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
BLUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-
GREEN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
-
CYAN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
RED
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
MAGENTA
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-
YELLOW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
-
WHITE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
GRAY
SCALE
OF
RED
BLACK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R0
DARK
↑
↓
LIGHT
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
R3~
R252
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R253
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R254
RED
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R255
GRAY
SCALE
OF
GREEN
BLACK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G0
DARK
↑
↓
LIGHT
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
G3~
G252
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
G253
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
G254
GREEN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
G255
GRAY
SCALE
OF
BLUE
BLACK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0
DARK
↑
↓
LIGHT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
B2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
B3~
B252
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
B253
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
B254
BLUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B255
Note) The definition of gray :
Rn : Red gray, Gn : Green gray, Bn : Blue gray (n = Gray level)
Input signal : 0 = Low level voltage, 1 = High level voltage
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5.4 LVDS receiver : T-con (merged) (10Bit)
- Data format
LVDS pin
JEIDA -DATA
Normal -DATA
TxOUT/RxIN0
TxIN/RxOUT0
R2
R0
TxIN/RxOUT1
R3
R1
TxIN/RxOUT2
R4
R2
TxIN/RxOUT3
R5
R3
TxIN/RxOUT4
R6
R4
TxIN/RxOUT6
R7
R5
TxIN/RxOUT7
G2
G0
TxOUT/RxIN1
TxIN/RxOUT8
G3
G1
TxIN/RxOUT9
G4
G2
TxIN/RxOUT12
G5
G3
TxIN/RxOUT13
G6
G4
TxIN/RxOUT14
G7
G5
TxIN/RxOUT15
B2
B0
TxIN/RxOUT18
B3
B1
TxOUT/RxIN2
TxIN/RxOUT19
B4
B2
TxIN/RxOUT20
B5
B3
TxIN/RxOUT21
B6
B4
TxIN/RxOUT22
B7
B5
TxIN/RxOUT24
HSYNC
HSYNC
TxIN/RxOUT25
VSYNC
VSYNC
TxIN/RxOUT26
DEN
DE
TxOUT/RxIN3
TxIN/RxOUT27
R0
R6
TxIN/RxOUT5
R1
R7
TxIN/RxOUT10
G0
G6
TxIN/RxOUT11
G1
G7
TxIN/RxOUT16
B0
B6
TxIN/RxOUT17
B1
B7
TxIN/RxOUT23
RESERVED
RESERVED
TxOUT/RxIN4(dithered10b
it)
TxIN/RxOUT28
R0
R8
TxIN/RxOUT29
R1
R9
TxIN/RxOUT30
G0
G8
TxIN/RxOUT31
G1
G9
TxIN/RxOUT32
B0
B8
TxIN/RxOUT33
B1
B9
TxIN/RxOUT34
RESERVED
RESERVED
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5.5 Input signals, basic display colors and the gray scale of each color. (10bit)
COLOR
DISPLAY
DATA SIGNAL
GRAY
SCALE
LEVEL
RED
GREEN
BLUE
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BASIC
COLOR
BLACK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
BLUE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 -
GREEN
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 -
CYAN
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
RED
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
MAGENTA
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 -
YELLOW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 -
WHITE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
GRAY
SCALE
OF RED
BLACK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0
DARK
↑
↓
LIGHT
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
:
R3~
R1020
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
:
1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1021
0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1022
RED
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1023
GRAY
SCALE
OF
GREEN
BLACK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G0
DARK
↑
↓
LIGHT
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G1
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G2
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
:
G3~
G1020
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 G1021
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 G1022
GREEN
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 G1023
GRAY
SCALE
OF
BLUE
BLACK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0
DARK
↑
↓
LIGHT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 B1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 B2
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
:
B3~
B1020
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 B1021
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 B1022
BLUE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 B1023
Note) The definition of gray :
Rn : Red gray, Gn : Green gray, Bn : Blue gray (n = Gray level)
Input signal : 0 = Low level voltage, 1 = High level voltage
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6. Interface timing
6.1 The parameters of timing ( Only DE mode )
SIGNAL
ITEM
SMBOL
MIN.
TYP.
MAX.
Unit
NOTE
Clock
Frequency
1/T
C
130
148.5
160
MHz
-
Hsync
F
H
48
67.5
75
KHz
-
Vsync
F
V
48
60
65
Hz
-
Term for the
vertical
display
Active
display
period
T
VD
-
1080
-
Lines
-
Total vertical
T
V
1092
1125
1380
Lines
-
Term for the
horizontal
display
Active
display
period
T
HD
-
1920
-
Clocks
-
Total
Horizontal
T
H
2090
2200
2350
clocks
-
Note) These products don’t have to receive the signal of Hsync & Vsync from the input device.
(1) Key points when testing: TTL controls the signal and the CLK at the input terminal of LVDS Tx of the
system.
(2) Internal VDD = 3.3V
(3) Spread spectrum
- The limit of spread spectrum's range of SET in which the LCD module is assembled should be within ± 3 %.
TxOUT/RxIN4(dithered10bit)
TxIN/RxOUT28
R0
R8
TxIN/RxOUT29
R1
R9
TxIN/RxOUT30
G0
G8
TxIN/RxOUT31
G1
G9
TxIN/RxOUT32
B0
B8
TxIN/RxOUT33
B1
B9
TxIN/RxOUT34
RESERVED
RESERVED
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6.2 Timing diagrams of interface signal (Only DE mode )
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6.3 Characteristics of Input data of LVDS
ITEM
SYMBOL
Min.
Typ.
Max.
UNIT
NOTE
Differential input high
threshold voltage
VTH
-
-
+100
mV
V
CM
= 1.2V
Differential input low
threshold voltage
VTL
-100 - -
mV
Input common mode voltage
V
CM
0.3
-
1.8 V -
Differential Input Voltage
|V
ID
|
100
350
600
mV
|V
ID
|=100mV
Input data position
F
IN
=80MHz
t
RSRM
- - 400
ps
t
RSLM
-400
-
ps
Notice The spread spectrum should be 0% when the skew is measured.
Position of a measurement is T-CON LVDS input pin
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LVDS Channel to Channel Skew (T-chskw) in Multiple LVDS Channels
Note: DE should be synchronized with DE per each LVDS Channel and T-chskw < 16 * LVDS Clock Period
LVDS Clock to Data Skew (T
RSRM
& T
RSLM
) at each LVDS Channel
RINCLK
(LVDS CLK)
RIN
(LVDS Data)
Rx
Internal
Strobe
Window
T
RSRM
T
RSLM
RIN
(LVDS Data)
Symbol
Characteristics
Min.
Typ.
Max.
Unit
T
RSRM
Input Data Position
LVDS CLK = 85MHz
400
ps LVDS CLK = 78MHz
450
ps
LVDS CLK = 75MHz
500
ps
T
RSLM
Input Data Position
LVDS CLK = 85MHz
400
ps
LVDS CLK = 78MHz
450
ps
LVDS CLK = 75MHz
500
ps
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6.4 The sequence of power on and off – Sony Model attached Reference file
To prevent a latch-up phenomena or the DC operation of the LCD Module, the power on/off sequence should
be accorded with the settings described in the diagram below.
T1 : The VDD rising time from 10% to 90%
T2 : The time from the point which V
DD
reach to 90% of voltage to the point which the valid data is out when
the power is on.
T3: The time from the point which the valid data is out to the point which VDD reach to the 90% of voltage
when the power is off.
T4: the time from the point which the Vdd decrease to the point which the Vdd increase again for windows to
restart.
※ The recommended operating condition of the back light system
T5: The time which takes for B/L to be turned on after the signal is entered when the time is on.
T6 : The time which takes until the signal is out after BL is turned off
The condition of supply voltage to enter in the module from the external system should have
the same condition as the definition of VDD.
Apply the voltage for the lamp within the range which the LCD operates. when the back light is turned on
before the LCD is operated or when the LCD is turned off before the back light is turned off, the display may
show the abnormal screen momentarily.
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While the V
DD
is off level, please keep the level of input signals low or keep a high impedance condition.
The figure of T4 should be measured after the module has been fully discharged between the periods
when the power is on and off.
The interface signal must not keep the high impedance condition when the power is on.
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7. Outline dimension
7.1 The adhesive size of POL
The next figure shows the size of POL on the drawing sheet attached to the panel for BLU design.
<Figure.>
The POL size of CF : 1029.28 X 586.25 ± 0.2mm
The POL size of TFT: 1028.88 X 586.25 ± 0.2mm
The total adhesion allowance of POL is ±0.8㎜(L/R), ±1.15㎜(U/D)
7.2 The drawing sheet for the size of the OLB bonding
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8. Reliability test
8.1 Panel
Item
Test Condition
Quantity
Note
HTOL
60 ℃ (Panel change 500hr / circuit change 250hr)
8
LTOL
-5 ℃ (Panel change 500hr / circuit change 250hr)
4
THB
50 ℃ / 90 %RH(Panel change 500hr / circuit change 250hr)
10
Image sticking
25 ℃ / Mosaic pattern(9*10) 12hrs
8
Rolling pattern 12hrs / 3cycles
Decompressio
n
-40~50℃, 0m(0ft) ~ 13,700m(45,000ft), 72.5Hr
4
HTS
70 ℃, Storage (Panel change 500hr / circuit change 250hr)
4
LTS
-25 ℃, Storage(Panel change 500hr / circuit change 250hr)
4
Transportation
condition
drop(20cm) → temperature/humidity(-30~60℃ / 40℃ 90%RH)
→ pressure → vibration(5~200Hz 1.05Grms, 2hr) → drop(20cm)
1pallet
WHTS
60 ℃ / 75 %RH , Storage
4
Noise
Electromagnetic noise: Overall 23dB 이하
2
Complex
stress
-20℃~60℃, 0~90%RH, 2cycle
4
ESD
S-IC Input ±7KV, Output ±4KV
Output 은 data TP 에 직접 인가 후 진행
Input 은 CKV,VCOM 등에 FFC CNT 를 통하여 TEST 를 진행
3
EOS (optional)
Item
Test condition
Vin Input
step
Surge combination (High impedance)
Pass Condition: 5kV under
Signal Input
step
Surge combination (High impedance)
Pass Condition: 120V under
2
[ Criteria on evaluation]
There should be no change of the product, which may affect to the practical display functions, when the
display quality test is executed under the normal operation setting.
* HTOL/ LTOL : The operating cycle on the high and low temperature
* THB : Temperature humidity slant
* HTS/LTS : The storage at the high and low temperature
* WHTS : The storage in the high temperature with the high humidity
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9. General precautions
9.1 Handling
(a) When the panel kit and BLU kit are assembled, the panel kit and BLU kit should be attached to the
set system firmly by combining each mounted holes. Be careful not to give the mechanical stress.
(b) Be careful not to give any extra mechanical stress to the panel when designing the set, and BLU kit.
(c) Be cautious not to give any strong mechanical shock and / or any to the panel kit.
Applying the any to the panel may cause the abnormal operation or the damage to the panel kit and
the back light unit kit.
(d) Refrain from applying any to the source PBA and the drive IC in the process of the handling
or installing to the set. If any are applied to the products, it may cause damage or a malfunction in the
panel kit.
(e) Refrain from applying any which cause a constant shock to the back side of panel kit, the set
design and BLU kit. If any are applied to the products, it may cause an abnormal display, a functional
failure and etc.
(f) Note that polarizer could be damaged easily.
Do not press or scratch the bare surface with the material which is harder than a HB pencil lead.
(g) Wipe off water droplets or oil immediately. If you leave the droplets for a long time on the product, a
staining or the discoloration may occur.
(h) If the surface of the polarizer is dirty, clean it using the absorbent cotton or the soft cloth.
(i) Desirable cleaners are water or IPA (Isopropyl Alcohol).
Do not use Kenton type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride.
These might cause the permanent damage to the polarizer due to chemical reaction.
(j) If the liquid crystal material leaks from the panel, this should be kept away from the eyes or mouth.
If this contacts to hands, legs, or clothes, you must washed it away with soap thoroughly and see a
doctor for the medical examination.
(k) Protect the panel kit and BLU Kit out of the static electricity. Otherwise the circuit IC could be
damaged.
- Reference : Process control standard of SDC
No.
Item
Control standard
1
Ionizer
All Equipment should be controlled under 150V.(Typ. 100V)
2
Carrying Roller
Carrying Roller should be controlled under 200V.
3
Equipment Ground
Resistance
All Equipment Ground Should be less than 1ohm.
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(l) Remove the stains with finger-stalls wearing soft gloves in order to keep the display clean in the
process of the incoming inspection and the assembly process.
(m) Do not pull or fold the source drive IC which connects to the source PBA and the panel or the gate
drive IC.
(n) Do not pull, fold or bend the source drive IC and the gate drive IC in any processes.
If not, the source drive IC could be bent one time in the process of assembling the panel Kit and the
BLU Kit.
(o) Do not adjust the variable resistor located on the panel kit and BLU kit except when adjusting the
flicker.
(p) Do not touch the pins of the interface connector directly with bare hands.
(q) Be cautious not to be peeled off the protection film.
(r) The protection film for the polarizer on the panel kit should be slowly peeled off just before using so
that the electrostatic charge can be minimized.
(s) The panel kit and BLU kit have high frequency circuits. The sufficient suppression to the EMI should
be done by the set manufacturers.
(t) The set of which the panel is assembled shall not be twisted. If the product is twisted, it may cause
the damage on the product.
(u) Surface Temp. of IC should be controlled less than 100℃, operating over the Temp. can cause the
damage or decrease of lifetime.
- Make sure to peel off slowly
(It is recommended to peel it off at the speed of more than 8sec.
constantly.)
- The peeling direction is shown at the Fig
- Instruct the ground worker to work with the adequate methods
such as the antistatic wrist band.
- Maker sure to be grounded the source PBA while peeling of the
protection film.
- Ionized air should be blown over during the peeling
- The protection film should not t be contacted to the source drive
IC.
- If the adhesive stains remain on the polarizer after the
protection film is peeled off, please move stains with isopropylalcohol liquid.
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9.2 Storage
The storage condition for packing
ITEM
Unit
Min.
Max.
Storage
Temperature
(℃)
5
40
Storage
Humidity
(%rH)
35
75
Storage life
12 months
Based on shipping date at SDC site
Storage
Condition
(1) Design the warehouse to be ventilated efficiently with equipping the roof, the
ventilation system, and the temp. controller.
(2) Don't load the product on the floor and store the product with loaded on the pallet
placed far away from the wall.
(3) Avoid exposing the product to the direct light, moisture, and water and prevent the
product from being condensed.
(4) Don't store the product at the container located outside where it rains and the
direct light shines.
(5) Prevent the product from being exposed to the noxious gas such as the acid gas or
alkali
gas which may damage the electric device.
(6) Don't store the product at the location surrounded by dangerous factors, which can
deteriorate the quality of product.
9.3 Operation
(a) Do not connect or disconnect the FFC cable during the "Power On" condition.
(b) Power supply should be always turned on and off by the "Power on/off sequence"
(c) The module has high frequency circuits. The sufficient suppression to the electromagnetic interference
should be done by the system manufacturers. The grounding and shielding methods is important to
minimize the interference.
(d) The cables between TV SET connector and Control PBA interface cable should be connected directly
to have a minimized length. A longer cable between TV SET connector and Control PBA interface
cable maybe operate abnormal display
(e) Recommend to age for over 1 hour at least in the state, which the product is driving initially to stabilize
the characteristic of the initial TFT.
(f) Response time depends on the temperature.( In Lower temperature, it becomes longer)
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9.4 Operation condition guide
(a) The LCD product shall be operated under normal conditions.
The normal condition is defined as below;
- Temperature : 20±15℃
- Humidity : 55±20%
- Display pattern : continually changing pattern (Not stationary)
(b) If the product will be used under extreme conditions such as under the high temperature, humidity,
display patterns or the operation time etc.., it is strongly recommended to contact SDC for the
advice about the application of engineering . Otherwise, its reliability and the function may not be
guaranteed. Extreme conditions are commonly found at airports, transit stations, banks, stock
markets, and controlling systems.
9.5 Others
(a) The ultra-violet ray filter is necessary for the outdoor operation.
(b) Avoid the condensation of water which may result in the improper operation of product or the
disconnection of electrode.
(c) Do not exceed the limit on the absolute maximum rating. (For example, the supply voltage
variation, the input voltage variation, the variation in content of parts and environmental
temperature, and so on) If not, panel may be damaged.
(d) If the module keeps displaying the same pattern for a long period of time, the image may be
remained to the screen. To avoid the image sticking, it is recommended to use a screen saver.
(e) This Panel has its circuitry of PCB's on the rear side, so it should be handled carefully in order for a
not to be applied.
(f) Please contact the SDC in advance when the same pattern is displayed for a long time
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10. Special precautions
10.1 Lists to be cautious when executing the design process
No.
Component
Expected cause
1
Upholding part for
panel
Prevent the panel from breaking by assigning gaps between the panel and the upholding part for panel on the drawing
for the upholding part for panel.
Refer to the (a), (b), (c) of 3-1 for the design of BLU.
2
The shape of the
upholding part for
panel
Design the upholding part for panel to fit to the panel appropriately when designing the BLU since the shape of the
upholding part for panel may damage the panel.
Refer to the (a), (b), (c) of 3-1 for the design of BLU.
3
The edge of
upholding part for
panel
Design the edge of panel to have a sufficient space with the upholding part for panel when designing the BLU since the
edge of the upholding part for panel may damage the panel when assembling the panel and BLU.
Refer to the (a), (b), (c) of 3-1 for the design of BLU.
4
Upholding part for
panel
Place the upholding part for the panel in order for the shape of mold, which contacts with the panel not to interfere with
the area of panel.
Refer to the (a), (b), (c) of 3-1 for the design of BLU.
5
Drive IC
Design the BLU in order for the COF not to contain the lead crack resulted from the tensioned COF created when the
product is twisted if the space between the D-IC COF and the middle mold isn't sufficient.
Refer to the (a), (b), (c),(d),(e),(f), and (g)of 3-2 for the design of BLU.
6
Drive IC
Design the BLU in order for the product not to contain the lead crack resulted from the tensioned COF caused under the
condition, which the product is twisted by fixing the source PCB.
Refer to the (a), (b), (c),(d),(e),(f), and (g)of 3-2 for the design of BLU.
7
IC
component
1) The temperature of each part of product suggested by our company and the second vendor shall meet the standard
of temperature, which is recommended not to be exceeded by our company when the product is affected under the
various temperature ranges.
Apply over 1mm long separation distance stated in the safety standard between the electric part and each conductor.
(Apply the rated separation distance when insulating.)
8
Thermal pad
Apply the thermal pad in a designated size to the product as a measure to lower the temperature of heat in order for
each part to use the rated temperature.
9
POL
The surrounding area of the POL shall be treated with an electrification treatment since the external ESD may cause a
phenomenon, which the POL is coming off.
In addition, the GND portion of source PBA shall be grounded.
10
PBA
The GND portion of each PBA shall be contacted with the GND portion of BLU.
Refer to the (a) and (b) of 3-3 for the design of BLU.
11
Circuit
The standardized approval from the client is required since the EMI is executed by a client.
Our company can only measure the reference since the client measures the BLU.
12
The height of
component
Design the BLU with considering the maximum height of parts, which our company suggests.
13
Between the FFC
and the C-PBA
Design the instrument with considering the length between the FFC and the control PBA.
(The marginal minimum length of 5mm or 8mm is required.)
14
Panel
The surface temperature of panel shall be maintained within 0℃ and 45℃ when the external ambient temperature is at
25℃. (Design the BLU with considering the increase of the temperature in the panel by the LED, CCFL, and etc.)
15
Aging
Recommend to age for over 1 hour at least in the state, which the product is driving initially to stabilize the characteristic
of the initial TFT.
16
The attachment of
gasket
The additional confirmation by our company is required If the attachment of gasket to the S-PBA of our company is
required.(To fix the S-PBA or the EMI)
17
Drive IC
Design the top chassis and the driver IC to be contacted by placing the shape of emboss inside the top chassis as a
measure to prevent the driver IC from heating. The size of emboss shall be designed in larger size than the size of IC
inside the film of the driver IC.
Refer to the (a), (b), (c),(d),(e),(f), and (g)of 3-2 for the design of BLU.
18
The prohibited
bandwidth
Design the BLU in order for the BLU not to interfere with the area, where the control PBA and the source PBA are
located densely according to the drawing for the BLU from our company.
19
S-PBA
The material, which contacts with the bottom side of S-PBA which has a pattern shall be non-conducting material or
shall be insulated.
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11. Example
. The length between the FFC and the C-PBA
. The grounding of PCB
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Appendix
Recommendation for the BLU Design
The Information described in this specification is for the first draft and can be changed without prior notice
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1. The schematic of panel
Item
Symbol
Remark
Protector Film
①
Removable
Polaroid Film
②
Color Filter Glass
③
TFT Glass
④
Source IC
⑤
Gate IC
⑥
Source PBA
⑦
FFC
⑧
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3. The guide for the mechanical design
3.1 The panel guide
(a) It is recommended to avoid the following cases since the light leakage can be caused by the
pressure of the guiding structure.
When the guiding part is made of plastic resin, the gap between the panel and the guiding structure
should be considered when you design. The shrinkage under the situation which the temperatures
change causes the light leakage. For your reference, it is recommended to have a total gap between
the panel and the guide structure as below (When the resin is composed of the PC and the 15% of
G/F.)
tꀀሄ
32”
40”
46”
55”
Total Gap
Right & Left
0.9
0.9
1.0
1.1
Top & Bottom
0.6
0.7
0.8
0.9
It is recommended to follow the dimension and the shape of the guiding structure stated as below
since the distortion of guiding parts can cause the light leakage
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(b) When the panel guide point is designed at the edge of the panel, the points in the corner shall not be
designed to be contacted with the other parts in order to avoid the crack on the panel caused by the
burr of the panel.
(c) It is recommended to avoid placing the ribs as shown below since the panel damage with the unstable
design can be easily happened under the external
-. The or the round shape near the panel shall be changed to a flat shape, such as the shape of screw
point, the gate point, and etc.
-. It is recommended to keep the gap between the panel guides and ribs over 1mm in the worst
conditions.
(※ The suggested dimension does not guarantee the quality of the products.)
-. The gap between the panel guide and the front cover (or the front chassis) should be a zero in Z-
direction to avoid the being broken in the panel caused by being stuck between the gap.
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3.2 The COF and the Drive IC
(a) The pattern of COF is easily damaged by the edge of the press and the burr of
mold under the condition which the products are shaking while delivering. Therefore, it
is recommended to avoid designing not to locate the gate of mold or the parting line in
the position of COF when designing the product.
(b) It is recommended to secure the sufficient gap between the COF and the other parts when
designing the product since the lack of gap between the COF and the other parts can cause the
damage in the COF such as the lead crack under the condition which the product is twisted.
(※ The space over 3.0mm for moving is recommended, but the quality of products is not
guaranteed.)
(c) The temperature of the surface of Drive-IC should be less than 100℃
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(d) The sufficient space for the COF and the Drive IC should be prepared including the worst condition
to prevent the damage on Drive-IC from the external
-. If the panel is placed to the upper part of the mold, it is recommended to keep the gap between
the mold and the front cover or the mold and the top chassis by adding the rib between the COF
and COF.
-. Design the gap between the rib and the cover to maintain the space for the protection of COF as
small as possible
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(e) When metal parts are assembled next to the Drive-IC, the metal part should be insulated to avoid
the damage on IC from the static electricity.
(f) If the length of COF is designed to be short, the lead crack can be occurred by applying the tension
on the COF due to the being shaking of the product.
(g) It is recommended to design source PCB can be easily moved to the direction of each axis in order
for the tension not to be applied to the edge of COF under vibrating condition, such as
transportation of the product.
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3.3 The control PBA and the Source PBA
(a) The gaps between the source PBA and the other parts and the control PBA and other parts should
be considered to avoid the damage on electrical parts by the static electricity and the external If
the material of shielding part is metal, the insulation method is recommended.
(b) Confirm the status of insulation tape since the inappropriately attached insulation tape can cause
the damage on the parts of product if the insulation tape for the insulation of part of PBA is
attached inconsecutively due to the inappropriate design or the error occurred during the process.
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3. 4 The 4-Corner and the cloudy light leakage
(a) It is recommended to follow the method delineated in the picture below for designing
since the distortion on panel and the increase of the temperature gradient in the
surface of panel can cause the light leakage.
-. Place the strong beads at the corner point to control the flatness of the panel.
-. The heat sinking plane in the lower parts shall contact with the bottom chassis.
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3.5 Others
(a) The corrosion of the source PBA
Be cautious when selecting the specification of tape or designing the product since the corrosion
of the parts of circuit caused by the overuse of the glass cleaner of the end user may cause the
occurrence of the abnormalities in the screen, if the model is the reversed product which has the
source PBA designed at the 90˚.
(b) The deterioration of crystal liquid
It is recommended to design the products to make the temperature of the active area of the product
operated below the 50℃ for the protection from containing the abnormalities in the screen due to the
deterioration of the liquid crystal. In addition, it is recommended to design the product not to cause
the occurrence of the deterioration of liquid crystal under the ambient temperature of 50 ℃.
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