Samsung KS57C2308 User Manual

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the KS57C2308/C2316 offer an excellent design solution for a wide variety of applications that require LCD functions.

Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the KS57C2308/C2316's advanced CMOS technology provides for low power consumption and a wide operating voltage range.

OTP

The KS57C2308/C2316 microcontroller is also available in OTP (One Time Programmable) version, KS57P2308/P2316. KS57P2308/P2316 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P2308/P2316 is comparable to KS57C2308/C2316, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

FEATURES

Memory

– 512 × 4-bit RAM – 8 K × 8-bit ROM (KS57C2308/P2308) – 16 K × 8-bit ROM (KS57C2316/P2316)

I/O Pins

– Input only: 8 pins – I/O: 24 pins – Output: 8 pins sharing with segment driver

outputs

LCD Controller/Driver

– Maximum 16-digit LCD direct drive capability – 32 segment, 4 common pins – Display modes: Static, 1/2 duty (1/2 bias),

1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

– Programmable interval timer – Watchdog timer

8-Bit Timer/Counter 0

– Programmable 8-bit timer – External event counter – Arbitrary clock frequency output – Serial I/O interface clock generator

Watch Timer

Bit Sequential Carrier

– Support 16-bit serial data transfer in arbitrary

format

Interrupts

– Three internal vectored interrupts – Three external vectored interrupts – Two quasi-interrupts

Memory-Mapped I/O Structure

– Data memory bank 15

Two Power-Down Modes

– Idle mode (only CPU clock stops) – Stop mode (main or sub system oscillation stops)

Oscillation Sources

– Crystal, ceramic, or RC for main system clock – Crystal or external oscillator for subsystem clock – Main system clock frequency: 4.19 MHz (typical) – Subsystem clock frequency: 32.768 kHz – CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

– 0.95, 1.91, 15.3 µs at 4.19 MHz (main) – 122 µs at 32.768 kHz (subsystem)

– Real-time and interval time measurement – Four frequency outputs to BUZ pin – Clock source generation for LCD

8-Bit Serial I/O Interface

– 8-bit transmit/receive mode – 8-bit receive only mode – LSB-first or MSB-first transmission selectable – Internal or external clock source

1-2

Operating Temperature

– – 40 °C to 85 °C

Operating Voltage Range

– 1.8 V to 5.5 V

Package Type

– 80-pin QFP

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.3/TCL0

P2.0/TCLO0

P4.0-P4.3

P5.0-P5.3

P6.0-P6.3/

KS0-KS3

P7.0-P7.3/

KS4-KS7

P8.0-P8.7/

SEG24-SEG31

INT0, INT1,INT2

8-Bit Timer/

Counter 0

I/O Port 3

I/O Port 4

I/O Port 6

I/O Port 7

I/O Port 8

Watch-Dog

Timer

RESET

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic and Logic Unit

Clock

OUT

Basic Timer

Instruction

4-Bit

Accumulator

Program

Counter

Program

Status Word

FLAGS

Stack

Pointer

Watch

Timer

P2.3/BUZ

LCD Drive/

Controller

I/O Port 0

Input Port 1

I/O Port 2

I/O Port 3

BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23

P8.0-P8.7/ SEG24-SEG31

P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI

P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0

P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ

P3.0/LCDCK P3.1/LCDSY P3.2 P3.3

P0.1 /SCK

Serial I/O

Port

P0.2 /SO

512 x 4-Bit

Data

Memory

8/16-Kbyte

Program

Memory

Figure 1-1. KS57C2308/C2316 Simplified Block Diagram

P0.3 /SI

1-3

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

PIN ASSIGNMENTS

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG2 SEG1

SEG0 COM0 COM1 COM2 COM3

BIAS VLC0 VLC1 VLC2

VDD

VSS

OUT

XIN

TEST

XTIN

OUT

RESET

P0.0/INT4

P0.1/SCK

P0.2/SO

P0.3/SI

P1.0/INT0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

KS57C2308 KS57C2316

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1

1-4

38 3940

P1.1/INT1

P1.2/INT2

P1.3/TCL0

P2.1

P2.3/BUZ

P2.2/CLO

P2.0/TCLO0

P3.2

P3.3

P3.0/LCDCK

P3.1/SCDSY

P4.0

P4.1

P4.2

P4.3

P5.0

Figure 1-2. KS57C2308/C2316 80-QFP Pin Assignment Diagram

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. KS57C2308/C2316 Pin Descriptions

Pin Name Pin

Type

P0.0 P0.1 P0.2 P0.3

P1.0

I I/O I/O

I 4-bit input port.

P1.1 P1.2 P1.3

P2.0

I/O 4-bit I/O port.

P2.1 P2.2 P2.3

P3.0

I/O 4-bit I/O port.

P3.1 P3.2 P3.3

4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read/write and test are possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software

Description Number Share

20 21 22 23

24 25 26 27

28 29 30 31

32 33

INT4

SCK

SO SI

INT0 INT1 INT2 TCL0

TCLO0 – CLO BUZ

LCDCK

LCDSY 34 35

Reset Value

Circuit

Type

Input A-1

D D

A-1

Input A-1

Input D

assignable.

P4.0– P4.3 P5.0– P5.3

I/O 4-bit I/O ports. N-channel open-drain output up

to 5 V. 1-, 4-, and 8-bit read/write and test are possible. Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up

36–43 – Input E

resistors are software assignable.

P6.0– P6.3 P7.0– P7.3

I/O 4-bit I/O ports. Port 6 pins are individually

software configurable as input or output. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. Ports

44–51 KS0–KS3

KS4–KS7

Input

6 and 7 can be paired to enable 8-bit data transfer.

P8.0– P8.7

SEG0– SEG23

SEG24–

O Output port for 1-bit data (for use as CMOS

driver only)

O LCD segment signal output 3–1,

59–52 SEG24–

SEG31

– Output H-15

Output H-16

80–60

O LCD segment signal output 59–52 P8.0–P8.7 Output H-16

SEG31 COM0–

O LCD common signal output 4–7 – Output H-15

COM3 V

LC0–VLC2

– LCD power supply. Voltage dividing resistors

are assignable by mask option

9–11 SCLK

SDAT

– –

BIAS – LCD power control 8 – – – LCDCK I/O LCD clock output for display expansion 32 P3.0 Input D

* *

1-5

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

Table 1-1. KS57C2308/C2316 Pin Descriptions (Continued)

Pin Name Pin

Type

LCDSY I/O LCD synchronization clock output for LCD

Description Number Share

33 P3.1 Input D

Reset Value

Circuit

Type

display expansion TCL0 I/O External clock input for timer/counter 0 27 P1.3 Input A-1 TCLO0 I/O Timer/counter 0 clock output 28 P2.0 Input D SI I Serial interface data input 23 P0.3 Input A-1 SO I/O Serial interface data output 22 P0.2 Input

SCK

INT0 INT1

I/O Serial I/O interface clock signal 21 P0.1 Input

I External interrupts. The triggering edge for

INT0 and INT1 is selectable. Only INT0 is

24 25

P1.0 P1.1

Input A-1

D D

synchronized with the system clock. INT2 I Quasi-interrupt with detection of rising edge

26 P1.2 Input A-1

signals. INT4 I External interrupt input with detection of rising

20 P0.0 Input A-1

or falling edge KS0–KS7 I/O Quasi-interrupt inputs with falling edge

44–51 P6.0–P7.3 Input

detection. CLO I/O CPU clock output 30 P2.2 Input D BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer

31 P2.3 Input D

sound with 4.19 MHz main system clock or

32.768 kHz subsystem clock.

IN,

OUT

IN,

OUT

RESET

TEST –

– Crystal, ceramic or RC oscillator pins for main

15,14 – – – system clock. (For external clock input, use XIN and input XIN‘s reverse phase to X

– Crystal oscillator pins for subsystem clock.

OUT

)

17,18 – – – (For external clock input, use XTIN and input

XTIN's reverse phase to XT

OUT

)

– Main power supply 12 – – – – Ground 13 – – – – Reset signal 19 – Input B

Test signal input (must be connected to VSS)

16 – – –

* *

NOTES:

1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

2. D * Type has a schmitt trigger circuit at input.

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KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

Figure 1-3. Pin Circuit Type A

PULL-UP RESISTOR

P-CHANNEL

N-CHNNEL

RESISTOR ENABLE

DATA

OUTPUT DISABLE

Figure 1-5. Pin Circuit Type C

RESISTOR

ENABLE

P-CHANNEL

N-CHANNEL

PULL-UP RESISTOR

P-CHANNEL

OUT

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3)

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

CIRCUIT TYPE A

Figure 1-6. Pin Circuit Type D

(P0.1, P0.2, P2, P3, P6, P7)

I/O

1-7

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

RESISTOR

PNE

DATA

P-CH

PULL-UP

RESISTOR

ENABLE I/O

LC0

LC1

OUTPUT

N-CH

ENABLE

CIRCUIT TYPE A

Figure 1-7. Pin Circuit Type E (P4, P5)

LC0

LC1

LCD SEGMENT/ COMMON DATA

LC2

OUT

LCD SEGMENT/ & PORT 8 DATA

LC2

Figure 1-9. Pin Circuit Type H-16 (P8)

OUT

Figure 1-8. Pin Circuit Type H-15 (SEG/COM)

1-8

SCHMITT TRIGGER

Figure 1-10. Pin Circuit Type B (RESET)

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

2 ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for KS57C2 308/C2316 devices are mask programmable at the factory. KS57C2308 has 8K × 8-bit program memory and KS57C2316 has 16K × 8-bit program memory, aside from the differences in the ROM size the two products are identical in other features. In its standard configuration, the device's 8,192 × 8-bit (16,384 × 8-bit) program memory has four areas that are directly addressable by the program counter (PC):

— 12-byte area for vector addresses — 96-byte instruction reference area — 20-byte general-purpose area — 8064-byte general-purpose area (KS57C2308) — 16256-byte general-purpose area (KS57C2316)

General-Purpose Program Memory

Two program memory areas are allocated for general-purpose use: One area is 20 bytes in size and the other is 8,064-bytes (16,256-bytes).

Vector Addresses

A 12-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte instructions, and one 3-byte instruction which are stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM.

Table 2-1. Program Memory Address Ranges

ROM Area Function Address Ranges Area Size (in Bytes)

Vector address area 0000H–000BH 12 General-purpose program memory 000CH–001FH 20 REF instruction look-up table area 0020H–007FH 96 General-purpose program memory 0080H–1FFFH (KS57C2308)

0080H–3FFFH (KS57C2316)

8064 (KS57C2308) 16256 (KS57C2316)

2-1

ADDRESS SPACES KS57C2308/P2308/C2316/P2316

GENERAL-PURPOSE MEMORY AREAS

The 20-byte area at ROM locations 000CH–001FH and the 8,064-byte (16,256-byte) area at ROM locations 0080H–1FFFH (0080H–3FFFH) are used as general-purpose program memory. Unused locations in the vector address area and REF instruction look-up table areas can be used as general-purpose program memory. However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM.

VECTOR ADDRESS AREA

The 12-byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. 12-byte vector addresses are organized as follows:

EMB ERB

PC13

(note)

PC12 PC11 PC10 PC9 PC8

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

NOTE: PC13 is used for KS57C2316/P2316 microcontroller.

To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the next page explain how to do this.

0000H

VECTOR ADDRESS AREA

000BH 000CH

001FH 0020H

007FH 0080H

(12 Bytes)

GENERAL-PURPOSE AREA

(20 Bytes)

INSTRUCTION

REFERENCE

AREA

0000H

0002H

0004H

0006H

7 6 5 4 3 2 1 0

RESET

INTB/INT4

INT0

INT1

2-2

GENERAL-PURPOSE AREA

(8,064 Bytes/

16,256 Bytes)

1FFFH 3FFFH

Figure 2-1. ROM Address Structure

0008H

INTS

000AH

INTT0

Figure 2-2. Vector Address Structure

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

++ PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory:

1. When all vector interrupts are used: ORG 0000H

VENT0 1,0,RESET ; EMB ← 1, ERB ← 0; Jump to RESET address by RESET VENT1 0,0,INTB ; EMB ← 0, ERB ← 0; Jump to INTB address by INTB VENT2 0,0,INT0 ; EMB ← 0, ERB ← 0; Jump to INT0 address by INT0 VENT3 0,0,INT1 ; EMB ← 0, ERB ← 0; Jump to INT1 address by INT1 VENT4 0,0,INTS ; EMB ← 0, ERB ← 0; Jump to INTS address by INTS VENT5 0,0,INTT0 ; EMB ← 0, ERB ← 0; Jump to INTT0 address by INTT0

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt

locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG 0000H VENT0 1,0,RESET ; EMB ← 1, ERB ← 0; Jump to RESET address by RESET

VENT1 0,0,INTB ; EMB ← 0, ERB ← 0; Jump to INTB address by INTB ORG 0006H ; INT0 interrupt not used VENT3 0,0,INT1 ; EMB ← 0, ERB ← 0; Jump to INT1 address by INT1 VENT4 0,0,INTS ; EMB ← 0, ERB ← 0; Jump to INTS address by INTS

ORG 000CH ; INTT0 interrupt not used ORG 0010H

3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not

written by a ORG instruction in Example 2, a CPU malfunction will occur:

ORG 0000H VENT0 1,0,RESET ; EMB ← 1, ERB ← 0; Jump to RESET address by RESET

VENT1 0,0,INTB ; EMB ← 0, ERB ← 0; Jump to INTB address by INTB VENT3 0,0,INT1 ; EMB ← 0, ERB ← 0; Jump to INT1 address by INT0 VENT4 0,0,INTS ; EMB ← 0, ERB ← 0; Jump to INTS address by INT1 VENT5 0,0,INTT0 ; EMB ← 0, ERB ← 0; Jump to INTT0 address by INTS

ORG 0010H General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur.

2-3

ADDRESS SPACES KS57C2308/P2308/C2316/P2316

INSTRUCTION REFERENCE AREA

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL.

By using REF instructions you can execute instructions larger than one byte, In summary, there are three ways you can use the REF instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions, — Branching to any location by referencing a branch instruction stored in the look-up table, — Calling subroutines at any location by referencing a call instruction stored in the look-up table.

++ PROGRAMMING TIP — Using the REF Look-Up Table

Here is one example of how to use the REF instruction look-up table:

ORG 0020H JMAIN TJP MAIN ; 0, MAIN KEYCK BTSF KEYFG ; 1, KEYFG CHECK WATCH TCALL CLOCK ; 2, CALL CLOCK INCHL LD @HL,A ; 3, (HL) ← A INCS HL

•

ABC LD EA,#00H ; 47, EA ← #00H

ORG 0080H MAIN NOP

NOP

•

REF KEYCK ; BTSF KEYFG (1-byte instruction)

REF JMAIN ; KEYFG = 1, jump to MAIN (1-byte instruction)

REF WATCH ; KEYFG = 0, CALL CLOCK (1-byte instruction)

REF INCHL ; LD @HL,A

; INCS HL

REF ABC ; LD EA,#00H (1-byte instruction)

•

2-4

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the 512 x 4-bit data memory has four areas: — 32 × 4-bit working register area in bank 0

— 224 × 4-bit general-purpose area in bank 0 which is also used as the stack area — 224 × 4-bit general-purpose area in bank 1 — 32 × 4-bit area for LCD data in bank 1 — 128 × 4-bit area in bank 15 for memory-mapped I/O addresses

To make it easier to reference, the data memory area has three memory banks — bank 0, bank 1 and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. One exception is the LCD data register area, which is 1-bit and 4-bit addressable only.

Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power RESET. However, when RESET signal is generated in power-down mode, the most of data memory contents are held.

000H

01FH 020H

0FFH 100H

1DFH 1E0H

1FFH

F80H

FFFH

WORKING REGISTERS

(32 x 4 Bits)

GENERAL-PURPOSE

REGISTERS AND

STACK AREA

(224 x 4 Bits)

GENERAL-PURPOSE

REGISTERS (224 x 4 Bits)

LCD DATA REGISTERS

(32 x 4 Bits)

MEMORY-MAPPED I/O

AEERESS REGISTERS

(128 x 4 Bits)

BANK 0

BANK 1

BANK 15

Figure 2-3. Data Memory (RAM) Map

2-5

ADDRESS SPACES KS57C2308/P2308/C2316/P2316

Memory Banks 0, 1, and 15

Bank 0 (000H–0FFH) The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing.

Bank 1 (100H–1FFH) The lowest 224 nibbles of bank1 (100H–1DFH) are for general–purpose use;

Use the remaining of 32 nibbles (1E0H–1FFH) as display registers or as general purpose memory.

Bank 15 (F80H–FFFH) The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware address are mapped into this area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15. With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all three data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

LCD Data Register Area

Bit values for LCD segment data are stored in data memory bank 1. Register locations in this area that are not used to store LCD data can be assigned to general-purpose use.

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KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

Table 2-2. Data Memory Organization and Addressing

Addresses Register Areas Bank EMB Value SMB Value

000H–01FH Working registers 0 0, 1 0 020H–0FFH Stack and general-purpose registers

100H–1DFH General-purpose registers 1 1 1 1E0H–1FFH LCD Data registers F80H–FFFH I/O-mapped hardware registers 15 0, 1 15

++ PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1

Clear banks 0 and 1 of the data memory area: RAMCLR SMB 1 ; RAM (100H–1FFH) clear

LD HL,#00H LD A,#0H

RMCL1 LD @HL,A

INCS HL JR RMCL1

SMB 0 ; RAM (010H–0FFH) clear LD HL,#10H

RMCL0 LD @HL,A

INCS HL JR RMCL0

2-7

ADDRESS SPACES KS57C2308/P2308/C2316/P2316

WORKING REGISTERS

Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units.

DATA

MEMORY

BANK 0

000H 001H

002H 003H

004H

005H 006H

007H

008H

00FH

010H

017H 018H

01FH

...

WORKING

BANK 0

BANK 1

BANK 2

BANK 3

2-8

Figure 2-4. Working Register Map

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

Working Register Banks

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing.

Table 2-3. Working Register Organization and Addressing

ERB Setting SRB Settings Selected Register Bank

3 2 1 0

0 0 0 – – Always set to bank 0

0 0 Bank 0

1 0 0 0 1 Bank 1

1 0 Bank 2 1 1 Bank 3

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB) (MSB) (LSB)

Y Z

W X

H L

E A

Figure 2-5. Register Pair Configuration

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

Special-Purpose Working Registers

Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction.

1-BIT

ACCUMULATOR

4-BIT

ACCUMULATOR

8-BIT

ACCUMULATOR

Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction.

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++ PROGRAMMING TIP — Selecting the Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0": VENT2 1,0,INT0 ; EMB ← 1, ERB ← 0, Jump to INT0 address INT0 PUSH SB ; PUSH current SMB, SRB

SRB 2 ; Instruction does not execute because ERB = "0" PUSH HL ; PUSH HL register contents to stack PUSH WX ; PUSH WX register contents to stack PUSH YZ ; PUSH YZ register contents to stack PUSH EA ; PUSH EA register contents to stack SMB 0 LD EA,#00H LD 80H,EA LD HL,#40H INCS HL LD WX,EA LD YZ,EA POP EA ; POP EA register contents from stack POP YZ ; POP YZ register contents from stack POP WX ; POP WX register contents from stack POP HL ; POP HL register contents from stack POP SB ; POP current SMB, SRB IRET

The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below.

2. When ERB = "1": VENT2 1,1,INT0 ; EMB ← 1, ERB ← 1, Jump to INT0 address INT0 PUSH SB ; Store current SMB, SRB

SRB 2 ; Select register bank 2 because of ERB = "1" SMB 0 LD EA,#00H LD 80H,EA LD HL,#40H INCS HL LD WX,EA LD YZ,EA POP SB ; Restore SMB, SRB IRET

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero.

F80H SP3 SP2 SP1 "0" F81H SP7 SP6 SP5 SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s).

Since the RESET value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly.

++ PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1": SMB 15 ; Select memory bank 15

LD EA,#00H ; Bit 0 of SP is always cleared to "0" LD SP,EA ; Stack area initial address (0FFH) ← (SP) – 1

2. When EMB = "0": LD EA,#00H

LD SP,EA ; Memory addressing area (00H–7FH, F80H–FFFH)

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PUSH OPERATIONS

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decreased by a number determined by the type of push operation and then points to the next available stack location.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has executed, the SP is decreased by two and points to the next available stack location.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decreased by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.

PUSH

(After PUSH, SP SP - 2)

SP - 2

SP - 1

LOWER

UPPER

: PC13 is used for KS57C2316/P2316 microcontroller

NOTE

CALL

(After CALL, SP SP - 6) SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

PC11- PC8

0 0

0 0 EMB ERB

0 0 0 0

PC13 PC12 PC13 PC12

PC3 - PC0 PC7 - PC4

PSW

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

Figure 2-7. Push-Type Stack Operations

INTERRUP

(When INT is acknowledged,

SP SP - 6)

PC11 - PC8

0 0

PC3 - PC0 PC7 - PC4

IS1 IS0 EMB ERB

PSW

C SC2 SC1 SC0

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

POP OPERATIONS

For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After the POP has executed, the SP is incremented by two and points to the next free stack location.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has executed, the SP is incremented by six and points to the next free stack location.

SP + 1

SP + 2

NOTE

POP

SP SP + 2)

LOWER

UPPER

: PC13 is used for KS57C2316/P2316 microcontroller

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

RET OR SRET

SP SP + 6)

PC11 – PC8

0 0

0 0 EMB ERB

0 0 0 0

PC13 PC12 PC13 PC12

PC3 – PC0 PC7 – PC4

PSW

Figure 2-8. Pop-Type Stack Operations

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

IRET

SP SP + 6)

PC11 – PC8

0 0

PC3 – PC0 PC7 – PC4

IS1 IS0 EMB ERB

PSW

C SC2 SC1 SC0

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BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero.

Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the L register.

BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately.

If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.

Table 2-4. BSC Register Organization

Name Address Bit 3 Bit 2 Bit 1 Bit 0

BSC0 FC0H BSC0.3 BSC0.2 BSC0.1 BSC0.0 BSC1 FC1H BSC1.3 BSC1.2 BSC1.1 BSC1.0 BSC2 FC2H BSC2.3 BSC2.2 BSC2.1 BSC2.0 BSC3 FC3H BSC3.3 BSC3.2 BSC3.1 BSC3.0

++ PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:

BITS EMB SMB 15 LD EA,#37H ; LD BSC0,EA ; BSC0 ← A, BSC1 ← E LD EA,#59H ; LD BSC2,EA ; BSC2 ← A, BSC3 ← E SMB 0 LD L,#0H ;

AGN LDB C,BSC0.@L ;

LDB P3.0,C ; P3.0 ← C INCS L JR AGN RET

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

PROGRAM COUNTER (PC)

A 13-bit program counter (PC) stores addresses for instruction fetches during program execution (KS57C2316 microcontroller has 14-bit program counter, PC0–PC13). Whenever a reset operation or an interrupt occurs, bits PC12 through PC0 (PC13 through PC0 for KS57C2316) are set to the vector address.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows:

(MSB) (LSB) FB0H IS1 IS0 EMB ERB FB1H C SC2 SC1 SC0

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logical zero.

Table 2-5. Program Status Word Bit Descriptions

PSW Bit Identifier Description Bit Addressing Read/Write

IS1, IS0 Interrupt status flags 1, 4 R/W EMB Enable memory bank flag 1 R/W ERB Enable register bank flag 1 R/W C Carry flag 1 R/W SC2, SC1, SC0 Program skip flags 8 R

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KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

INTERRUPT STATUS FLAGS (IS0, IS1)

PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.

Table 2-6. Interrupt Status Flag Bit Settings

IS1

Value

0 0 0 All interrupt requests are serviced 0 1 1 Only high-priority interrupt(s) as determined in the

1 0 2 No more interrupt requests are serviced 1 1 – Not applicable; these bit settings are undefined

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing.

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

interrupt priority register (IPR) are serviced

++ PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB DI ; Disable interrupt BITR IS1 ; IS1 ← 0 BITS IS0 ; Allow interrupts according to IPR priority level EI ; Enable interrupt

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

EMB FLAG (EMB)

The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1 or 15.

When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose areas of bank 0, 1 and 15 can be accessed by using the appropriate SMB value.

++ PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0": SMB 1 ; Non-essential instruction since EMB = "0"

LD A,#9H LD 90H,A ; (F90H) ← A, bank 15 is selected LD 34H,A ; (034H) ← A, bank 0 is selected SMB 0 ; Non-essential instruction since EMB = "0" LD 90H,A ; (F90H) ← A, bank 15 is selected LD 34H,A ; (034H) ← A, bank 0 is selected SMB 15 ; Non-essential instruction, since EMB = "0" LD 20H,A ; (020H) ← A, bank 0 is selected LD 90H,A ; (F90H) ← A, bank 15 is selected

2. When EMB = "1": SMB 1 ; Select memory bank 1

LD A,#9H LD 90H,A ; (190H) ← A, bank 1 is selected LD 34H,A ; (134H) ← A, bank 1 is selected SMB 0 ; Select memory bank 0 LD 90H,A ; (090H) ← A, bank 0 is selected LD 34H,A ; (034H) ← A, bank 0 is selected SMB 15 ; Select memory bank 15 LD 20H,A ; Program error, but assembler does not detect it LD 90H,A ; (F90H) ← A, bank 15 is selected

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ERB FLAG (ERB)

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (SRB).

When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions.

++ PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0": SRB 1 ; Register bank 0 is selected (since ERB = "0", the

LD EA,#34H ; Bank 0 EA ← #34H LD HL,EA ; Bank 0 HL ← EA SRB 2 ; Register bank 0 is selected LD YZ,EA ; Bank 0 YZ ← EA SRB 3 ; Register bank 0 is selected LD WX,EA ; Bank 0 WX ← EA

2. When ERB = "1": SRB 1 ; Register bank 1 is selected

LD EA,#34H ; Bank 1 EA ← #34H LD HL,EA ; Bank 1 HL ← Bank 1 EA SRB 2 ; Register bank 2 is selected LD YZ,EA ; Bank 2 YZ ← BANK2 EA SRB 3 ; Register bank 3 is selected LD WX,EA ; Bank 3 WX ← Bank 3 EA

; SRB is configured to bank 0)

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

SKIP CONDITION FLAGS (SC2, SC1, SC0)

The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag.

Table 2-7. Valid Carry Flag Manipulation Instructions

Operation Type Instructions Carry Flag Manipulation

Direct manipulation SCF Set carry flag to "1"

RCF Clear carry flag to "0" (reset carry flag) CCF Invert carry flag value (complement carry flag) BTST C Test carry and skip if C = "1"

Bit transfer

Boolean manipulation

LDB (operand) LDB C,(operand) BAND C,(operand)

(1)

Load carry flag value to the specified bit Load contents of the specified bit to carry flag AND the specified bit with contents of carry flag and save

the result to the carry flag

BOR C,(operand)

(1)

OR the specified bit with contents of carry flag and save the result to the carry flag

BXOR C,(operand)

(1)

XOR the specified bit with contents of carry flag and save the result to the carry flag

Interrupt routine

INTn

(2)

Save carry flag to stack with other PSW bits

Return from interrupt IRET Restore carry flag from stack with other PSW bits

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. “INTn” refers to the specific interrupt being executed and is not an instruction.

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++ PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one: SCF ; C ← 1

LD EA,#0C3H ; EA ← #0C3H LD HL,#0AAH ; HL ← #0AAH ADC EA,HL ; EA ← #0C3H + #0AAH + #1H, C ← 1

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P4.0: LD H,#3H ; Set the upper four bits of the address to the H register

value LDB C,@H+0FH.3 ; C ← bit 3 of 3FH BAND C,P3.3 ; C ← C AND P3.3 LDB P4.0,C ; Output result from carry flag to P4.0

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ADDRESS SPACES KS57C2308/P2308/C2316/P2316

NOTES

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