Samsung KS57P01504, KS57C01504, KS57C01502 Datasheet

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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1PRODUCT OVERVIEW

The KS57C01502/C01504 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

The KS57P01504 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are
the same to KS57C01502/C01504. With a four-channel comparator, eight LED direct drive pins, serial I/O
interface, and its versatile 8-bit timer/counter, the KS57C01502/C01504 offers an excellent design solution for a
wide variety of general-purpose applications.

Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the KS57C01502/C01504's advanced CMOS technology provides for
very low power consumption and a wide operating voltage range — all at a very low cost.

PRODUCT OVERVIEW KS57C01502/C01504/P01504

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FEATURES SUMMARY

Memory

• 512 × 4-bit data memory (RAM)

• 2048 × 8-bit program memory

(ROM):KS57C01502
4096 × 8-bit program memory
(ROM):KS57C01504

24 I/O Pins

•• I/O: 18 pins, including 8 high current pins

• Input only: 6 pins

Comparator

• 4-channel mode:

Internal reference (4-bit resolution)
16-step variable reference voltage

• 3-channel mode:

External reference
150 mV resolution (worst case)

8-bit Basic Timer

• Programmable interval timer

• Watch-dog timer

8-bit Timer/Counter 0

• Programmable interval timer

• External event counter function

Timer/counter clock output to TCLO0 pin

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms at 4.19

MHz

• 4 frequency outputs to BUZ pin

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive-only mode

• LSB-first or MSB-first transmission selectable

• Internal or external clock source

Bit Sequential Carrier

• Supports 16-bit serial data transfer in arbitrary

format

Interrupts

• Two external interrupt vectors

• Three internal interrupt vectors

• Two quasi-interrupts

Memory-Mapped I/O Structure

• Data memory bank 15

Two Power-Down Modes

• Idle mode: Only CPU clock stops

• Stop mode: System clock stops

OSCILLATION SOURCES

• Crystal, Ceramic for system clock

• Crystal/ceramic: 0.4 - 6.0 MHz

• CPU clock divider circuit (by 4. 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19 MHz

• 0.67, 1.33, 10.7 µs at 6.0 MHz

Operating Temperature

• – 40

°

C to 85 °C

Operating Voltage Range

• 1.8 V to 5.5 V

Package Type

• 30 SDIP, 32 SOP

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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FUNCTION OVERVIEW

SAM47 CPU

All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and
shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles.

CPU REGISTERS
Program Counter

A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is
incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF
which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an
interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13–12 is reserved to support future
expansion of the device's ROM size.

Stack Pointer

An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the general-purpose
data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to logic zero.

During an interrupt or a subroutine call, the PC value and the program status word (PSW) are saved to the stack
area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored.
Then, the next instruction is executed.

The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset
value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H
by program code. This sets the first register of the stack area to data memory location 0FFH.

PROGRAM MEMORY

In its standard configuration, the 4096 × 8-bit ROM is divided into three functional areas:
— 16-byte area for vector addresses

— 96-byte instruction reference area
— 1920-byte general purpose area (KS57C01502)
— 3968-byte general purpose area (KS57C01504)

The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used
as general-purpose ROM.

The REF instruction references 2 × 1-byte and 2-byte instructions stored in locations 0020H–007FH. The REF
instruction can also reference 3-byte instructions such as JP or CALL. In order for REF to be able to reference
these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to
the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the
instruction reference area can be allocated to general-purpose use.

PRODUCT OVERVIEW KS57C01502/C01504/P01504

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DATA MEMORY
Overview

Data memory is organized into three areas:
— 32 × 4-bit working registers

— 224 × 4-bit general-purpose area in bank 0
— 256 × 4-bit general-purpose area in bank 1
— 128 × 4-bit area in bank 15 for memory-mapped I/O addresses

Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions.
Data memory is organized into two memory banks — bank 0, bank 1 and bank 15. The select memory bank in-

struction (SMB) selects the bank to be used as working data memory. After power-on reset operation, initialization
values for data memory must be redefined by code.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15.
When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all two

data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode is
used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts, subroutines,
mapped I/O, and repetitive access of specific RAM addresses.

Working Registers

The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register
bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can be
addressed as double registers by 8-bit instructions.

Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers
WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as
general-purpose memory.

To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used
for the main program and banks 1, 2, and 3 for interrupt service routines.

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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CONTROL REGISTERS
Program Status Word

The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions can
always address the PSW regardless of the current value of data memory enable flags.

Before an interrupt or subroutine is processed, the PSW values are pushed onto the stack in data memory bank 0.
When the service routine is completed, the PSW values are restored.

IS1 IS0 EMB ERB

C SC2 SC1 SC0

Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags
(SC0–SC2) using 8-bit read instructions only.

Select Bank (SB) Register

Two 4-bit registers store address values used to access specific memory and register banks: the select memory
bank register, SMB, and the select register bank register, SRB.

'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory
address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you can
use the instruction 'SRB n'.

The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and
subroutines.

CLOCK CIRCUITS

System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware.
The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To drive

KS57C01502/C01504 using an external clock source, the external clock signal should be input to Xin, and its
inverted signal to X

out

.

4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock
signal (fx) can be divided internally to produce three CPU clock frequencies — fx/4, fx/8, or fx/64.

INTERRUPTS

Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by
peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0–KS2) detects
falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The
following components support interrupt processing:

— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit

PRODUCT OVERVIEW KS57C01502/C01504/P01504

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POWER-DOWN

To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode; the STOP instruction initiates stop mode.

In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock
oscillation stops completely, halts all operations except for a few basic peripheral functions. A power-down is
terminated either by a or by an interrupt (with exception of the external interrupt INT0).

RESET

When is input during normal operation or during power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed,
normal CPU operation resumes.

I/O PORTS

The KS57C01502/C01504 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–
FF6H in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins
for a total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.

TIMERS and TIMER/COUNTER

The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer.
The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock

frequency.
The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and

dividing external clock signals. The 8-bit timer/counter generates a clock signal ( ) for the serial I/O interface.
The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its

functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer sound.

SERIAL I/O INTERFACE

The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:

— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter

The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first
transmission is also selectable.

The serial interface can operate with an internal or an external clock source, or using the clock signal generated by
the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO mode
register.

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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BIT SEQUENTIAL CARRIER

The bit sequential carrier (BSC) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions.
Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs

can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of
the L register. BSC data can also be manipulated using direct addressing.

COMPARATOR

The KS57C01502/C01504 contains a 4-channel comparator which can be multiplexed to normal input port.
— Conversion time: 15.2 µs, 121.6 µs at 4.19 MHz

— Two operation modes:

Three channels for analog input and one channel for external reference voltage input

Four channels for analog input and internal reference voltage level
— 16-level internal reference voltage generator
— 150 mV accuracy for input voltage level difference detection (maximum)
— Comparator enable and disable

The comparison results are read from the 4-bit CMPREG register after the specified conversion time.

PRODUCT OVERVIEW KS57C01502/C01504/P01504

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BLOCK DIAGRAM

Program

Status Word

Flags

Arithmetic

and

Logic Unit

Instruction Decoder

Internal

Interrupts

RESET

Interrupt

Control

Block

Stack

Pointer

Clock

Program Memory
KS57C01502: 2 KByte
KS57C01504: 4 KByte

512 x 4-Bit

Data

Memory

Input Port 2

Comparator

P2.0/KS0/CIN0
P2.1/KS1/CIN1
P2.2/KS2/CIN2
P2.3/KS3/CIN3

I/O Port 5

P4.0 - P4.3

P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3

I/O Port 4

I/O Port 6

X

OUT

X

IN

Program

Counter

8-Bit

Timer/Counter

I/O Port 3

I/O Port 0

P0.0/CLO
P0.1/TIO
P0.2/INT1

P3.0/TCL0

P3.1/TCLO0

P3.2/CLO

P5.0 - P5.3

Serial I/O Port

Input Port 1

P0.0/SCK
P0.1/SO
P0.2/SI

Basic Timer Watch Timer

Figure 1-1. KS57C01502/C01504 Simplified Block Diagram

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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Pin Assignments

V

SS

Xout

Xin

TEST
P1.0/INT0
P1.1/INT1

RESET

P0.0/

SCK

P0.1./SO

P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3

P3.0/TCL0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

V

DD

P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.2/CLO
P3.1/TCLO0

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

KS57C01502
KS57C01504

(Top View)

30-SDIP

V

SS

Xout

Xin

TEST
P1.0/INT0
P1.1/INT1

RESET

NC

P0.0/

SCK

P0.1./SO

P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3

P3.0/TCL0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

V

DD

P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
NC
P3.2/CLO
P3.1/TCLO0

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

KS57C01502
KS57C01504

(Top View)

32-SOP

Figure 1-2. KS57C01502/C01504 Pin Assignment Diagram

PRODUCT OVERVIEW KS57C01502/C01504/P01504

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PIN DESCRIPTIONS

Table 1-1. KS57C01502/C01504 Pin Descriptions

Pin Name Pin

Type

Description Number Share Pin

P0.0
P0.1
P0.2

I/O 3-bit I/O port. 1-bit or 3-bit read/write and test are

possible. Pull-up resistors are assignable to input pins by
software and are automatically disabled for output pins.
Pins are individually configurable as input or output.

8(9)

9(10)

10(11)

SO

SI

P1.0
P1.1

I 2-bit input port. 1-bit or 2-bit read and test are possible.

Pull-up resistors are assignable by software.

5(5)
6(6)

INT0
INT1

P2.0–P2.3 I 4-bit input port. 1-bit or 4-bit read and test are possible. 11-14

(12-15)

CIN0–CIN3

P3.0
P3.1
P3.2

I/O Same as port 0 15(16)

16(17)
17(18)

TCL0

TCLO0

CLO

P4.0–P4.3
P5.0–P5.3

I/O 4-bit I/O ports. 1-, 4-, or 8-bit read/write and test are

possible. Pins are individually configurable as input or
output. 4-bit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. The N-channel open-drain or push-pull output can
be selected by software (1-bit unit)

18-21(20-23)
22-25(24-27)

–

P6.0
P6.1
P6.2
P6.3

I/O 4-bit I/O port.

1-bit or 4-bit read/write and test are possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.

26(28)
27(29)
28(30)
29(31)

KS0
KS1
KS2
BUZ

INT0 I External interrupts with detection of rising and falling

edges

5(5) P1.0

INT1 I External interrupts with detection of rising or falling edges 6(6) P1.1

CIN0–CIN3 I 4-channel comparator input.

CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input

11-14(12-15) P2.0–P2.3

I/O Serial interface clock signal P0.0

SO I/O Serial data output 9(10) P0.1

SI I/O Serial data input 10(11) P0.2

TCL0 I/O External clock input for timer/counter 15(16) P3.0

TCLO0 I/O Timer/counter clock output 16(17) P3.1

CLO I/O CPU clock output 17(18) P3.2
BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19

MHz for buzzer sound

29(31) P6.3

NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.

KS57C01502/C01504/P01504 PRODUCT OVERVIEW

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Table 1-1. KS57C01502/C01504 Pin Descriptions (Continued)

Pin Name Pin

Type

Description Number Share Pin

Quasi-interrupt input with falling edge detection 26-28(28-30) P6.0–P6.2

V

DD

— Main power supply 30(32) —

V

SS

— Ground 1(1) —

I Reset signal 7(7) —

TEST I

Test signal input (must be connected to VSS)

4(4) —

Xin, X

out

— Crystal or ceramic oscillator signal for system clock 3,2(3,2) —

NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.

Table 1-2. Overview of KS57C01502/C01504 Pin Data

SDIP Pin

Numbers

Pin

Names

Share

Pins

I/O

Type

Reset
Value

Circuit

Type

1

V

SS

   

2,3 Xout, Xin

   

4 TEST



I

 

5,6 P1.0, P1.1 INT0, INT1 I Input A-3

7



I



B

8-10 P0.0 - P0.2

, SO, SI

I/O Input D-1

11-14 P2.0 - P2.3 CIN0 - CIN3 I Input

F-1, F-2

(note)

15-17 P3.0 - P3.2 TCL0, TCLO0,

CLO

I/O Input D-1

18-21 P4.0 - P4.3



I/O Input E

22-25 P5.0 - P5.3



I/O Input E

26-29 P6.0 - P6.3 KS0, KS1, KS2,

BUZ

I/O Input D-1

30

V

DD

   

NOTE: I/O circuit type F-2 is implemented for P2.3 only.