SAMSUNG KM416V4004C, KM416V4104C Technical data

KM416V4004C

KM416V4004C,KM416V4104C	CMOS DRAM

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Extended Data Out Mode operation

•

Part Identification

• 2

CAS

Byte/Word Read/Write operation

•

CAS-before-RAS refresh capability

•

-only and Hidden refresh capability

- KM416V4004C/C-L(3.3V, 8K Ref.)

RAS

- KM416V4104C/C-L(3.3V, 4K Ref.)

•

Fast parallel test mode capability

•

Self-refresh capability (L-ver only)

•

Active Power Dissipation

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

Unit : mW

• JEDEC Standard pinout

Speed

8K

4K

•

Available in Plastic TSOP(II) packages

-45

324

468

• +3.3V±0.3V power supply

-5

288

432

-6

252

396

•

Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

Refresh

Refresh time

NO.

cycle

Normal

L-ver

KM416V4004C*

8K

64ms

128ms

RAS

Control

Vcc

UCAS

KM416V4104C

4K

LCAS

Clocks

Vss

VBB Generator

W

* Access mode & RAS only refresh mode									Lower
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
							Row Decoder		Data in
CAS-before-RAS & Hidden refresh mode						Refresh Timer			Buffer
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)						Refresh Control		I/O	Lower
									Data out
								&
							Memory Array		Buffer
								Amps
• Performance Range						Refresh Counter	4,194,304 x 16		Upper
							Cells		Data in
								Sense
Speed	tRAC	tCAC	tRC	tHPC	A0~A12	Row Address Buffer			Buffer
-45	45ns	12ns	74ns	17ns	(A0~A11)*1				Upper
					A0~A8	Col. Address Buffer	Column Decoder		Data out
-5	50ns	15ns	84ns	20ns					Buffer
					(A0~A9)*1
-6	60ns	17ns	104ns	25ns		Note) *1 : 4K Refresh

DQ0

to

DQ7

OE

DQ8 to

DQ15

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM416V4004C,KM416V4104C	CMOS DRAM

PIN CONFIGURATION (Top Views)

			•KM416V40(1)04CS
VCC				1	50				VSS
DQ0				2	49				DQ15
DQ1				3	48				DQ14
DQ2				4	47				DQ13
DQ3				5	46				DQ12
VCC				6	45				VSS
DQ4				7	44				DQ11
DQ5				8	43				DQ10
DQ6				9	42				DQ9
DQ7				10	41				DQ8
N.C				11	40				N.C
VCC				12	39				VSS
W				13	38				LCAS
RAS				14	37				UCAS
N.C				15	36				OE
N.C				16	35				N.C
N.C				17	34				N.C
N.C				18	33				A12(N.C)*
A0				19	32				A11
A1				20	31				A10
A2				21	30				A9
A3				22	29				A8
A4				23	28				A7
A5				24	27				A6
VCC				25	26				VSS

									(400mil TSOP(II))
								*(N.C) : N.C for 4K Refresh Product
			Pin Name						Pin function
			A0 - A12						Address Inputs(8K Product)
			A0 - A11						Address Inputs(4K Product)
			DQ0 - 15						Data In/Out
			VSS						Ground
									Row Address Strobe
			RAS
									Upper Column Address Strobe
			UCAS
									Lower Column Address Strobe
			LCAS
									Read/Write Input
			W
									Data Output Enable
			OE
			VCC						Power(+3.3V)
			N.C						No Connection

KM416V4004C,KM416V4104C					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Rating				Units
Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		V
Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		V
Storage Temperature	Tstg	-55 to +150				°C
Power Dissipation	PD		1			W
Short Circuit Output Current	IOS		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C)

	Parameter	Symbol	Min	Typ	Max	Units
Supply Voltage		VCC	3.0	3.3	3.6	V
Ground		VSS	0	0	0	V
Input High Voltage		VIH	2.0	-	VCC+0.3*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	V
*1	: VCC+1.3V at pulse width≤15ns which is measured at VCC
*2	: -1.3 at pulse width≤15ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Parameter		Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,		II(L)	-5	5	uA
	all other pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V

KM416V4004C,KM416V4104C							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				KM416V4004C		KM416V4104C
		-45		90		130		mA
ICC1	Don′t care	-5		80		120		mA
		-6		70		110		mA
ICC2	Normal	Don′t care		1		1		mA
	L			1		1		mA
		-45		90		130		mA
ICC3	Don′t care	-5		80		120		mA
		-6		70		110		mA
		-45		100		100		mA
ICC4	Don′t care	-5		90		90		mA
		-6		80		80		mA
ICC5	Normal	Don′t care		500		500		uA
	L			200		200		uA
		-45		130		130		mA
ICC6	Don′t care	-5		120		120		mA
		-6		110		110		mA
ICC7	L	Don′t care		350		350		uA
ICCS	L	Don′t care		350		350		uA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)

ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V

W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.

KM416V4004C,KM416V4104C

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

UCAS,

LCAS,

W,

OE]

Output capacitance [DQ0 - DQ15]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

							Parameter											Symbol		-45			-5			-6		Unit	Note
																			Min		Max	Min		Max	Min		Max	s
		Random read or write cycle time																tRC	74			84			104			ns
		Read-modify-write cycle time																tRWC	101			113			138			ns
		Access time from																tRAC			45			50			60	ns	3,4,10
							RAS
		Access time from																tCAC			12			13			15	ns	3,4,5
							CAS
		Access time from column address																tAA			23			25			30	ns	3,10
				to output in Low-Z														tCLZ	3			3			3			ns	3
		CAS
		Output buffer turn-off delay from																tCEZ	3		13	3		13	3		13	ns	6,20
													CAS
			to output in Low-Z															tOLZ	3			3			3			ns	3
		OE
		Transition time (rise and fall)																tT	1		50	1		50	1		50	ns	2
				precharge time														tRP	25			30			40			ns
		RAS
				pulse width														tRAS	45		10K	50		10K	60		10K	ns
		RAS
				hold time														tRSH	8			8			10			ns
		RAS
				hold time														tCSH	35			38			40			ns
		CAS
				pulse width														tCAS	7		5K	8		10K	10		10K	ns
		CAS
				to		delay time												tRCD	11		33	11		37	14		45	ns	4
		RAS			CAS
				to column address delay time														tRAD	9		22	9		25	12		30	ns	10
		RAS
				to		precharge time												tCRP	5			5			5			ns
		CAS			RAS
		Row address set-up time																tASR	0			0			0			ns
		Row address hold time																tRAH	7			7			10			ns
		Column address set-up time																tASC	0			0			0			ns	13
		Column address hold time																tCAH	7			7			10			ns	13
		Column address to										lead time						tRAL	23			25			30			ns
									RAS
		Read command set-up time																tRCS	0			0			0			ns
		Read command hold time referenced to																tRCH	0			0			0			ns	8
															CAS
		Read command hold time referenced to																tRRH	0			0			0			ns	8
															RAS
		Write command hold time																tWCH	7			7			10			ns
		Write command pulse width																tWP	6			7			10			ns
		Write command to									lead time							tRWL	8			8			10			ns
								RAS
		Write command to									lead time							tCWL	7			7			10			ns	16
								CAS
		Data set-up time																tDS	0			0			0			ns	9,19

KM416V4004C,KM416V4104C																																																CMOS DRAM
	AC CHARACTERISTICS (Continued)
																			Parameter																				Symbol		-45			-5			-6		Units	Note
																																								Min		Max	Min		Max	Min		Max
		Data hold time																																					tDH	7			7			10			ns	9,19
		Refresh period (Normal)																																					tREF			64			64			64	ms
		Refresh period (L-ver)																																					tREF			128			128			128	ms
		Write command set-up time																																					tWCS	0			0			0			ns	7
									to			delay time																											tCWD	24			27			32			ns	7,15
		CAS									W
									to			delay time																											tRWD	57			64			77			ns	7
		RAS									W
		Column address to																							delay time														tAWD	35			39			47			ns	7
																				W
									set-up time																		-before-								refresh)				tCSR	5			5			5			ns	17
		CAS															(CAS														RAS
									hold time															-before-									refresh)						tCHR	10			10			10			ns	18
		CAS													(CAS															RAS
									to					precharge time																									tRPC	5			5			5			ns
		RAS									CAS
		Access time from																									precharge												tCPA			24			28			35	ns	3
																		CAS
		Hyper Page cycle time																																					tHPC	17			20			25			ns	21
		Hyper Page read-modify-write cycle time																																					tHPRWC	47			47			56			ns	21
									precharge time (Hyper page cycle)																														tCP	6.5			7			10			ns	14
		CAS
									pulse width (Hyper page cycle)																														tRASP	45		200K	50		200K	60		200K	ns
		RAS
									hold time from																				precharge										tRHCP	24			30			35			ns
		RAS																			CAS
						access time																																	tOEA			12			13			15	ns	3
		OE
						to data delay																																	tOED	8			10			13			ns
		OE
									precharge to															delay time															tCPWD	36			41			52			ns
		CAS																	W
		Output buffer turn off delay time from																																					tOEZ	3		11	3		13	3		13	ns	6
																																					OE
					command hold time																																		tOEH	5			5			5			ns
		OE
		Write command set-up time (Test mode in)																																					tWTS	10			10			10			ns	11
		Write command hold time (Test mode in)																																					tWTH	10			10			10			ns	11
				to								precharge time (C-B-R refresh)																											tWRP	10			10			10			ns
		W							RAS
				to								hold time (C-B-R refresh)																											tWRH	10			10			10			ns
		W							RAS
		Output data hold time																																					tDOH	4			5			5			ns
		Output buffer turn off delay from																																					tREZ	3		13	3		13	3		13	ns	6,20
																																RAS
		Output buffer turn off delay from																																					tWEZ	3		13	3		13	3		13	ns	6
																																W
			to data delay																																				tWED	8			15			15			ns
		W
					to								hold time																										tOCH	5			5			5			ns
		OE								CAS
							hold time to																																tCHO	5			5			5			ns
		CAS														OE
						precharge time																																	tOEP	5			5			5			ns
		OE
				pulse width (Hyper Page Cycle)																																			tWPE	5			5			5			ns
		W
							pulse width (C-B-R self refresh)																																tRASS	100			100			100			us	22,23,24
		RAS
								precharge time (C-B-R self refresh)																															tRPS	74			90			110			ns	22,23,24
		RAS
								hold time (C-B-R self refresh)																															tCHS	-50			-50			-50			ns	22,23,24
		CAS

	KM416V4004C,KM416V4104C																							CMOS DRAM
TEST MODE CYCLE																										( Note 11 )
							Parameter								Symbol		-45			-5			-6		Units	Note
																Min		Max	Min		Max	Min		Max
	Random read or write cycle time														tRC	79			89			109			ns
	Read-modify-write cycle time														tRWC	110			121			145			ns
	Access time from														tRAC			50			55			65	ns	3,4,10,12
								RAS
	Access time from														tCAC			17			18			20	ns	3,4,5,12
								CAS
	Access time from column address														tAA			28			30			35	ns	3,10,12
					pulse width										tRAS	50		10K	55		10K	65		10K	ns
	RAS
					pulse width										tCAS	12		10K	13		10K	15		10K	ns
	CAS
					hold time										tRSH	18			18			20			ns
	RAS
					hold time										tCSH	39			43			50			ns
	CAS
	Column Address to												lead time		tRAL	28			30			35			ns
										RAS
				to			delay time								tCWD	29			35			39			ns	7
	CAS					W
					to		delay time								tRWD	62			72			84			ns	7
	RAS					W
	Column Address to										delay time				tAWD	40			47			54			ns	7
										W
	Hyper Page cycle time														tHPC	22			25			30			ns	21
	Hyper Page read-modify-write cycle time														tHPRWC	52			53			61			ns	21
					pulse width (Hyper page cycle)										tRASP	50		200K	55		200K	65		200K	ns
	RAS
	Access time from											precharge			tCPA			29			33			40	ns	3
									CAS
			access time												tOEA			17			18			20	ns	3
	OE
			to data delay												tOED	13			18			20			ns
	OE
			command hold time												tOEH	13			18			20			ns
	OE

KM416V4004C,KM416V4104C	CMOS DRAM

NOTES

1.An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved.

2.Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.

3.Measured with a load equivalent to 1 TTL load and 100pF.

4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.Assumes that tRCD³tRCD(max).

6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

7.tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS³tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD³tCWD(min), tRWD³tRWD(min) and tAWD³tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.

8.Either tRCH or tRRH must be satisfied for a read cycle.

9.This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles.

10.Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

11.These specifiecations are applied in the test mode.

12.In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

13.tASC, tCAH are referenced to the earlier CAS falling edge.

14.tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

15.tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

KM416V40(1)04C Truth Table

RAS

LCAS

UCAS

W

OE

DQ0 - DQ7

DQ8-DQ15

STATE

H

X

X

X

X

Hi-Z

Hi-Z

Standby

L

H

H

X

X

Hi-Z

Hi-Z

Refresh

L

L

H

H

L

DQ-OUT

Hi-Z

Byte Read

L

H

L

H

L

Hi-Z

DQ-OUT

Byte Read

L

L

L

H

L

DQ-OUT

DQ-OUT

Word Read

L

L

H

L

H

DQ-IN

-

Byte Write

L

H

L

L

H

-

DQ-IN

Byte Write

L

L

L

L

H

DQ-IN

DQ-IN

Word Write

L

L

L

H

H

Hi-Z

Hi-Z

-

KM416V4004C,KM416V4104C	CMOS DRAM

16.tCWL is specified from W falling edge to the earlier CAS rising edge.

17.tCSR is referenced to earlier CAS falling before RAS transition low.

18.tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR

tCHR

19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15							Din

20.If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

21.tASC³6ns, Assume tT=2.0ns, if tASC£6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".

22.If tRASS³100us, then RAS precharge time must use tRPS instead of tRP.

23.For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification.

24.For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.

KM416V4004C,KM416V4104C	CMOS DRAM

WORD READ CYCLE

				tRC	tRP
VIH -				tRAS
RAS VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
UCAS VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
LCAS VIL -			tRAD
				tRAL
	tASR	tRAH	tASC
				tCAH
VIH -
	ROW			COLUMN
A VIL -
	ADDRESS			ADDRESS
			tRCS		tRCH
					tRRH
VIH -
W VIL -
				tAA
VIH -				tOLZ
				tOEA
OE VIL -
				tCAC	tCEZ
DQ0 ~ DQ7			tRAC	tCLZ	tOEZ
VOH -		OPEN			DATA-OUT
VOL -
				tCAC	tCEZ
DQ8 ~ DQ15			tRAC	tCLZ	tOEZ
VOH -
		OPEN			DATA-OUT
VOL -

Don′t care

Undefined

KM416V4004C,KM416V4104C	CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC	tRP
VIH -				tRAS
RAS VIL -
	tCRP				tRPC
VIH -
UCAS VIL -
	tCRP			tCSH
			tRCD	tRSH
VIH -				tCAS
LCAS VIL -			tRAD
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -
	ROW			COLUMN
A VIL -
	ADDRESS			ADDRESS
			tRCS		tRCH
					tRRH
VIH -
W VIL -					tCEZ
				tAA
					tOEZ
VIH -				tOEA
OE VIL -
				tCAC
DQ0 ~ DQ7			tRAC	tCLZ
VOH -		OPEN			DATA-OUT
VOL -

tOLZ

DQ8 ~ DQ15 VOH -

OPEN

VOL -

Don′t care

Undefined