Samsung K9F4008W0A-TIB0, K9F4008W0A-TCB0 Datasheet

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

Document Title

512K x 8 bit NAND Flash Memory

Revision History

Revision No.

0.0

1.0

1.1

1.2

1.3

History

Initial issue.

1. Changed Operating Voltage 2.7V ~ 5.5V → 3.0V ~ 5.5V

Data Sheet 1999

1. Added CE don’t care mode during the data-loading and reading

1. Changed device name

- KM29W040AT -> K9F4008W0A-TCB0

- KM29W040AIT -> K9F4008W0A-TIB0

1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences

~ 2.5V

V

CC

High

WP

WE

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.

3. AC parameter tAR is devided into tAR1, tAR2 (before revision)

ALE to RE Delay tAR 250 - ns

1µ

≈

≈

≈

~ 2.5V

Draft Date

April 10th 1998

July 14th 1998

April 10th 1999

Sep. 15th 1999

Jul. 23th 2001

Remark

Preliminary

(after revision)

ALE to RE Delay(ID Delay) tAR1 20 - ns
ALE to RE Delay(Read Cycle) tAR2 250 - ns

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

1

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

512K x 8 Bit NAND Flash Memory

GENERAL DESCRIPTIONFEATURES

• Voltage Supply: 3.0V~5.5V

• Organization

- Memory Cell Array : 512K x 8 bit

- Data Register : 32 x 8 bit

• Automatic Program and Erase (Typical)

- Frame Program : 32 Byte in 500µs

- Block Erase : 4K Byte in 6ms

• 32-Byte Frame Read Operation

- Random Access : 15µs(Max.)

- Serial Frame Access : 120ns(Min.)

• Command/Address/Data Multiplexed I/O port

• Low Operation Current (Typical)

- 10µA Standby Current

- 10mA Read/ Program/Erase Current

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

• Package

- 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)

The K9F4008W0A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typical 500µs and an Erase operation erase a
4K-byte block in typical 6ms. Data in a frame can be read out at
a burst cycle rate of 120ns/byte. The I/O pins serve as the ports
for address and data input/output as well as for command
inputs. The on-chip write controller automates the program and
erase operations, including program or erase pulse repetition
where required, and performs internal verification of cell data.

The K9F4008W0A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include data storage in digital Telephone Answering
Devices(TAD) and other consumer applications that require
voice data storage.

PIN CONFIGURATION

VSS

1

CLE

2

ALE

3

WE

4

WP

5

N.C

6

N.C

7

N.C

8

N.C

9

N.C

10
11
12

N.C

13

N.C

14

N.C

15

N.C

16

N.C

17

I/O0

18

I/O1

19

I/O2

20

I/O3

21

VSS

22 VCC

44(40) TSOP (II)

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC, VSS or GND inputs disconnected.

VCC

44

CE

43

RE

42

R/B

41

GND

40

N.C

39

N.C

38

N.C

37

N.C

36

N.C

35
34
33

N.C

32

N.C

31

N.C

30

N.C

29

N.C

28

I/O7

27

I/O6

26

I/O5

25

I/O4

24
23

PIN DESCRIPTION

Pin Name Pin Function

I/O0 ~ I/O7 Data Inputs/Outputs

CLE Command Latch Enable
ALE Address Latch Enable

CE Chip Enable

RE Read Enable
WE Write Enable
WP Write Protect

GND Ground Input

R/B Ready/Busy output
VCC Power
VSS Ground
N.C No Connection

2

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

A7 - A18

A0 - A6

Command

CE
RE
WE

X-Buffers
Latches
& Decoders

Y-Buffers
Latches
& Decoders

Command

Register

Control Logic

& High Voltage

Generator

CLE ALE WP

Figure 2. ARRAY ORGANIZATION

4M Bit

NAND Flash ARRAY

32Byte x 4Frames x 4096Rows

Page Register & S/A

Y-Gating

I/O Buffers & Latches

Global Buffers

Good Block

1Block = 32 Rows
= 4K Bytes

I/O0
I/O7

The 1st Block (4KB)

1 Frame = 32 Bytes

4K Rows
(=128 Blocks)

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A8 A9 A10 A11 A12 A13 A14 A15

3rd Cycle A16 A17 A18 X*

NOTE : *(1) : X can be VIL or VIH

1 2

128Bytes

Frame Register

32 Bytes

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

3

4

I/O0 ~ I/O7

(1)

X* X* *X *X

1 Row = 4 Frames = 128 Bytes

1 Block = 32 Rows = 4K Bytes

1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks
= 4Mbits

8 bit

* The device ignores any additional input of address cycles than reguired.

Column Address (A0-A4)
Frame Address (A5-A6)

Row Address (A7-A11)
Block Address (A12-A18)

3

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

PRODUCT INTRODUCTION

The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is
executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.

The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to
higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus
cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a
19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles fol­lowing by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F4008W0A.

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 00h ­Reset FFh - O
Frame Program 80h 10h
Block Erase 60h D0h
Status read 70h - O
Read ID 90h -

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

4

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.

I/O Port : I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.

5

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Voltage on any pin relative to VSS VIN -0.6 to +7.0 V

Temperature Under Bias

Storage Temperature TSTG -65 to +150 °C

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F4008W0A-TCB0
K9F4008W0A-TIB0 -40 to +125

TBIAS

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C)

Parameter Symbol Min Typ. Max Unit

Supply Voltage VCC 3.0 - 5.5 V
Supply Voltage

VSS 0 0 0 V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Oper-

ating

Current
Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1
Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50

Output Leakage Current ILO VOUT=0 to 5.5V - - ±10 - - ±10
Input High Voltage, All

inputs
Input Low Voltage, All inputs VIL - -0.3 - 0.6 -0.3 - 0.8

Output High Voltage Level VOH IOH=-400µA 2.4 - - 2.4 - ­Output Low Voltage Level
Output Low Current(R/B) IOL(R/B) VOL=0.4V 8 10 - 8 10 - mA

Burst Read Cycle ICC1 tRC=120ns,CE=VIL, IOUT=0mA - 5 10 - 10 20
Program ICC2 - - 5 10 - 10 20

Erase ICC3 - - 5 10 - 10 20

VIH - 2.4 -

VOL IOL=2.1mA - - 0.4 - - 0.4

Vcc = 3.0V ~ 3.6V Vcc = 3.6V ~ 5.5V

Min

-10 to +125

Typ

Max Min

VCC+

0.3

2.4 -

Typ

Max

VCC+

0.5

°C

Unit

mA

µAInput Leakage Current ILI VIN=0 to 5.5V - - ±10 - - ±10

V

6

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 125 - 128 Block

NOTE :

1. The K9F4008W0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase

or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

AC TEST CONDITION

(K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C, VCC=3.0V ~ 5.5V unless otherwise noted)

Parameter

Vcc=3.0V ~ 3.6V Vcc=3.6V ~ 5.5V
Input Pulse Levels 0.4V to 2.6V 0.4V to 2.6V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 0.8V and 2.0V
Output Load 1 TTL GATE and CL = 100pF

CAPACITANCE(TA=25°C, Vcc=5.0V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input / Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

Value

MODE SELECTION

CLE ALE CE WE RE WP Mode

H L L H X
L H L H X Address Input(3clock)
H L L H H
L H L H H Address Input(3clock)
L L L H H
L L L H X Sequential Read & Data Output
L L L H H X During Read(Busy)
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X
X X H X X

NOTE : 1. X can be VIL or VIH

2. WP should be biased to CMOS high or CMOS low for standby.

(1)

X

X X X L Write Protect

(2)

0V/VCC

Read Mode

Write Mode

Data Input

Stand-by

Command Input

Command Input

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 0.5 1 ms
Number of Partial Program Cycles in the Same Frame Nop - - 10 cycles
Block Erase Time tBERS - 6 10 ms

7

K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol Min Max Unit

CLE Set-up Time tCLS 50 - ns
CLE Hold Time tCLH 50 - ns
CE Setup Time tCS 50 - ns
CE Hold Time
WE Pulse Width tWP 60 - ns
ALE Setup Time tALS 50 - ns
ALE Hold Time tALH 50 - ns
Data Set-up Time tDS 40 - ns
Data Hold Time
Write Cycle Time tWC 120 - ns
WE High Hold Time

AC Characteristics for Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 15 µs
ALE to RE Delay(ID Delay) tAR1 20 - ns
ALE to RE Delay(Read Cycle) tAR2 250 - ns
CE low to RE low (ID read) tCR 250 - ns
CLE to RE Delay tCLR 50 - ns
Ready to RE Low tRR 100 - ns
RE Pulse Width tRP 60 - ns
WE High to Busy tWB - 200 ns
Read Cycle Time tRC 120 - ns
RE Access Time tREA - 50 ns
RE High to Output Hi-Z tRHZ 0 30 ns
CE High to Output Hi-Z tCHZ - 50 ns
RE High Hold Time tREH 40 - ns
Output Hi-Z to RE Low tIR 0 - ns
CE High to Ready(in case of interception by CE at read)
RE Low to Status Output tRSTO - 60
CE Low to Status Output tCSTO - 70 ns
WE High to RE Low tWHR 50 - ns
RE access time(Read ID) tWHRID 100 - ns
Device Resetting Time(Read/Program/Erase) tRST - 5/10/500 µs

NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

tCH 50 - ns

tDH 20 - ns

tWH 40 - ns

tCRY -

100+tr(R/B)

(1)

ns
ns

8