SAMSUNG K9F2808U0C Technical data

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K9F2808U0C

Document Title

16M x 8 Bit NAND Flash Memory

Revision History

Revision No.

0.0

1.0

2.0

2.1

2.2

History

Initial issue.

TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm

1.A3 Pin assignment of TBGA Package is changed.(Page 4)
(before) NC --> (after) Vss

2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)

3. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 33)

The min. Vcc value 1.8V devices is changed.

K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.

K9F2808U0C-FCB0,FIB0

K9F2808Q0C-HCB0,HIB0

K9F2816U0C-HCB0,HIB0

K9F2816U0C-PCB0,PIB0

K9F2816Q0C-HCB0,HIB0

K9F2808U0C-HCB0,HIB0

K9F2808U0C-PCB0,PIB0

FLASH MEMORY

Draft Date

Apr. 15th 2002

Sep. 5th 2002

Dec.10th 2002

Mar. 6th 2003

Mar. 13rd 2003

Remark

Advance

Advance

Preliminary

2.3

2.4

2.5

2.6

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

Some AC parameters are changed(K9F28XXQ0C).

tWC tWH tWP tRC tREH tRP tREA tCEA

Before 45 15 25 50 15 25 30 45

After 60 20 40 60 20 40 40 55

1. New definition of the number of invalid blocks is added.
(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb

memory space)

2. Note is added.

(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)

1. K9F2808U(Q)0C-DC(I)B0,K9F2816U(Q)0C-DC(I)B0 is deleted.

2. tWC is changed.
45ns(Before) ---> 50ns(After)

3. Minimum valid block number is changed.
1004(Before) --> 1009(After)

1. Minimum valid block number is changed.
1009(Before) --> 1004(After)

Mar. 26th 2003

May. 24th 2003

Oct. 10th 2003

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

1

Package Dimensions FLASH MEMORY

Document Title

16M x 8 Bit NAND Flash Memory

Revision History

Revision No.

2.7

2.8

2.9

History

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram

2. PKG(TSOP1, WSOP1) Dimension Change

1. NAND Flash Technical Notes is changed.

-Invalid block -> initial invalid block ( page 13)

-Error in write or read operation ( page 14 )

-Program Flow Chart ( page 14 )

1. The flow chart to creat the initial invalid block table is changed.

Draft Date

May 21th 2004

Oct. 25th. 2004

May 6th 2005

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

2

K9F2808U0C

FLASH MEMORY

16M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F2808U0C-Y,P

K9F2808U0C-V,F WSOP1

FEATURES

• Voltage Supply : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

-(16M + 512K)bit x 8bit

- Data Register

- (512 + 16)bit x 8bit

• Automatic Program and Erase

- Page Program

-(512 + 16)Byte

- Block Erase :

- (16K + 512)Byte

• Page Read Operation

- Page Size

- (512 + 16)Byte

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)

2.7 ~ 3.6V X8

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Unique ID for Copyright Protection

• Package

- K9F2808U0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F2808U0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package

- K9F2808U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)

- K9F2808U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package
* K9F2808U0C-V/F(WSOPI ) is the same device as

K9F2808U0C-Y/P(TSOP1) except package type.

TSOP1

GENERAL DESCRIPTION

Offered in 16Mx8bit , the K9F2808U0C is 128M bit with spare 4M bit capacity. The device is offered in 3.3V Vcc. Its NAND cell pro­vides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs
on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out
at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write control automates all program and erase functions including pulse repetition, where required, and internal verification and mar­gining of data. Even the write-intensive systems can take advantage of the K9F2808U0C’s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F2808U0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.

3

K9F2808U0C

PIN CONFIGURATION (TSOP1)

K9F2808U0C-YCB0,PCB0/YIB0,PIB0

FLASH MEMORY

N.C
N.C
N.C
N.C
N.C

GND

R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE
WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

20.00±0.20

0.787±0.008

+0.07

-0.03

#1

0.20

#48

N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C

Unit :mm/Inch

MAX

0.10

0.004

0.25
()

0.010

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197

0~8°

0.45~0.75

0.018~0.030

#24

0.25

TYP

0.010

18.40±0.10

0.724±0.004

#25

+0.075

0.035
+0.003

-0.001

0.125

0.005

0.50

()

0.020

MAX

0.488

12.40

1.00±0.05

0.039±0.002

1.20
MAX

0.047

12.00

0.472

0.05
MIN

0.002

4

K9F2808U0C

PIN CONFIGURATION (WSOP1)

K9F2808U0C-VCB0,FCB0/VIB0,FIB0

N.C

1

N.C

N.C
N.C
N.C
R/B
RE

CE

N.C
Vcc
Vss
N.C

CLE
ALE

WE
WP
N.C
N.C

N.C
N.C

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

DNU

DNU

DNU

DNU

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FLASH MEMORY

N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C

48 - WSOP1 - 1217F

#1

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP
(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0

°

~

8

°

0.45~0.75

5

K9F2808U0C

PIN DESCRIPTION

Pin Name Pin Function

DATA INPUTS/OUTPUTS

I/O

0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.

FLASH MEMORY

CLE

ALE

CE

RE

WE

WP

R/B

Vcc

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE

CHIP ENABLE

The CE

input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE
read operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE

WRITE ENABLE

The WE

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE

pulse.

WRITE PROTECT

The WP

pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP

READY/BUSY OUTPUT

The R/B

output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

OUTPUT BUFFER POWER

Q

Vcc

Q is the power supply for Output Buffer.

Vcc

Q is internally connected to Vcc, thus should be biased to Vcc.

with ALE high.

control during

which also increments the internal column address counter by one.

pin is active low.

signal.

Vcc

Vss GROUND

N.C

GND

DNU

NOTE :
Connect all V
Do not leave V

POWER

V

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

GND INPUT FOR ENABLING SPARE AREA

To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.

DO NOT USE

Leave it disconnected.

CC and VSS pins of each device to common power supply outputs.

CC or VSS disconnected.

6

K9F2808U0C

Figure 1-1. K9F2808U0C FUNCTIONAL BLOCK DIAGRAM

VCC

SS

V

FLASH MEMORY

A9 - A23

X-Buffers
Latches
& Decoders

A0 - A7

Y-Buffers
Latches
& Decoders

A8

Command

Command

Register

CE
RE
WE

Control Logic

& High Voltage

Generator

CLE ALE

WP

Figure 2-1. K9F2808U0C ARRAY ORGANIZATION

128M + 4M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 32768

Page Register & S/A

Y-Gatin g

I/O Buffers & Latches

Global Buffers

1 Block =32 Pages
= (16K + 512) Byte

Output

Driver

VCC/VCCQ
VSS

I/0 0

I/0 7

32K Pages
(=1,024 Blocks)

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

512Byte 16 Byte

Page Register

512 Byte

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 L*

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

8 is set to "Low" or "High" by the 00h or 01h Command.

* A

* The device ignores any additional input of address cycles than reguired.

* L must be set to "Low".

0 A1 A2 A3 A4 A5 A6 A7

1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 1024 Blocks
= 132 Mbits

8 bit

I/O 0 ~ I/O 7

16 Byte

Column Address
Row Address

(Page Address)

7

K9F2808U0C

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F2808U0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc­tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 1024 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is pro­hibited on the K9F2808U0C.
The K9F2808U0C has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high perfor­mance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O’s by bringing WE
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com­mands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution.
The 16K-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low
row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the
required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are
selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F2808U0C.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.

to low while CE is low. Data is latched on the rising edge of WE. Command Latch

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1

Read 2

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Block Erase 60h D0h

Read Status 70h - O

NOTE: 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on 2nd half of register by the 01h command, start pointer is automatically moved to

1st half register(00h) on the next cycle.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

00h/01h

50h

(1)

-

-

8

K9F2808U0C

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

VIN/OUT -0.6 to + 4.6

Voltage on any pin relative to V

Temperature Under Bias

Storage Temperature

K9F2808U0C-XCB0

K9F2808U0C-XIB0 -40 to +125

K9F2808U0C-XCB0

K9F2808U0C-XIB0

SS

V

CC -0.6 to + 4.6

V

CCQ -0.6 to + 4.6

T

BIAS

T

STG -65 to +150 °C

-10 to +125

V

°C

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F2808U0C-XCB0 :TA=0 to 70°C, K9F2808U0C-XIB0:TA=-40 to 85°C)

Parameter Symbol Min Typ. Max Unit

Supply Voltage V

Supply Voltage V

Supply Voltage V

CC 2.7 3.3 3.6 V

CCQ 2.7 3.3 3.6 V

SS 000V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions Min Typ Max Unit

Operating

Current

Sequential Read I

Program I

Erase I

Stand-by Current(TTL) I

Stand-by Current(CMOS) I

Input Leakage Current I

Output Leakage Current I

Input High Voltage V

Input Low Voltage, All inputs V

Output High Voltage Level V

Output Low Voltage Level V

Output Low Current(R/B

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

)IOL(R/B)VOL=0.4V 8 10 - mA

CC1

CC2--1020

CC3--1020

SB1CE=VIH, WP=0V/VCC -- 1

SB2CE=VCC-0.2, WP=0V/VCC -10 50

LI VIN=0 to Vcc(max) - - ±10

LO VOUT=0 to Vcc(max) - - ±10

IH*

IL* --0.3-0.8

OH IOH=-400µA2.4--

OL IOL=2.1mA - - 0.4

tRC=50ns, CE
IOUT=0mA

I/O pins 2.0 - VCCQ+0.3

Except I/O pins 2.0 - V

=VIL

-10 20

CC+0.3

mA

µA

V

9

K9F2808U0C

FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Ty p. Max Unit

Valid Block Number N

NOTE :

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.

VB 1004 - 1024 Blocks

. Do not erase or program

3. Minimum 502 valid blocks are guaranteed for each contiguous 64Mb memory space.

AC TEST CONDITION

(K9F2808U0C-XCB0 :TA=0 to 70°C, K9F2808U0C-XIB0:TA=-40 to 85°C
K9F2808U0C : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F2808U0C

Input Pulse Levels 0.4V to 2.4V

Input Rise and Fall Times 5ns

Input and Output Timing Levels 1.5V

Output Load (Vcc

Output Load (Vcc

Q:3.0V +/-10%) 1 TTL GATE and CL=50pF

Q:3.3V +/-10%) 1 TTL GATE and CL=100pF

CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

I/O VIL=0V - 10 pF

IN VIN=0V - 10 pF

MODE SELECTION

CLE ALE CE WE RE GND WP Mode

HL L H X X

Read Mode

Command Input

L H L H X X Address Input(3clock)

HL L H X H

Write Mode

Command Input

L H L H X H Address Input(3clock)

L L L H L H Data Input

L L L H L X Data Output

LL L H H

XX X X H

L

L

X During Read(Busy)

X During Read(Busy)

X X X X X L H During Program(Busy)

X X X X X X H During Erase(Busy)

X

(1)

X

XX H X X 0V

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

X X X X L Write Protect

(2)

Stand-by

CC

0V/V

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time t

Number of Partial Program Cycles
in the Same Page

Main Array

Spare Array - - 3 cycles

Block Erase Time t

NOTE : Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of

°C .

25

PROG - 200 500 µs

Nop

BERS -23ms

--2cycles

10