SAMSUNG K9F1G08Q0A Technical data

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

K9F1G08Q0A K9F1G08U0A

Document Title

128M x 8 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No

0.0

0.1

0.2

0.3

History

1. Initial issue

1. The tADL(Address to Data Loading Time) is added.

- tADL Minimum 100ns (Page 11, 23~26)

- tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation.

2. Added Addressing method for program operation

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

1. PKG(TSOP1, WSOP1) Dimension Change

Draft Date

Aug. 24. 2003 Jan. 27. 2004

Apr. 23. 2004

May. 19. 2004

Remark

Advance Preliminary

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.

K9F1G08Q0A K9F1G08U0A

FLASH MEMORY

128M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F1G08Q0A 1.70 ~ 1.95V K9F1G08U0A-Y,P K9F1G08U0A-V,F WSOP1

2.7 ~ 3.6V

FEATURES

• Voltage Supply

-1.8V device(K9F1G08Q0A): 1.70V~1.95V

-3.3V device(K9F1G08U0A): 2.7 V ~3.6 V

• Organization

- Memory Cell Array : (128M + 4,096K)bit x 8bit

- Data Register : (2K + 64)bit x8bit

- Cache Register : (2K + 64)bit x8bit

• Automatic Program and Erase

- Page Program : (2K + 64)Byte

- Block Erase : (128K + 4K)Byte

• Page Read Operation

- Page Size : 2K-Byte

- Random Read : 25µs(Max.)

- Serial Access : 30ns(Min.) : (K9F1G08U0A) 50ns(Min.) : (K9F1G08Q0A)

• Fast Write Cycle Time

- Program time : 300µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Cache Program Operation for High Performance Program

• Intelligent Copy-Back Operation

• Unique ID for Copyright Protection

• Package :

- K9F1G08U0A-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1G08U0A-VIB0 48 - Pin WSOP I (12X17X0.7mm)

- K9F1G08U0A-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1G08U0A-FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1G08U0A-V,F(WSOPI ) is the same device as K9F1G08U0A-Y,P(TSOP1) except package type.

Only available in MCP

TSOP1

GENERAL DESCRIPTION

Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-byte page and an erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 50ns (30ns, K9F1G08U0A) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08X0A′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

K9F1G08Q0A K9F1G08U0A

PIN CONFIGURATION (TSOP1)

K9F1G08X0A-YCB0,PCB0/YIB0,PIB0

X8 X8

N.C

N.C N.C N.C N.C N.C N.C R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WP N.C N.C N.C N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-pin TSOP1

Standard Type 12mm x 20mm

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

FLASH MEMORY

48 - TSOP1 - 1220AF

+0.07

-0.03

0.20

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197

#24

TYP

0.25

0.010

0~8°

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#48

#25

Unit :mm/Inch

MAX

0.10

0.004

0.25

0.010

( )

MAX

12.00

0.472

0.488

12.40

1.00±0.05

0.039±0.002

1.20 MAX

+0.075

0.035 +0.003

-0.001

0.125

0.005

0.047

0.05

0.002

MIN

0.45~0.75

0.018~0.030

0.50

( )

0.020

K9F1G08Q0A K9F1G08U0A

PIN CONFIGURATION (WSOP1)

K9F1G08U0A-VIB0,FIB0

N.C

N.C N.C

N.C N.C R/B RE

N.C Vcc Vss N.C

CLE ALE

WP N.C N.C

N.C N.C

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DNU

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

FLASH MEMORY

N.C N.C DNU N.C I/O7 I/O6 I/O5 I/O4 N.C DNU N.C Vcc Vss N.C DNU N.C I/O3 I/O2 I/O1 I/O0 N.C DNU N.C N.C

48 - WSOP1 - 1217F

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP

(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0.45~0.75

K9F1G08Q0A K9F1G08U0A

PIN DESCRIPTION

Pin Name Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled.

FLASH MEMORY

CLE

ALE

R/B

Vcc

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

POWER

VCC is the power supply for device.

Vss GROUND

N.C

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.

NO CONNECTION

Lead is not internally connected.

K9F1G08Q0A K9F1G08U0A

Figure 1-1. K9F1G08X0A (X8) Functional Block Diagram

VCC VSS

FLASH MEMORY

A12 - A27

A0 - A11

Command

CE RE WE

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

Control Logic

& High Voltage

Generator

CLE

ALE PRE

Figure 2-1. K9F1G08X0A (X8) Array Organization

1024M + 32M Bit

NAND Flash

ARRAY

(2048 + 64)Byte x 65536

Data Register & S/A

Cache Register

Y-Gating

I/O Buffers & Latches

Global Buffers

1 Block = 64 Pages (128K + 4k) Byte

Output

Driver

VCC VSS

I/0 0

I/0 7

64K Pages (=1,024 Blocks)

2K Bytes 64 Bytes

Page Register

2K Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A8 A9 A10 A11 *L *L *L *L

3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low". * The device ignores any additional input of address cycles than required.

1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 1024 Blocks = 1056 Mbits

8 bit

I/O 0 ~ I/O 7

64 Bytes

Column Address Column Address

Row Address Row Address

K9F1G08Q0A K9F1G08U0A

Product Introduction

The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 columns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially connected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08X0A.

The K9F1G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte physical space requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1G08X0A.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed.

FLASH MEMORY

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 00h 30h Read for Copy Back 00h 35h Read ID 90h Reset FFh - O Page Program 80h 10h Cache Program 80h 15h Copy-Back Program 85h 10h Block Erase 60h D0h Random Data Input Random Data Output Read Status 70h O

85h 05h E0h

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Command not specified in command sets table is not permitted to be entered to the device, which can raise erroneous operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

K9F1G08Q0A K9F1G08U0A

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Voltage on any pin relative to VSS

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F1G08X0A-XCB0 K9F1G08X0A-XIB0 -40 to +125 K9F1G08X0A-XCB0 K9F1G08X0A-XIB0

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

VCC -0.2 to + 2.45 -0.6 to + 4.6

TBIAS

TSTG -65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage VCC 1.70 1.8 1.95 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 0 0 0 V

K9F1G08Q0A(1.8V)

Min Typ. Max Min Typ. Max

1.8V DEVICE 3.3V/2.65V DEVICE

-10 to +125

K9F1G08U0A(3.3V)

FLASH MEMORY

Rating

Unit

°C

Unit

K9F1G08Q0A K9F1G08U0A

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

K9F1G08Q0A K9F1G08U0A

Parameter Symbol Test Conditions

Min Typ Max Min Typ Max

Operating

Current

Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1

Stand-by Current(CMOS) ISB2

Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10

Input High Voltage VIH* - 0.8xVCC -

Input Low Voltage, All inputs VIL* - -0.3 - 0.2xVcc -0.3 - 0.2xVcc

Output High Voltage Level VOH

Output Low Voltage Level

Output Low Current(R/B) IOL(R/B)

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

Page Read with Serial Access

Program ICC2 - - 10 20 - 15 30 Erase ICC3 - - 10 20 - 15 30

tRC=50ns, CE=VIL

ICC1

IOUT=0mA

CE=VCC-0.2, WP=0V/VCC

K9F1G08Q0A :IOH=-100µA K9F1G08U0A :IOH=-400µA

K9F1G08Q0A :IOL=100uA

VOL

K9F1G08U0A :IOL=2.1mA K9F1G08Q0A :VOL=0.1V

K9F1G08U0A :VOL=0.4V

- 10 20 - 15 30

- 10 50 - 10 50

Vcc

-0.1

3 4 - 8 10 - mA

- - 2.4 - -

- - 0.1 - - 0.4

FLASH MEMORY

VCC

+0.3

0.8xVcc -

VCC

+0.3

Unit1.8V 3.3V

µA

K9F1G08Q0A K9F1G08U0A

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 1004 - 1024 Blocks

NOTE :

1. The K9F1G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

AC TEST CONDITION

(K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C K9F1G08Q0A : Vcc=1.70V~1.95V, K9F1G08U0A : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F1G08Q0A K9F1G08U0A

Input Pulse Levels 0V to Vcc 0V to Vcc Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels Vcc/2 Vcc/2 Output Load 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

FLASH MEMORY

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE ALE CE WE RE WP Mode

H L L H X

L H L H X Address Input(4clock)

H L L H H

L H L H H Address Input(4clock) L L L H H Data Input

L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X X H X X

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

(1)

X X X L Write Protect

0V/VCC

(2)

Read Mode

Write Mode

Stand-by

Command Input

K9F1G08Q0A K9F1G08U0A

Program / Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 300 700 µs Dummy Busy Time for Cache Program tCBSY 3 700

Number of Partial Program Cycles in the Same Page

Block Erase Time tBERS - 2 3 ms

NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in

Main Array

Spare Array - - 4 cycles

Nop

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol

CLE setup Time tCLS 25 10 - - ns CLE Hold Time tCLH 10 5 - - ns CE setup Time tCS 35 15 - - ns CE Hold Time tCH 10 5 - - ns WE Pulse Width tWP ALE setup Time tALS 25 10 - - ns ALE Hold Time tALH 10 5 - - ns Data setup Time tDS 20 10 - - ns Data Hold Time tDH 10 5 - - ns Write Cycle Time tWC 45 30 - - ns WE High Hold Time tWH 15 10 - - ns ALE to Data Loading Time tADL

NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

K9F1G08Q0A K9F1G08U0A K9F1G08Q0A K9F1G08U0A

100

Min Max

(1)

- - 4 cycles

15 - - ns

(1)

100

FLASH MEMORY

µs

Unit

- - ns

K9F1G08Q0A K9F1G08U0A

AC Characteristics for Operation

Parameter Symbol

Data Transfer from Cell to Register tR - - 25 25 µs ALE to RE Delay tAR 10 10 - - ns CLE to RE Delay tCLR 10 10 - - ns Ready to RE Low tRR 20 20 - - ns RE Pulse Width tRP 25 15 - - ns WE High to Busy tWB - - 100 100 ns Read Cycle Time tRC 50 30 - - ns RE Access Time tREA - - 30 18 ns CE Access Time tCEA - - 45 23 ns RE High to Output Hi-Z tRHZ - - 30 30 ns CE High to Output Hi-Z tCHZ - - 20 20 ns RE or CE High to Output hold tOH 15 15 - - ns RE High Hold Time tREH 15 10 - - ns Output Hi-Z to RE Low tIR 0 0 - - ns WE High to RE Low tWHR 60 60 - - ns Device Resetting Time

(Read/Program/Erase)

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

tRST - -

K9F1G08Q0A K9F1G08U0A K9F1G08Q0A K9F1G08U0A

Min Max

FLASH MEMORY

5/10/500

(1)

5/10/500

(1)

Unit

µs

+ 25 hidden pages