SAMSUNG K7N803601B Technical data

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K7N803601B
K7N801801B

Document Title

256Kx36 & 512Kx18-Bit Pipelined NtRAM

Revision History

256Kx36 & 512Kx18 Pipelined NtRAM

TM

TM

Rev. No.

0.0

0.1

0.2

1.0

2.0

2.1

3.0

History

1. Initial document.

1. Add x32 org part and industrial temperature part

1. change scan order(1) form 4T to 6T at 119BGA(x18)

1. Final spec release

2. Change I

Change ordering information( remove 225MHz at Nt-Pipelined)

1. Delete 119BGA package

1. Remove x32 organization

SB2 form 50mA to 60mA

Draft Date

May. 18. 2001

Aug. 11. 2001

Aug. 28 .2001

Nov. 16. 2001

April. 01. 2002

April. 04. 2003

Nov. 17. 2003

Remark

Preliminary

Preliminary

Preliminary

Final

Final

Final

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques­tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Nov. 2003

Rev 3.0

K7N803601B
K7N801801B

8Mb NtRAM(Flow Through / Pipelined) Ordering Information

Org. Part Number Mode VDD

K7M801825B-QC(I)65/75 FlowThrough 3.3 6.5/7.5 ns

K7N801801B-QC(I)16/13 Pipelined 3.3 167/133 MHz

512Kx18

256Kx36

K7N801809B-QC(I)25 Pipelined 3.3 250 MHz

K7N801845B-QC(I)16/13 Pipelined 2.5 167/133 MHz

K7N801849B-QC(I)25 Pipelined 2.5 250MHz

K7M803625B-QC(I)65/75 FlowThrough 3.3 6.5/7.5 ns

K7N803601B-QC(I)16/13 Pipelined 3.3 167/133 MHz

K7N803609B-QC(I)25 Pipelined 3.3 250 MHz

K7N803645B-QC(I)16/13 Pipelined 2.5 167/133 MHz

K7N803649B-QC(I)25 Pipelined 2.5 250 MHz

256Kx36 & 512Kx18 Pipelined NtRAM

Speed

FT ; Access Time(ns)

Pipelined ; Cycle Time(MHz)

PKG Temp

Commercial

Temperature

Q:

100TQFP

Industrial

Temperature

TM

C:

Range

I:

Range

- 2 -

Nov. 2003

Rev 3.0

K7N803601B
K7N801801B

256Kx36 & 512Kx18 Pipelined NtRAM

TM

256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAM

GENERAL DESCRIPTIONFEATURES

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.

• Byte Writable Function.

• Enable clock and suspend operation.

• Single

READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

• Α interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• 100-TQFP-1420A

• Operating in commercial and industrial temperature range.

FAST ACCESS TIMES

PARAMETER Symbol -16 -13 Unit

Cycle Time t

Clock Access Time t

Output Enable Access Time t

CYC 6.0 7.5 ns

CD 3.5 4.2 ns

OE 3.5 3.8 ns

The K7N803601B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The NtRAM
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B and K7N801801B are implemented with
SAMSUNG′s high performance CMOS technology and is avail­able in 100pin TQFP and Multiple power and ground pins mini­mize ground bounce.

TM

, or No Turnaround Random Access Memory uti-

TM

LOGIC BLOCK DIAGRAM

A [0:17] or

A [0:18]

CLK

LOGIC

CKE

CS

1

CS

2

CS

2

ADV

WE

BW

x

(x=a,b,c,d or a,b)

OE
ZZ

0

~ DQd

7

DQa
DQPa ~ DQPd

or DQa0 ~ DQb8

CONTROL

ADDRESS

REGISTER

K

REGISTER

CONTROL

A2~A

LBO

A0~A

17

or A2~A18

WRITE

ADDRESS

REGISTER

BURST

ADDRESS

1

COUNTER

CONTROL

LOGIC

A

WRITE

ADDRESS

REGISTER

′0~A

′

1

256Kx36 , 512Kx18

MEMORY

ARRAY

DATA-IN

K

REGISTER

DATA-IN

K

REGISTER

OUTPUT

K

REGISTER

BUFFER

36 or 18

NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.

- 3 -

Nov. 2003

Rev 3.0

K7N803601B
K7N801801B

PIN CONFIGURATION(TOP VIEW)

6

A7

CS1

A

CS2

BWcBWbBW

BWd

256Kx36 & 512Kx18 Pipelined NtRAM

a

2

CS

VDD

VSS

CLKWECKEOEADV

N.C.

A17A8

9

A

TM

DQPc

DQc
DQc1
VDDQ

VSSQ
DQc2
DQc3
DQc4
DQc5

VSSQ
VDDQ
DQc6
DQc7

VDD
VDD
VDD

VSS
DQd0
DQd1
VDDQ

VSSQ
DQd2
DQd3
DQd4
DQd5

VSSQ
VDDQ
DQd6
DQd7

DQPd

DQPb
DQb
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
VDD
VDD
ZZ
DQa
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa

7

7

48

82

49

81

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

9998979695949392919089888786858483

1

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

100

2
3
4
5
6
7
8
9

100 Pin TQFP

(20mm x 14mm)

K7N803601B(256Kx36)
K7N803201B(256Kx32)

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

0

LBO

0

A5

N.C.

A

A1

A2

A3

A4

DD

VSS

V

N.C.

A10

N.C.

N.C.

A13

A12

A11

16

A

A15

A14

PIN NAME

SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.

- 4 -

V

DD

VSS
N.C.

0~a7

DQa
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd

V

DDQ

VSSQ

Power Supply(+3.3V)
Ground
No Connect

Data Inputs/Outputs

Output Power Supply
(3.3V or 2.5V)
Output Ground

14,15,16,41,65,66,91
17,40,67,90
38,39,42,43,84

52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

0 - A17

A

ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b,c,d)
OE
ZZ
LBO

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A

Address Inputs

Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control

0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31

Nov. 2003

Rev 3.0

K7N803601B
K7N801801B

PIN CONFIGURATION(TOP VIEW)

6

A7

CS1

A

256Kx36 & 512Kx18 Pipelined NtRAM

a

2

CS

N.C.

BW

BWb

VDD

VSS

CLKWECKEOEADV

N.C.

CS2

N.C.

A18A8

9

A

TM

N.C.
N.C.
N.C.

DDQ

V

VSSQ

N.C.

N.C.
DQb
DQb7

VSSQ
VDDQ
DQb6
DQb5

VDD
VDD
VDD

VSS
DQb4
DQb3
VDDQ

VSSQ
DQb2
DQb1
DQb0

N.C.

SSQ

V
VDDQ

N.C.
N.C.
N.C.

48

49

82

50

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

10

A
N.C.
N.C.

DDQ

V
VSSQ
N.C.
DQa
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
VDD
VDD
ZZ
DQa
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.

SSQ

V
VDDQ
N.C.
N.C.
N.C.

0

5

9998979695949392919089888786858483

1

100

2
3
4
5
6
7
8

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

100 Pin TQFP

(20mm x 14mm)

K7N801801B(512Kx18)

42

41

40

39

38

37

36

35

34

33

32

43

44

45

46

47

LBO

0

A5

N.C.

A

A1

A2

A3

A4

DD

VSS

V

N.C.

A11

N.C.

N.C.

A14

A13

A12

17

A

A16

A15

PIN NAME

SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.

0 - A18

A

ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b)
OE
ZZ
LBO

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A

Address Inputs

Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control

0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31

V

DD

VSS
N.C.

DQa

0~a8

DQb0~b8

VDDQ

VSSQ

- 5 -

Power Supply(+3.3V)
Ground
No Connect

Data Inputs/Outputs

Output Power Supply
(3.3V or 2.5V)
Output Ground

14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96

58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

Nov. 2003

Rev 3.0

K7N803601B
K7N801801B

256Kx36 & 512Kx18 Pipelined NtRAM

TM

FUNCTION DESCRIPTION

The K7N803601B and K7N801801B is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.

, LBO and ZZ) are synchronized to rising clock edges.

Clock Enable(CKE
inputs are ignored and the internal device registers will hold their previous values.

TM

NtRAM
are active .
Output Enable(OE

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE
be driven low for the device to drive out the requested data.

Write operation occurs when WE
lined NtRAM
At the first rising edge of the clock, WE
later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO
And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.

latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

) can be used to disable the output at any given time.

is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

TM

uses a late-late write cycle to utilize 100% of the bandwidth.

is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-

and address are registered, and the data associated with that address is required two cycle

pin. When this pin is low, linear burst sequence is selected.

must

BURST SEQUENCE TABLE (Interleaved Burst, LBO=High)

LBO PIN HIGH

First Address

Fourth Address

Case 1 Case 2 Case 3 Case 4

A1 A0 A1 A0 A1 A0 A1 A0

0
0
1
1

0
1
0
1

0
0
1
1

1
0
1
0

1
1
0
0

0
1
0
1

1
1
0
0

1
0
1
0

BQ TABLE (Linear Burst, LBO=Low)

LBO PIN LOW

First Address

Fourth Address

Note : 1. LBO

pin must be tied to High or Low, and Floating State must not be allowed.

Case 1 Case 2 Case 3 Case 4

A1 A0 A1 A0 A1 A0 A1 A0

0
0
1
1

0
1
0
1

0
1
1
0

- 6 -

1
0
1
0

1
1
0
0

0
1
0
1

1
0
0
1

Nov. 2003

Rev 3.0

1
0
1
0