SAMSUNG K6X4016T3F Technical data

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K6X4016T3F Family CMOS SRAM

Document Title

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No

0.0

0.1

1.0

History

Initial draft

Revised

- Added Commercial product

- Deleted 44-TSOP2-400R Package Type.

- Added 55ns product(@ 3.0V~3.6V)

Finalized
Revised

- Changed ICC(Operating power supply current) from 4mA to 2mA

- Changed ICC1(Average operating current) from 4mA to 3mA

- Changed ICC2(Average operating current) from 40mA to 25mA

- Changed ISB1(Standby Current(CMOS), Commercial)
from 15µA to 10µA

- Changed ISB1(Standby Current(CMOS), Industrial)
from 20µA to 10µA

- Changed ISB1(Standby Current(CMOS), Automotive)
from 30µA to 20µA

- Changed IDR(Data retention current, Commercial)
from 15µA to 10µA

- Changed IDR(Data retention current, Industrial)
from 20µA to 10µA

- Changed IDR(Data retention current, Automotive)
from 30µA to 20µA

Draft Date

July 29, 2002

December 2, 2002

August 8, 2003

Remark

Preliminary

Preliminary

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

FEATURES

• Process Technology: Full CMOS

• Organization: 256K x16

• Power Supply Voltage: 2.7~3.6V

• Low Data Retention Voltage: 2V(Min)

• Three State Outputs

• Package Type: 44-TSOP2-400F

GENERAL DESCRIPTION

The K6X4016T3F families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support var­ious operating temperature range and have 44-TSOP2 pack­age type for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.

PRODUCT FAMILY

Product Family Operating Temperature Vcc Range Speed(ns)

(ISB1, Max)

K6X4016T3F-B Commercial(0~70°C)
K6X4016T3F-F Industrial(-40~85°C) 10µA

2.7~3.6V

K6X4016T3F-Q Automotive(-40~125°C)

1. This parameter is measured with 30pF test load (Vcc=3.0~3.6V).

2. The parameter is measured with 30pF test load.

PIN DESCRIPTION

A4

1

A3

2

A2

3

A1

4

A0

5

CS

6

I/OI

7

I/O2

8

I/O3

9

10

I/O4

Vcc

11

44-TSOP2

12

Vss
I/O5
I/O6
I/O7
I/O8

WE
A17
A16
A15
A14
A13

13
14
15
16
17
18
19
20
21
22

Forward

Name Function Name Function

CS Chip Select Input Vcc Power
OE Output Enable Input Vss Ground
WE Write Enable Input LB Lower Byte (I/O1~8)

A0~A17 Address Inputs UB Upper Byte (I/O9~16)

I/O1~I/O16 Data Input/Output NC No Connection

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O16

37

I/O15

36

I/O14
I/O13

35

Vss

34

Vcc

33

I/O12

32

I/O11

31

I/O10

30

I/O9

29

NC

28

A8

27

A9

26

A10

25

A11

24

A12

23

551)/702)/85ns

702)/85ns

FUNCTIONAL BLOCK DIAGRAM

Row
Addresses

I/O1~I/O8

I/O9~I/O16

WE
OE

Control

UB

logic

LB
CS

Power Dissipation

Standby

Operating

(ICC2, Max)

10µA

20µA

Clk gen.

Row
select

Data
cont

Data
cont

Data
cont

PKG Type

25mA 44-TSOP2-400F

Precharge circuit.

Vcc
Vss

Memory array

I/O Circuit

Column select

Column Addresses

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

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Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C) Industrial Products(-40~85°C) Automotive Products(-40~125°C)

Part Name Function Part Name Function Part Name Function

1)

K6X4016T3F-TB55
K6X4016T3F-TB70
K6X4016T3F-TB85

1. Operating voltage range is 3.0~3.6V

44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
44-TSOP2-F, 85ns, LL

K6X4016T3F-TF55
K6X4016T3F-TF70
K6X4016T3F-TF85

FUNCTIONAL DESCRIPTION

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

H

1)

X
L H H
L

1)

X
L L H L H Dout High-Z Lower Byte Read Active
L L H H L High-Z Dout Upper Byte Read Active
L L H L L Dout Dout Word Read Active
L
L
L

1. X means don′t care. (Must be in low or high state)

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

H H High-Z High-Z Output Disabled Active

L L H Din High-Z Lower Byte Write Active
L H L High-Z Din Upper Byte Write Active
L L L Din Din Word Write Active

1)

44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
44-TSOP2-F, 85ns, LL

K6X4016T3F-TQ70
K6X4016T3F-TQ85

44-TSOP2-F, 70ns, L
44-TSOP2-F, 85ns, L

High-Z High-Z Deselected Standby
High-Z High-Z Output Disabled Active

ABSOLUTE MAXIMUM RATINGS

1)

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.2 to VCC+0.3(max. 3.9V) V ­Voltage on Vcc supply relative to Vss VCC -0.2 to 3.9 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

0 to 70

-40 to 85 K6X4016T3F-F

°C

K6X4016T3F-B

-40 to 125 K6X4016T3F-Q

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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Revision 1.0

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K6X4016T3F Family CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS

Item Symbol Min Typ Max Unit

Supply voltage Vcc
Ground Vss 0 0 0 V

Input high voltage VIH 2.2 ­Input low voltage VIL

Note:

1. Commercial Product: TA=0 to 70°C, otherwise specified.
Industrial Product: TA=-40 to 85°C, otherwise specified.
Automotive Product: TA=-40 to 125°C, otherwise specified.

2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns.

3. Undershoot: -2.0V in case of pulse width ≤ 30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

1)

(f=1MHz, TA=25°C)

Item Symbol Test Condition Min Max Unit

1)

2.7

-0.2

3.0/3.3

3)

- 0.6 V

3.6

Vcc+0.2

2)

V

V

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIL=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 2 mA

Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,

ICC1

Average operating current

Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA

Standby Current(CMOS) ISB1

VIN≤0.2V or VIN≥Vcc-0.2V
Cycle time=Min2), 100% duty, IIO=0mA, CS=VIL,

ICC2

VIN=VIH or VIL

CS≥Vcc-0.2V, Other
inputs=0~Vcc

K6X4016T3F-B
K6X4016T3F-F
K6X4016T3F-Q - - 20 µA

- - 3 mA

- - 25 mA

- 10 µA

-

- 10 µA

-

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Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL

1.Including scope and jig capacitance

AC CHARACTERISTICS

( VCC=2.7~3.6V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C )

Parameter List Symbol

Read cycle time tRC 55 - 70 - 85 - ns
Address access time tAA - 55 - 70 - 85 ns
Chip select to output tCO - 55 - 70 - 85 ns
Output enable to valid output tOE - 25 - 35 - 40 ns
LB, UB valid to data output tBA - 25 - 35 - 40 ns

Read

Write

1. Voltage range is 3.0V~3.6V for commercial and industrial product.

Chip select to low-Z output tLZ 10 - 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - 5 - ns
LB, UB enable to low-Z output tBLZ 5 - 5 - 5 - ns
Output hold from address change tOH 10 - 10 - 10 - ns
Chip disable to high-Z output tHZ 0 20 0 25 0 25 ns
OE disable to high-Z output tOHZ 0 20 0 25 0 25 ns
LB, UB disable to high-Z output tBHZ 0 20 0 25 0 25 ns
Write cycle time tWC 55 - 70 - 85 - ns
Chip select to end of write tCW 45 - 60 - 70 - ns
Address set-up time tAS 0 - 0 - 0 - ns
Address valid to end of write tAW 45 - 60 - 70 - ns
Write pulse width tWP 40 - 55 - 60 - ns
Write recovery time tWR 0 - 0 - 0 - ns
Write to output high-Z tWHZ 0 20 0 25 0 25 ns
Data to write time overlap tDW 25 - 30 - 35 - ns
Data hold from write time tDH 0 - 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - 5 - ns
LB, UB valid to end of write tBW 45 - 60 - 70 - ns

Min Max Min Max Min Max

55ns

)

1

)

1

CL

Speed Bins

70ns 85ns

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 3.6 V

K6X4016T3F-B

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V

Data retention set-up time tSDR
Recovery time tRDR 5 - -

See data retention waveform

K6X4016T3F-F 10 µA
K6X4016T3F-Q 20 µA

- -

0 - -

5

Typ

Max Unit

10

Revision 1.0

August 2003

µA

ms

K6X4016T3F Family CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tAA

Data Valid

tRC

tOH

tCO

tHZ

tBA

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

UB, LB

OE

tBLZ

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

High-Z

tLZ

tOE

tOLZ

Data Valid

tBHZ

tOHZ

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Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tWR(4)

CS

UB, LB

tCW(2)

tAW

tBW

tWP(1)

WE

Data in

Data out

Data Undefined

tAS(3)

High-Z

tWHZ

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

tAS(3)

CS

UB, LB

WE

Data in

tWC

tCW(2)

tAW

tBW

tWP(1)

tDW

Data Valid

tDW

Data Valid

tDH

High-Z

tOW

tWR(4)

tDH

Data out

High-Z High-Z

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Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

CS

UB, LB

WE

Data in

tCW(2)

tAW

tBW

tAS(3)

tWP(1)

tDW

tWR(4)

tDH

Data Valid

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

High-Z

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

2.7V

2.2V

VDR

CS
GND

tSDR

Data Retention Mode

CS≥VCC - 0.2V

tRDR

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Revision 1.0

August 2003

K6X4016T3F Family CMOS SRAM

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#44 #23

#1

( )

0.805

0.032

18.81

0.741

18.41±0.10

0.725±0.004

0.35± 0.10

0.014±0.004

MAX.

0.0315

#22

0.80

MIN.

0.05

0.002

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

1.20

0.047

MAX.

0.004

0.10

MAX

10.16

5

1

.

0

0

.

0

0.25

( )

0.010

0.400

0

1

.

0

+

5

0

.

0

­0

0

.

0

+

0

.

6

0

0

-

Unit: millimeter(inch)

0~8°

4

2

0

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

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Revision 1.0

August 2003