Samsung K5P2880YCM-T085 Datasheet

K5P2880YCM - T085

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Document Title

Multi-Chip Package MEMORY

128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

Revision No.

0.0

Remark

Advanced Information

History

Initial issue.

Draft Date

Jun. 11th 2001

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html

K5P2880YCM - T085

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Multi-Chip Package MEMORY

128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM

The K5P2880YCM featuring single 3.0V power supply is a Multi ChipPackage Memory which combines 128Mbit Nand Flash and 8Mbit full CMOS SRAM. The 128Mbit Flash memory is organized as 16M x8 bit and the 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. In 128Mb NAND Flash a 528-byte page program can be typically achieved within 300us and an 16K-byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. The I/O pins serve as the ports for address and data input/output as well as command inputs. Even the write-intensive systems can take advantage of the FLASH′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 8Mbit SRAM supports the low data retention voltage for battery backup operation with low current. The K5P2880YCM is suitable for use in data memory of mobil communication system to reduce not only mount area but also power consumption. This device is available in 69-ball TBGA Type.

FEATURES

• Power Supply voltage : 2.7V to 3.3 V

• Organization

- Flash : (16M + 512K)bit x 8bit

- SRAM : 1M x 8 / 512K x 16 bit

• Access Time

- Flash : Random access : 10us(Max.), Serial read : 50ns(Min.)

- SRAM : 85 ns

• Power Consumption (typical value)

- Flash Read Current : 10 mA(@20MHz) Program/Erase Current : 10 mA Standby Current : 10 µA

- SRAM Operating Current : 20 mA Standby Current : 0.5 µA

• Flash Automatic Program and Erase Page Program : (512 + 16)Byte Block Erase : (16K + 512)Byte

• Flash Fast Write Cycle Time Program time : 300us(Typ.) Block Erase Time : 2ms(Typ.)

• Flash Endurance : 100,000 Program/Erase Cycles Minimum

• Flash Data Retention : 10 years

• SRAM Data Retention : 1.5 V (min.)

• Operating Temperature : -25°C ~ 85°C

• Package : 69 - ball TBGA Type - 8 x 13mm, 0.8 mm pitch

GENERAL DESCRIPTION

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

BALL CONFIGURATION

Ball Name Description

A0 to A18 Address Input Balls (SRAM)

D/Q0 to D/Q7 Data Input/Output Balls (Common)

D/Q8 to D/Q15 Data Input/Output Balls (SRAM)

Vccs Power Supply (SRAM)

VccF Power Supply (Flash Memory)

VccQF

Output Buffer Power (Flash Memory) This input may be tied directly to VCCF.

Vss Ground (Common)

UB Upper Byte Enable (SRAM)

LB Lower Byte Enable (SRAM)

WP Write Protection (Flash Memory) CLE Command Latch Enable(Flash Memory) ALE Address Latch Enable(Flash Memory)

BYTES Byte Control (SRAM)

SA Address Inputs (SRAM)

CEF Chip Enable (Flash Memory)

CS1S Chip Enable (SRAM Low Active) CS2S Chip Enable (SRAM High Active)

WE Write Enable (Common)

OE/RE Output Enable (Common)

R/B Ready/Busy (Flash memory)

N.C No Connection

A3A

CEf

CS2sN.C

A5A18AL

N.CA9

OE/REDQ9DQ3

DQ4DQ13

C D

CLE

A10

DQ1

A17

A11

A12

A13

N.C

A14

A16

R/B

Vcc

DQ8

DQ2DQ11

DQ5

DQ1

CS1

DQ0DQ10Vc

QFVccSDQ1

DQ7

Vss

BYT

N.C

Index

BALL DESCRIPTION

69 Ball TBGA , 0.8mm Pitch

Top View (Ball Down)

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Figure 1. FUNCTIONAL BLOCK DIAGRAM

CS1S

Vccs

CS2S

BYTES

512Bytes 16 Bytes

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low"

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 *L

1st half Page Register (=256 Bytes)

2nd half Page Register (=256 Bytes)

32K Pages (=1024 Blocks)

512 Bytes

8 bit

16 Bytes

1 Block =32 Pages = (16K + 512) Bytes

I/O 0 ~ I/O 7

1 Page = 528 Bytes 1 Block = 528 Bytes x 32 Pages = (16K + 512) Bytes 1 Device = 528 Bytes x 32Pages x 1024 Blocks = 132 Mbits

Column Address Row Address (Page Address)

Page Register

Figure 2. Flash ARRAY ORGANIZATION

R/B

WP CEf

ALE

Address(A0 to A18)

128 M bit

Flash Memory

8 M bit

Static RAM

CLE

OE/RE

Vss

Vccf Vss VccQf

DQ0 to DQ15

DQ0 to DQ7

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NAND FLASH PRODUCT INTRODUCTION

Table 1. COMMAND SETS

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle.

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

00h/01h

(1)

50h

Read ID 90h Reset FFh - O Page Program 80h 10h Block Erase 60h D0h Read Status 70h - O

The NAND Flash is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are

located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer

between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that

are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages f

ormed

by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program and rea

operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists of 1024

blocks, and a block is separately erasable by 16K-byte unit. It indicates that the bit by bit erase operation is prohibited o

n the NAND

Flash.

The NAND Flash has addresses multiplexed with 8 I/O′

s. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written throug

I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE

. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle

except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution.

The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low

row address and high row address, in that order. Page Read and Page Program need the same three address cycles following

required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected

by writing specific commands into command register. Table 1 defines the specific commands of the NAND Flash.

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Table 2. FLASH MEMORY OPERATIONS TABLE

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE ALE CE WE RE WP Mode

H L L H X

Read Mode

Command Input L H L H X Address Input(3clock) H L L H H

Write Mode

Command Input L H L H H Address Input(3clock) L L L H H Data Input L L L H X Sequential Read & Data Output L L X H H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X

(1)

X X X L Write Protect

X X H X X

0V/VCC

(2)

Stand-by

Table 3. SRAM OPERATIONS TABLE

1. Word Mode

Note: X means don′t care. (Must be low or high state)

2. Byte Mode

Note: X means don′t care.(Must be low or high state)

1. Address input for byte operation.

CS1 CS2 OE WE BYTE SA LB UB I/O0~7 I/O8~15 Mode Power

H X X X X X X X High-Z High-Z Deselected Standby X L X X X X X X High-Z High-Z Deselected Standby X X X X X X H H High-Z High-Z Deselected Standby

L H H H VCC X L X High-Z High-Z Output Disabled Active L H H H VCC X X L High-Z High-Z Output Disabled Active L H L H VCC X L H Dout High-Z Lower Byte Read Active L H L H VCC X H L High-Z Dout Upper Byte Read Active L H L H VCC X L L Dout Dout Word Read Active L H X L VCC X L H Din High-Z Lower Byte Write Active L H X L VCC X H L High-Z Din Upper Byte Write Active L H X L VCC X L L Din Din Word Write Active

CS1 CS2 OE WE BYTE SA LB UB I/O0~7 I/O8~15 Mode Power

H X X X X X X X High-Z High-Z Deselected Standby X L X X X X X X High-Z High-Z Deselected Standby

L H H H VSS

DNU DNU High-Z DNU Output Disabled Active

L H L H VSS

DNU DNU Dout DNU Lower Byte Read Active

L H X L VSS

DNU DNU Din DNU Lower Byte Write Active

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FLASH MEMORY OPERATION

PAGE READ

Figure 3. Read1 Operation

Start Add.(3Cycle)00h

01h

A0 ~ A7 & A9 ~ A23

Data Output(Sequential)

(00h Command)

1st half array 2nd half array

Data Field Spare Field

(01h Command)*

1st half array 2nd half array

Data Field Spare Field

* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.

CLE

ALE

R/B

I/O0 ~ 7

Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out by sequential RE pulse of 50ns period cycle. High to low transitions of the RE clock take out the data from the selected column address up to the last column address. Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(512 to 527 bytes) may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of spare area while addresses A4 to A7 are ignored. To move the pointer back to the main area, Read1 command(00h/01h) is needed. Figures 3 through 4 show typical sequence and timing for each read operation. Figure 3,4 details the sequence.

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PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state-control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 5). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.

Figure 5. Program & Read Status Operation

80h

A0 ~ A7 & A9 ~ A23

I/O0 ~ 7

R/B

Address & Data Input

I/O0

Pass

528 Byte Data

10h 70h

Fail

tPROG

Figure 4. Read2 Operation

50h

A0 ~ A3 & A9 ~ A23

Data Output(Sequential)

Spare Field

CLE

ALE

R/B

1st half array 2nd half array

Data Field Spare Field

Start Add.(3Cycle)

(A4 ~ A7 : Don't Care)

I/O0 ~ 7

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Figure 6. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A23 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write state-control handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 6 details the sequence.

60h

Block Add. : A9 ~ A23

I/O0 ~ 7

R/B

Address Input(2Cycle)

I/O0

Pass

D0h

70h

Fail

tBERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle.

I/O # Status Definition

I/O0 Program / Erase

"0" : Successful Program / Erase "1" : Error in Program / Erase

I/O1

Reserved for Future

Use

"0" I/O2 "0" I/O3 "0" I/O4 "0" I/O5 "0" I/O6 Device Operation "0" : Busy "1" : Ready I/O7 Write Protect "0" : Protected "1" : Not Protected

Table4. Read Status Register Definition

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Figure 7. Read ID Operation

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 7 shows the operation sequence.

Figure 8. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 8 below.

After Power-up After Reset

Operation Mode Read 1 Waiting for next command

FFhI/O0 ~ 7

R/B

Table5. Device Status

tRST

CLE

I/O0~7

ALE

90h

00h

ECh

Address. 1cycle

Maker code

Device code

tCEA

tAR1

tREA

73h

tWHR

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