SAMSUNG K4S64323LF-S Technical data
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K4S64323LF-S(D)N/U/P
Mobile SDRAM
(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V)
CMOS SDRAM
2Mx32
90FBGA
Revision 1.5
December 2002
Rev. 1.5 Dec 2002
K4S64323LF-S(D)N/U/P
512K x 32Bit x 4 Banks SDRAM
• 2.5V Power Supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock .
• Burst read single-bit write operation.
• DQM for masking.
• Auto & self refresh.
• 64ms refresh period (4K cycle).
• Extended temperature range (-25°C to 85°C).
Industrial Temperature range (-40°C to 85°C) for low power.
• 90balls FBGA( -SXXX -Pb, -DXXX -Pb Free).
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
GENERAL DESCRIPTIONFEATURES
The K4S64323LF is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth and high performance memory system
applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S64323LF-S(D)N/U/P75
K4S64323LF-S(D)N/U/P1H 105MHz(CL=2)
K4S64323LF-S(D)N/U/P1L
K4S64323LF-S(D)N/U/P15
-S(D)N ; Low Power, Operating Temp : -25°C~85°C.
-S(D)U ; Super Low Power, Operating Temp : -25 °C~85°C.
-S(D)P ; Low Power, Operating Temp : -40 °C~85°C.
Notes :
1. In case of 55MHz Frequency, CL1 can be supported.
2. In case of 40MHz Frequency, CL1 can be supported.
3. In case of 33MHz Frequency, CL1 can be supported.
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=3)
66MHz(CL=2/3)
*1
*2
*3
LVCMOS
90FBGA
Pb
(Pb Free)
CLK
ADD
Data Input Register
Bank Select
Refresh Counter
Row Buffer
Address Register
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE DQM
Row Decoder Col. Buffer
Latency & Burst Length
Programming Register
LCAS LWCBR
Timing Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
LWE
LDQM
Sense AMP
Samsung Electronics reserves the right to
*
change products or specification without
notice.
Output BufferI/O Control
DQi
Rev. 1.5 Dec 2002
K4S64323LF-S(D)N/U/P
90-Ball FBGA Package Dimension and Pin Configuration
CMOS SDRAM
1
D
Substrate(4Layer)
< Bottom View*1 >
E
1
5 2 16 3489 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
E
*2: Top View
*1: Bottom View
< Top View*2 >
#A1 Ball Origin Indicator
K4S64323LF-XXXX
E/2
< Top View*2 >
90Ball(6x15) CSP
e
D
D/2
A
A1
z
b
A DQ26 DQ24 VSS VDD DQ23 DQ21
B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E VDDQ DQ31 NC NC DQ16 VSSQ
F VSS DQM3 A3 A2 DQM2 VDD
G A4 A5 A6 A10 A0 A1
H A7 A8 NC NC BA1 NC
J CLK CKE A9 BA0 CS RAS
K DQM1 NC NC CAS WE DQM0
L VDDQ DQ8 VSS VDD DQ7 VSSQ
M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 VSS VDD DQ0 DQ2
DQM0 ~ DQM3 Data Input/Output Mask
SAMS UNG Week
VDDQ/VSSQ Data Output Power/Ground
1 2 3 7 8 9
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A10 Address
BA0 ~ BA1 Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
DQ 0 ~ 31 Data Input/Output
VDD /VSS Power Supply/Ground
[Unit:mm]
Symbol Min Typ Max
A - 1.30 1.40
A
1
E - 11.00 -
E
1
D - 13.00 -
D
1
e - 0.80 b 0.40 0.45 0.50
z - - 0.10
0.30 0.35 0.40
- 6.40 -
- 11.20 -
Rev. 1.5 Dec 2002
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