SAMSUNG K4S64323LF-S Technical data

!

K4S64323LF-S(D)N/U/P

CMOS SDRAM

2Mx32 Mobile SDRAM

90FBGA

(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V)

Revision 1.5

December 2002

Rev. 1.5 Dec 2002

K4S64323LF-S(D)N/U/P

CMOS SDRAM

512K x 32Bit x 4 Banks SDRAM

FEATURES

•2.5V Power Supply.

•LVCMOS compatible with multiplexed address.

•Four banks operation.

•MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).

•All inputs are sampled at the positive going edge of the system clock .

•Burst read single-bit write operation.

•DQM for masking.

•Auto & self refresh.

•64ms refresh period (4K cycle).

•Extended temperature range (-25°C to 85 °C).

Industrial Temperature range (-40°C to 85°C) for low power.

• 90balls FBGA( -SXXX -Pb, -DXXX -Pb Free).

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The K4S64323LF is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

ORDERING INFORMATION

Part No.	Max Freq.	Interface	Package
K4S64323LF-S(D)N/U/P75	133MHz(CL=3)*1
	105MHz(CL=2)
			90FBGA
K4S64323LF-S(D)N/U/P1H	105MHz(CL=2)	LVCMOS	Pb
K4S64323LF-S(D)N/U/P1L	105MHz(CL=3)*2		(Pb Free)
K4S64323LF-S(D)N/U/P15	66MHz(CL=2/3)*3

-S(D)N ; Low Power, Operating Temp : -25°C~85 °C. -S(D)U ; Super Low Power, Operating Temp : -25 °C~85°C. -S(D)P ; Low Power, Operating Temp : -40°C~85 °C.

Notes :

1.In case of 55MHz Frequency, CL1 can be supported.

2.In case of 40MHz Frequency, CL1 can be supported.

3.In case of 33MHz Frequency, CL1 can be supported.

Data Input Register

Bank Select

Control I/O

LWE

LDQM

	Address		CounterRefresh	BufferRow	DecoderRow			512K x 32	AMPSense	BufferOutput
								512K x 32			DQi
								512K x 32
CLK								512K x 32
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR		LDQM
					Timing Register
								* Samsung Electronics reserves the right to
	CLK	CKE		CS	RAS	CAS	WE	DQM	change products or specification without
									notice.

Rev. 1.5 Dec 2002

K4S64323LF-S(D)N/U/P

CMOS SDRAM

90-Ball FBGA Package Dimension and Pin Configuration

D1

	< Bottom View*1 >
				E1
9	8	7	6	5	4	3	2	1
A								e
B
C
D								D
E
F
G
H
J
K								D/2
L
M
N
P
R
				E
						E/2

< Top View*2 >

90Ball(6x15) CSP

1

2

3

7

8

9

A

DQ26

DQ24

VSS

VD D

DQ23

DQ21

B

DQ28

VDDQ

VSSQ

VDDQ

VSSQ

DQ19

C

VSSQ

DQ27

DQ25

DQ22

DQ20

VDDQ

D

VSSQ

DQ29

DQ30

DQ17

DQ18

VDDQ

E

VDDQ

DQ31

NC

NC

DQ16

VSSQ

F

VSS

DQM3

A3

A2

DQM2

VD D

G

A4

A5

A6

A10

A0

A1

H

A7

A8

NC

NC

BA1

NC

J

CLK

CKE

A9

BA0

CS

RAS

K

DQM1

NC

NC

DQM0

CAS

WE

L

VDDQ

DQ8

VSS

VD D

DQ7

VSSQ

M

VSSQ

DQ10

DQ9

DQ6

DQ5

VDDQ

N

VSSQ

DQ12

DQ14

DQ1

DQ3

VDDQ

P

DQ11

VDDQ

VSSQ

VDDQ

VSSQ

DQ4

R

DQ13

DQ15

VSS

VD D

DQ0

DQ2

*2: Top View

Pin Name

Pin Function

CLK

System Clock

Chip Select

CS

A

CKE

Clock Enable

A0

~ A10

Address

A1

BA0 ~ BA1

Bank Select Address

Substrate(4Layer)

b

z

RAS

Row Address Strobe

*1: Bottom View

Column Address Strobe

CAS

< Top View*2 >

Write Enable

WE

DQM0 ~ DQM3

Data Input/Output Mask

#A1 Ball Origin Indicator

DQ 0 ~ 31

Data Input/Output

-K4S64323LF

SAMSUNG

VDD /VSS

Power Supply/Ground

VDDQ/VSSQ

Data Output Power/Ground

[Unit:mm]

Symbol

Min

Typ

Max

A

-

1.30

1.40

A1

0.30

0.35

0.40

E

-

11.00

-

E1

-

6.40

-

D

-

13.00

-

XXXX

Week

D1

-

11.20

-

e

-

0.80

-

b

0.40

0.45

0.50

z

-

-

0.10

Rev. 1.5 Dec 2002