Samsung K4S641632F-TL75, K4S641632F-TL70, K4S641632F-TL60, K4S641632F-TL55, K4S641632F-TL50 Datasheet
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K4S641632F
CMOS SDRAM
64Mbit SDRAM
1M x 16Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
Sept. 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.0.1 Sept. 2001
K4S641632F
CMOS SDRAM
Revision History
Revision 0.0 (June, 2001)
Revision 0.1 (Sep., 2001)
• Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.0.1 Sept. 2001
K4S641632F
1M x 16Bit x 4 Banks Synchronous DRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
GENERAL DESCRIPTIONFEATURES
The K4S641632F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S641632F-TC50/TL50 200MHz(CL=3)
K4S641632F-TC55/TL55 183MHz(CL=3)
K4S641632F-TC60/TL60 166MHz(CL=3)
K4S641632F-TC70/TL70 143MHz(CL=3)
K4S641632F-TC75/TL75 133MHz(CL=3)
K4S641632F-TC1H/TL1H 100MHz(CL=2)
K4S641632F-TC1L/TL1L 100MHz(CL=3)
LVTTL
TSOP(II)
54
CLK
ADD
LCKE
Data Input Register
Bank Select
Refresh Counter
Row Buffer
Address Register
LRAS
LCBR
LRAS LCBR LWE LDQM
Row Decoder Col. Buffer
LCAS LWCBR
Timing Register
1M x 16
1M x 16
1M x 16
1M x 16
Column Decoder
Latency & Burst Length
Programming Register
Sense AMP
LWE
LDQM
Output BufferI/O Control
DQi
CLK CKE CS RAS CAS WE L(U)DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev.0.1 Sept. 2001
K4S641632F
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
PIN FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select
CKE Clock enable
A0 ~ A11 Address
BA0 ~ BA1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
L(U)DQM Data input/output mask
DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground
N.C/RFU
No connection
/reserved for future use
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Rev.0.1 Sept. 2001
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