Sagem HILONC APPLICATION NOTE User Manual

Download

HILONC V2 APPLICATION NOTE

~ Freedom of speech

for smart machines ~

This page is intentionally left blank

FICHE RECAPITULATIVE / REVISION HISTORY

Ed Date

Date

1 03/09/2010 URD1 OTL 5665.3 003 72238 ed 01 all Document creation 2 02/24/2011 URD1 OTL 5665.3 003 72238 ed 02 17, 21, 24, 25,

Référence Reference

Pages modifiées / Changed pages

34, 37, 41

Observations

Comments

Surge and transient on Vbat and protection example and POK_IN relative waveforms and warnings

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 3/66

SOMMAIRE / CONTENTS

1. OVERVIEW...................................................................................................................................................................8

1.1 OBJECT OF THE DOCUMENT......................................................................................................................... 8

1.2 REFERENCE DOCUMENTS .............................................................................................................................8

1.3 MODIFICATION OF THIS DOCUMENT .......................................................................................................... 8

1.4 CONVENTIONS ...................................................................................................................................................8

2. BLOCK DIAGRAM....................................................................................................................................................... 9

3. HILONC FAMILY LEGACY......................................................................................................................................10

3.1 PADS OUT AND NEW FEATURES................................................................................................................10

3.2 EASY MIGRATION FROM HILONC (V1) TO HILONC V2..........................................................................11

3.2.1 Migration without the use of new features ..............................................................................................11

3.2.2 Migration with the use of new features ...................................................................................................11

4. FUNCTIONAL INTEGRATION.................................................................................................................................11

4.1 HOW TO CONNECT TO A SIM CARD .......................................................................................................... 12

4.2 HOW TO CONNECT THE AUDIOS? .............................................................................................................14

4.2.1 Connecting microphone and speaker .....................................................................................................14

4.2.2 Recommended characteristics for the microphone and speaker........................................................16

4.2.3 DTMF OVER GSM NETWORK ...............................................................................................................17

4.3 PWM ....................................................................................................................................................................17

4.3.1 PWM outputs ..............................................................................................................................................17

4.3.2 PWM for Buzzer connection .....................................................................................................................17

4.4 NETWORK LED .................................................................................................................................................18

4.5 POWER SUPPLY ..............................................................................................................................................18

4.5.1 Burst conditions.......................................................................................................................................... 19

4.5.2 Ripples and drops ......................................................................................................................................19

4.6 EXAMPLE OF POWER SUPPLIES ................................................................................................................ 20

4.6.1 DC/DC Power supply from a USB or PCMCIA port..............................................................................20

4.6.2 Simple high current low dropout voltage regulator................................................................................ 20

4.6.3 Simple 4V boost converter. ......................................................................................................................21

4.7 UART ................................................................................................................................................................... 21

4.7.1 Signals reminder ........................................................................................................................................21

4.7.2 Complete V24 – connection HiLoNC V2 - host .....................................................................................22

4.7.3 Complete V24 interface with PC .............................................................................................................. 23

4.7.4 Partial V24 (RX-TX-RTS-CTS) – connection HiLoNC V2 - host .........................................................24

4.7.5 Partial V24 (RX-TX) – connection HiLoNC V2 - host ...........................................................................25

4.8 UART0 .................................................................................................................................................................27

4.9 GPIO ....................................................................................................................................................................27

4.10 ADC.................................................................................................................................................................. 27

4.11 PCM .................................................................................................................................................................27

4.12 RF BURST INDICATOR ............................................................................................................................... 28

4.13 BACKUP BATTERY ......................................................................................................................................28

4.13.1 Backup battery function feature ...............................................................................................................28

4.13.2 Current consumption on the backup battery .......................................................................................... 29

4.13.3 Charge by internal HiLoNC V2 charging function .................................................................................29

4.13.4 Backup Battery technology .......................................................................................................................30

4.14 START THE MODULE PROPERLY AND AVOID POWER UP ISSUES. ............................................. 31

4.14.1 Power domains...........................................................................................................................................31

4.14.2 IO DC PRESENCE BEFORE POWER ON. ..........................................................................................32

4.14.3 SIDE EFFECTS OF A RETRO SUPPLY (CURRENT RE-INJECTION) ...........................................32

4.14.4 EXAMPLE OF A CURRENT RE-INJECTION ON U.A.R.T. ................................................................ 33

4.14.5 ADVICES FOR EVERY POWER DOMAIN............................................................................................34

4.14.6 CASE OF VBAT RISE TIME ....................................................................................................................35

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 4/66

4.14.7 START- UP ................................................................................................................................................. 35

4.15 UART SIGNALS AT POWER ON................................................................................................................36

4.16 POWER ON AND SLEEP DIAGRAMS ......................................................................................................38

4.17 MODULE RESET...........................................................................................................................................40

4.18 MODULE SWITCH OFF ............................................................................................................................... 40

4.19 SLEEP MODE MANAGEMENT AND POWER CONSUMPTION .......................................................... 41

5. RECOMMENDED I/OS AND COMPONENTS ON THE FINAL PRODUCT .........................................................43

6. ESD & EMC RECOMMENDATIONS .......................................................................................................................43

6.1 HILONC V2 ALONE........................................................................................................................................... 43

6.2 HANDLING THE MODULE ..............................................................................................................................43

6.3 Customer’s product with HiLONC V2..............................................................................................................43

6.4 Analysis ............................................................................................................................................................... 43

6.5 Recommendations to avoid ESD issues ........................................................................................................44

7. RADIO INTEGRATION..............................................................................................................................................44

7.1 ANTENNA ...........................................................................................................................................................44

7.2 GROUND LINK AREA....................................................................................................................................... 45

7.3 LAYOUT ..............................................................................................................................................................46

7.4 MECHANICAL SURROUNDING .....................................................................................................................47

7.5 OTHER RECOMMENDATIONS – TESTS FOR PRODUCTION/DESIGN ............................................... 47

8. AUDIO INTEGRATION .............................................................................................................................................47

8.1 MECHANICAL INTEGRATION AND ACOUSTICS ......................................................................................47

8.2 ELECTRONICS AND LAYOUT .......................................................................................................................48

9. RECOMMENDATIONS ON LAYOUT OF CUSTOMER’S BOARD ......................................................................48

9.1 GENERAL RECOMMENDATIONS ON LAYOUT......................................................................................... 48

9.1.1 Ground.........................................................................................................................................................48

9.1.2 Power supplies ........................................................................................................................................... 48

9.1.3 Clocks ..........................................................................................................................................................49

9.1.4 Data bus and other signals .......................................................................................................................49

9.1.5 Radio............................................................................................................................................................ 49

9.1.6 Audio............................................................................................................................................................49

9.2 EXAMPLE OF LAYOUT FOR CUSTOMER’S BOARD................................................................................50

10. RECOMMANDATIONS FOR CUSTOMER PRODUCTION ............................................................................... 50

10.1 MOISTURE LEVEL........................................................................................................................................50

10.2 PACKAGE.......................................................................................................................................................50

10.3 STENCIL .........................................................................................................................................................52

10.4 SOLDER PASTE............................................................................................................................................52

10.5 PROFILE FOR REFLOW SOLDERING .....................................................................................................53

10.6 SMT MACHINE ..............................................................................................................................................53

10.6.1 Nozzles ........................................................................................................................................................54

10.6.2 Fiducials ......................................................................................................................................................55

10.7 UNDERFILL ....................................................................................................................................................55

10.8 SECOND REFLOW SOLDERING............................................................................................................... 56

10.9 HAND SOLDERING ......................................................................................................................................56

10.10 UNSOLDERING .............................................................................................................................................56

11. LABEL .....................................................................................................................................................................57

12. REFERENCE DESIGN: HiLoNC V2 DEVELOPMENT KIT ................................................................................58

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 5/66

FIGURES LIST

Figure 1: Block diagram of HiLoNC module ........................................................................................................................... 9

Figure 2: Postage stamp sized HiLoNC V2 51 pads out front side ........................................................................................12

Figure 3: Postage stamp sized HiLoNC V2 51 pads out back side......................................................................................... 12

Figure 4: SIM Card signals..................................................................................................................................................... 12

Figure 5: Protections: EMC and ESD components close to the SIM .....................................................................................13

Figure 6: Protections: Serial resistors for long SIM bus lines. ...............................................................................................14

Figure 7: Audio connection .................................................................................................................................................... 14

Figure 8 : Filter and ESD protection of microphone ..............................................................................................................15

Figure 9: Filter and ESD protection of 32 ohms speaker........................................................................................................15

Figure 10: Example of D class TPA2010D1 1Watt audio amplifier connections. ................................................................. 16

Figure 11: Buzzer connection .................................................................................................................................................17

Figure 12: Network LED connection ..................................................................................................................................... 18

Figure 13: Over voltage protection on VBatt ......................................................................................................................... 18

Figure 14: GSM/GPRS Burst Current rush ............................................................................................................................ 19

Figure 15: GSM/GPRS Burst Current rush and VBAT drops and ripples ...............................................................................19

Figure 16: Example of power supply based on a DC/DC step down converter......................................................................20

Figure 17: Example of power supply based on regulator MIC29302WU ..............................................................................20

Figure 18: Example with Linear LT1913 ............................................................................................................................... 21

Figure 19: Complete V24 connection between HiLoNC V2 and host....................................................................................22

Figure 20: CTS versus POK_IN signal during the power on sequence. .................................................................................23

Figure 21: connection to a data cable .....................................................................................................................................23

Figure 22: Example of a connection to a data cable with a MAX3238E................................................................................ 24

Figure 23: Partial V24 connection (4 wires) between HiLoNC V2 and host ......................................................................... 24

Figure 24: CTS versus POK_IN signal during the power on sequence. .................................................................................25

Figure 25: Partial V24 connection (2 wires) between HiloNC V2 and host........................................................................... 26

Figure 26: CTS versus POK_IN signal during the power on sequence. .................................................................................26

Figure 27: PCM interface timing ............................................................................................................................................28

Figure 28: RF_TX burst indicator ..........................................................................................................................................28

Figure 29: Backup battery or 10µ F Capacitor internally charged ..........................................................................................29

Figure 30: Charging curve of backup battery ......................................................................................................................... 30

Figure 31 : HiLoNC V2 51 pads with their power domains ...................................................................................................31

Figure 32 : HiLoNC V2 51 pads with their power domains…continued ...............................................................................32

Figure 33: Digital Pad-out clamp diode..................................................................................................................................33

Figure 34: Hardware interface diodes solution between HiLoNC V2 and host......................................................................34

Figure 35: Hardware interface buffers solution between HiLoNC V2 and host.....................................................................34

Figure 36: Power ON sequence ..............................................................................................................................................36

Figure 37: Full UART signals during the power on sequence................................................................................................37

Figure 38: Diagram for the power on ..................................................................................................................................... 38

Figure 39: Diagram for the sleep mode ..................................................................................................................................39

Figure 40: Reset command of the HiLoNC V2 by an external GPIO ....................................................................................40

Figure 41: Power supply command by a GPIO ......................................................................................................................40

Figure 42: Power OFF sequence for POK_IN, VGPIO and CTS...........................................................................................41

Figure 43: Power consumption at DRX9 (with RS-NGMO2 power supply) ......................................................................... 42

Figure 44: Antenna connection...............................................................................................................................................44

Figure 45: Antenna detection circuit ......................................................................................................................................45

Figure 46: Mandatory area for varnish ...................................................................................................................................46

Figure 47: Connection of RF lines with different width.........................................................................................................46

Figure 48: Layout of audio differential signals on a layer n ...................................................................................................49

Figure 49: Adjacent layers of audio differential signals .........................................................................................................49

Figure 50: layer allocation for a 6 layers circuit ..................................................................................................................... 50

Figure 51: Factory Tape dimensions ......................................................................................................................................51

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 6/66

Figure 52 : Solder mask design .............................................................................................................................................. 52

Figure 53 : Typical thermal profile.........................................................................................................................................53

Figure 54 : Flexjet nozzle 340F ..............................................................................................................................................54

Figure 55 : Siemens nozzle 417.............................................................................................................................................. 54

Figure 56 : Fiducials positions................................................................................................................................................55

Figure 57 : Underfill injection holes.......................................................................................................................................56

Figure 58 : Laboratory hot plate to unsolder the module........................................................................................................57

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 7/66

1. OVERVIEW

1.1 OBJECT OF THE DOCUMENT

The aim of this document is to describe some examples of hardware solutions for developing products around the SAGEMCOM HiLoNC V2 GPRS Module. Most parts of these solutions are not mandatory. Use them as suggestions of what should be done to have a working product and what should be avoided thanks to our experiences. This document suggests how to integrate the HiLoNC V2 GPRS module in machine devices such as automotive, AMM (Automatic Metering Management), tracking system: connection with external devices, layout advises, external components (decoupling capacitors…).

1.2 REFERENCE DOCUMENTS

URD1 OTL 5665.3 001 71927 - HiLoNC V2 technical specification URD1 OTL 5635.1 008 70248 - AT Command Set for SAGEM HiLo Modules

1.3 MODIFICATION OF THIS DOCUMENT

The information presented in this document is supposed to be accurate and reliable. SAGEMCOM assumes no responsibility for its use, nor any infringement of patents or other rights of third parties which may result from its use.

This document is subject to change without notice. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.

1.4 CONVENTIONS

SIGNAL NAME: All signal names available on the pads of the HiLoNC V2 module is written in italic.

Specific attention must be granted to the information given here.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 8/66

2. BLOCK DIAGRAM

Figure 1: Block diagram of HiLoNC module

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 9/66

3. HILONC FAMILY LEGACY

3.1 PADS OUT AND NEW FEATURES

HiLoNC Pads

E1 E2

E3 E4 E5 E6 E7 E8

E9 E10 E11 E12 E13

E14 E15 E16 E17

E18 E19 E20

E21 E22 E23 E24

E25

E26 E27 E28 E29 E30 E31

E32

E33 E34 E35 E36 E37 E38 E39 E40 E41 E42 E43

HiLoNC V2

Signal Name

/INTMIC_P AUDIO

/AUX_ADC0 ADC

GND POWER

VGPIO EXT_VDD

VBACKUP EXT_VDD

/PWM0 PWM

/RESET_IN RESET SAGEMCOM FACTORY USE SAGEMCOM FACTORY USE SAGEMCOM FACTORY USE

NTRST JTAG/FACTORY SAGEMCOM FACTORY USE SAGEMCOM FACTORY USE

/GPIO2 GPIO

/GPIO1 GPIO

/RF_TX RF

/PCM_CLK PCM

/PCM_SYNC PCM

/PCM_OUT PCM

/PCM_IN PCM

GND POWER

/ JTAG1 JTAG

/JTAG2 JTAG

/TEST JTAG

/UART0_RXD Trace UART 0

/GPIO3 GPIO

GND RF

/ANTENNA RF

GND RF VBATT POWER VBATT POWER

/UART0_TXD Trace UART 0 /UART1_DSR UART 1 /UART1_DCD UART 1

/UART1_RI UART 1 /UART1_DTR UART 1 /UART1_RTS UART 1

/UART1_RX UART 1

/UART1_TX UART 1

/UART1_CTS UART 1

/POK_IN POWER ON

/PWM2 PWM /PWM1 PWM

HiLoNC V2

Function

HiLoNC V1

Signal Name

/INTMIC_P AUDIO P2P Compliant

/AUX_ADC0 ADC P2P Compliant

GND POWER P2P Compliant

VGPIO EXT_VDD P2P Compliant

VBACKUP EXT_VDD P2P Compliant

/PWM0 PWM P2P Compliant

/RESET_IN RESET P2P Compliant SAGEMCOM FACTORY P2P Compliant SAGEMCOM FACTORY P2P Compliant SAGEMCOM FACTORY P2P Compliant /JTAG_TRST JTAG P2P Compliant SAGEMCOM FACTORY P2P Compliant

SAGEMCOM FACTORY P2P Compliant

/GPIO2 GPIO P2P Compliant

/GPIO1 GPIO P2P Compliant

/GPIO8_SPI_IN SPI

/SCL_SPI_OUT SPI

/SDA_SPI_SEL SPI

/GPIO6_SPI_IRQ SPI

/GPIO7_SPI_CLK SPI

GND POWER P2P Compliant /TEST_GPIO1 GPIO P2P Compliant /TEST_GPIO2 GPIO P2P Compliant

/TEST JTAG P2P Compliant

/GPIO4 GPIO

/GPIO3 GPIO P2P Compliant

GND RF P2P Compliant

/ANTENNA RF P2P Compliant

GND RF P2P Compliant

VBATT POWER P2P Compliant

/GPIO5 GPIO

/UART1_DSR UART P2P Compliant

/UART1_DCD UART P2P Compliant

/UART1_RI UART P2P Compliant

/UART1_DTR UART P2P Compliant

/UART1_RTS UART P2P Compliant

/UART1_RX UART P2P Compliant

/UART1_TX UART P2P Compliant

/UART1_CTS UART P2P Compliant

/POK_IN POWER ON P2P Compliant

/PWM2 PWM P2P Compliant

/PWM1 PWM P2P Compliant

HiLoNC V1

Function

Delta

New Feature New Feature New Feature New Feature New Feature

New Feature

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 10/66

E44 E45 E46 E47 E48 E49 E50 E51

As seen in the table above, the two modules are almost pad to pad (P2P) compliant for the main important signals, however the new HiLoNC V2 M2M module introduce some new interesting features as the digital audio on the PCM bus and the RF bust indicator signal.

/SIM_CLK SIM /SIM_RST SIM

/SIM_DATA SIM

VSIM SIM

VBATT POWER

GND POWER /HSET_OUT_P AUDIO /HSET_OUT_N AUDIO

/SIM_CLK SIM P2P Compliant

/SIM_RST SIM P2P Compliant

/SIM_DATA SIM P2P Compliant

VSIM SIM P2P Compliant

VBATT POWER P2P Compliant

GND POWER P2P Compliant

/HSET_OUT_P AUDIO P2P Compliant

/HSET_OUT_N AUDIO P2P Compliant

3.2 EASY MIGRATION FROM HILONC (V1) TO HILONC V2

3.2.1 Migration without the use of new features

When upgrading from the HiLoNC V1 to the HiLoNC V2, the SPI bus formerly used was supposed to be left as test points on your design, then simply left the design as it is, therefore the new PCM bus and RF burst indicator signals will remain not used. For the former GPIO4 and GPIO5, if there were both not used, simply add if possible two test points on those signals to be able to connect a trace cable in case of need. Otherwise, if one or both former GPIO4 and GPIO5 were used, you have to reallocate those pads to GPIO1, GPIO2 or GPIO3 which remain pad to pad compliant.

3.2.2 Migration with the use of new features

When upgrading from the HiLoNC V1 to the HiLoNC V2, the former SPI bus which was supposed to be left on test points is now used as the digital audio PCM bus and also the RF indicator signal, simply connect the new signals as described below in the respective chapter. The former GPIO4 and GPIO5 signals are now used to connect the UART TXD / RXD trace bus, then add if possible two test points on those signals to be able to connect a trace cable in case of need.

4. FUNCTIONAL INTEGRATION

The improvement of Silicon technologies heads toward functionality improvement, less power consumption. The postage stamp sized HiLoNC V2 module meets all these requirement, uses the last high end technology in a very compact design of only 24 x 24 x 2.6 mm and weighs less than 3 grams.

All digital I/Os among the 51 pads are in 2.8V domain which is suitable for most systems except SIM I/O's



with can also be in the 1.8V domain depending on the used SIM card and POK_IN at 3Vdomain

Analogical I/Os are in the following power domains



• VSIM  (the SIM I/Os at 1.8V or 2.9V domain).

• VBACKUP 3V domain

• VGPIO 2.8V domain

• VBAT  (from 3.2V to 4.5V domain)

• AUX_ADC0 2.8V domain

• INTMIC_P 2.85V domain

• HSET_OUT_P/N VBAT domain

• ANTENNA (RF power Amplifier is on VBAT domain)

Do not power the module I/O with a voltage over the specified limits, this could damage the module.



Acoustic engineering competences are mandatory to get accurate audio performance on customer’s



product

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 11/66

51 14

Radio engineering competences are mandatory to get accurate radio performance on customer’s product.



Figure 2: Postage stamp sized HiLoNC V2 51 pads out front side

Figure 3: Postage stamp sized HiLoNC V2 51 pads out back side

4.1 HOW TO CONNECT TO A SIM CARD

Figure 4: SIM Card signals

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 12/66

HiLoNC V2 module provides the SIM signals on the 51 pads. A SIM card holder with 6 pads needs to be adopted to use the SIM function.

Decoupling capacitors have to be added on SIM_CLK, SIM_RST, VSIM and SIM_DATA signals as close



as possible to the SIM card connector to avoid EMC issues and pass the SIM card tests approvals .

Use ESD protection components to protect SIM card and module I/Os against Electro Static Discharges.



The following schematic shows how to protect the SIM access for 6 pads connector, this should be apply every time a SIM card holder is accessible by the final customer.

Figure 5: Protections: EMC and ESD components close to the SIM

 In case of long SIM bus lines over 10cm, it is recommended to also use serial resistors to avoid electrical

overshoots on SIM bus signals. Use 56Ω for the clock line and 10Ω for the reset and data lines.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 13/66

Figure 6: Protections: Serial resistors for long SIM bus lines.

The schematic here above includes the hardware SIM card presence detector. It can be connected to any GPIO and managed with an AT command.

 SIM card must not be removed from its holder while it is still powered. First switch the module off properly

with the AT command, then remove the SIM card from its holder.

4.2 HOW TO CONNECT THE AUDIOS?

The HiLoNC V2 module features one input audio path and one output audio path. The input path is single-end while the output path is differential. In this following chapter examples of design will be given including protections against EMC and ESD and some notes about the routing rules to follow to avoid the TDMA noise sometimes present in this sensitive area of design.



customer’s product.

4.2.1 Connecting microphone and speaker

The HiLoNC V2 module can manage an external microphone (INTMIC_P) in single-end mode and an external speaker (HSET_OUT_P / HSET_OUT_N) in differential mode. Thus, one speaker and one microphone can be connected to the module. The 2.4V voltage to bias the microphone is implemented in the module.

Note that acoustic engineering competences are mandatory to get accurate audio performance on

The speaker connected to the module should be 32 ohms.



HiLoNC V2

If the design is ESD or EMC sensitive we strongly recommend reading the notes below. A poor audio quality could either come from the PCB routing and placement or from the chosen components (or even both).

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HSET_OUT_P

HSET_OUT_N

INTMIC_P

Filter and

ESD

protection

Figure 7: Audio connection

32ohms speaker

MIC

HiLoNC V2 Application Note

11 March 2011 - page 14/66

4.2.1.1 Notes for microphone

Pay attention to the microphone device, it must not be sensitive to RF disturbances.



If you need to have deported microphone out of the board with long wires, you should pay attention to the



EMC and ESD effect. It is also the case when your design is ESD sensitive. In those cases, add the following protections to improve your design.



voltage to be re-injected inside the module.

4.2.1.2 Notes for speaker

To ensure proper operation of such sensitive signals, they have to be isolated from the others by

analogue ground on customer’s board layout. (Refer to Layout design chapter)

HiLoNC V2

To use an external bias voltage for the microphone, simply use a capacitor of 10µF to prevent this bias

As explained for the microphone, if the speaker is deported out of the board or is sensitive to ESD, use the schematic here after to improve the audio.

INTMIC_P

Figure 8 : Filter and ESD protection of microphone

Ferrite Bead

MIC

18pF

ESD protection

18pF

HiLoNC V2

HSET_OUT_P, HSET_OUT_N tracks must be larger than other tracks: 0.1 mm.



As described in the layout chapter, differential signals have to be routed in parallel (HSET_OUT_P and



HSET_OUT_N signals)

The impedance of audio chain (filter + speaker) must be lower than 32Ω.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HSET_OUT_P

HSET_OUT_N

Figure 9: Filter and ESD protection of 32 ohms speaker

Ferrite Bead

18pF

ESD protection

speaker

ESD protection

HiLoNC V2 Application Note

11 March 2011 - page 15/66

To use an external audio amplifier connected to a loud-speaker, use serial capacitors of 10nF on HiLoNC



audio outputs to connect the audio amplifier.

Figure 10: Example of D class TPA2010D1 1Watt audio amplifier connections.

4.2.2 Recommended characteristics for the microphone and speaker

4.2.2.1 Recommended characteristics for the microphone

Item to be inspected Acceptance criterion

Sensitivity - 40 dB SPL +/-3 dB (0 dB = 1 V/Pa @ 1kHz)

Frequency response Limits (relatives values)

Freq. (Hz) Lower limit Upper limit 100 -1 1 200 -1 1 300 -1 1 1000 0 0 2000 -1 1 3000 -1.5 1.5 3400 -2 2 4000 -2 2

Current consumption 1 mA (maximum) Operating voltage DC 1 to 3 V (minimum) S / N ratio 55 dB minimum (A-Curve at 1 kHz, 1 Pa) Directivity Omni-directional Maximum input sound pressure level 100 dB SPL (1 kHz)

Maximum distortion 1%

Radio frequency protection Over 800 -1200 MHz and 1700 -2000 MHz, S/N ratio 50

dB minimum (signal 1 kHz, 1 Pa)

4.2.2.2 Recommended characteristics for the speaker

Item to be inspected Acceptance criterion

Input power: rated / max 0.1W (Rate)

Audio chain impedance 32 ohm +/- 10% at 1V 1KHz

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 16/66

Frequency Range

300 Hz ~ 4.0 KHz

Sensitivity (S.P.L) >105 dB at 1KHz with IEC318 coupler,

Distortion 5% max at 1K Hz, nominal input power

4.2.3 DTMF OVER GSM NETWORK

Former systems used to transmits data through DTMF modulation on RTC telephone lines.

Audio DTMF tones are not guarantee over GSM network



This is due to the nature of the GSM Voice CODEC - it is specifically designed for the human voice and does not faithfully transmit DTMF. When you press the buttons on your GSM handset during a call, this goes in the Signalling channel - it does not generate in-band DTMF; the actual DTMF tones are generated in the network.

Therefore if your design needs the DTMF functionality, you should know their transmission over the network is not at all guaranteed (because of voice codec). This could work or fail depending very strongly to the GSM network provider. SAGEMCOM does not guarantee any success on using this function.

However tests on HiLoNC V2 shown this feature can work on some GSM Networks. Successful transmissions and receptions have been done with 300ms of characters duration and 200mVpp as input level on microphone input.

If this function is needed, first try with your network and those parameters then (if success) try to tune



them to fit your specification.

4.3 PWM

4.3.1 PWM outputs

The HiLoNC V2 module can manage two PWM outputs. They can be configured with appropriate AT command (for more details refer to AT command set for SAGEMCOM HiLoNC V2 module specification).

User application can set for each output:

• Frequency between : 25.6KHz and 1083.3KHz

• Duty range from: 0 to 100%

4.3.2 PWM for Buzzer connection

The HiLoNC V2 module can manage a dedicate PWM output to drive a buzzer. The buzzer can be used to alarm for abnormal state.

Resistors should be added to protect the buzzer. The value of these resistors depends on the buzzer and



the transistor. Normally, they can be set as 1KΩ.

VBAT

HiloNC

PWM2

Figure 11: Buzzer connection

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 17/66

GPIO or

4.4 NETWORK LED

The HiLoNC V2 module can manage a network LED. The LED can be connected either to one of the available GPIO or to a PWM (but not the one dedicated to the buzzer). The transistors can be found a in a single package referenced as UMDXX or PUMDXX Family. Value of resistor R depends on characteristic of chosen LED; it is used to limit the current through the diode. Use the AT command to set the GPIO or PWM used to control the LED.

PWM

HiLoNC V2

VBAT

Figure 12: Network LED connection

4.5 POWER SUPPLY

The HiLoNC V2 module can be supplied by a battery or any DC/DC converter compliant with the module supply range 3.2V to 4.5V and 2.2 A.

Warning: The HiLoNC V2 module is not supposed to be supplied w ith a voltage over 4.5V even in transient. However the module can resist to over voltage transient lower than 6.8V. If the system main board pow er supply unit i or over in case of transient voltage presence on the circuit, the HiLoNC V2 module power amplifier may be severely damaged.

To avoid such issue, simply add a voltage limiter to the module power supply lines so the VBATT signal Pads may never receive a surge voltage over 6.8V. The limiter can be as simple as a Zener diode as shown here under or in the annex development kit schematic of this document.

s not stable or if the system main board is supplied w ith 9V

Figure 13: Over voltage protection on VBatt

The PCB tracks must be well dimensioned to support 2.2 A maximum current (Burst current 1.8A plus the



extra current for the other used I/Os). The voltage ripple caused by serial resistance of power supply path (Battery internal resistance, tracks and contact resistance) could result in the voltage drops.

To prevent any issue in the power up procedure the typical rise time for VBAT should be 1ms.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 18/66

The HiLoNC V2 module does not manage the battery charging.



4.5.1 Burst conditions

- Communication mode (worst case: 2 continuous GSM time-slot pulse):

Figure 14: GSM/GPRS Burst Current rush

A 47µF with Low ESR capacitor is highly recommended for VBAT and close to the module pads 30 & 31.



4.5.2 Ripples and drops

Current burst at 1.8A 33dBm

GSM TX Lev 5

Ripple

VBAT drop

3.2V Min

Figure 15: GSM/GPRS Burst Current rush and VBAT drops and ripples

The minimum voltage during the drop of VBAT must be 3.2V at 33dBm at pads 30 and 31 for the full



range of the required functioning temperature. To reach this aim, adapt the VBAT tracks width to minimize the loss: the shorter and thicker is the track; the lower is the serial impedance.

To check the serial resistor, any CAD software can be used or by experiment by measuring it on the PCB by injecting 1A into the VBAT track on connector side and shorting to GND the other side, this could be done using a laboratory power supply set to few volts with a limitation in current to 1A. Then the measure of the drop voltage leads to the serial resistor.

Noise on VBAT due to drops could result in poor audio quality.



Serial resistor should be less than 250mΩ including the impedance of connectors if any.



Ripple has to be minimised to have a clean RF signal. This can be improved by filtering the output of the



power supply when AC/DC or DC/DC components are used. Refer to the power converter chip supplier application note for more information and advises.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 19/66

To have 3.7V out R1=560K & R2=271.8K

(270K+1.8K)

4.6 EXAMPLE OF POWER SUPPLIES

4.6.1 DC/DC Power supply from a USB or PCMCIA port.

It the following application note from Linear Technology LTC3440, this schematic is an example of a DC/DC power supply able to power 3.6V under 2A. This can be use with a AC/DC 5V unit or an USB or PCMCIA bus as input power source. C6 to C9 can be followed by a serial MOS transistor to avoid a slow rise signal at VOUT.

Figure 16: Example of power supply based on a DC/DC step down converter

4.6.2 Simple high current low dropout voltage regulator.

If the whole power consumption is not an issue, this example of a simple voltage regulator preceded by an AC/DC to 5V converter, can be use to power the module.

The voltage output is given by: VOUT = 1.235V × [1 + (R1 / R2)]

Figure 17: Example of power supply based on regulator MIC29302WU

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 20/66

4.6.3 Simple 4V boost converter.

Simple boost converter with Linear LT1913 (see LT1316 evaluation kit document). The input can be preceded by an AC/DC converter to get the 5V. PGOOD signal can be checked before the ignition of the module.

Figure 18: Example with Linear LT1913

4.7 UART

The HiLoNC V2 module features a V24 interface to communicate with the host through AT commands or for easy firmware upgrading purpose.

It is recommended to manage an external access to the V24 interface, in order to allow easy software



upgrade (baud rate up to 460.8kbps, validated with ATEN USB/Serial converter).

DTR, DSR, DCD and RI signals are internally pull upped to VGPIO with a 100KΩ.



RI signal is a stand alone signal that can be used with anyone of the following configurations. Consult the



AT command specification for more information about this signal and its use.

4.7.1 Signals reminder

The following table quickly sums up the use of the different signals from UART

Signal name Signal use(DTE point of view)

TX DCD DSR DTR

RTS CTS

Receive data Transmit data Signal data connections in progress (GPRS or CSD) Signal UART interface is ON Prevent the HiLoNC V2 to enter into sleep mode Switch between data and command modes Wake up the module,… Wakes up the module when Ksleep=1 is used Signal HiLoNC V2 is ready to receive AT commands, has waken up Signal incoming calls (voice and data), SMS,…

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 21/66

Consult the AT command Specification document for the use of the UART signals.



Unused signals can be left not connected.



4.7.2 Complete V24 – connection HiLoNC V2 - host

A V24 interface is provided on the 51 pads of the HiLoNC V2 module with the following signals: RTS/CTS, RXD/TXD, DSR, DTR, DCD, RI.

The use of this complete V24 connection is recommended as soon as your application needs to exchange



data (over GPRS or CSD).

HiLoNC V2 Module

39 40 33 34 35

36 38 37

TXD

CTS DSR

DCD

DTR RXD

RTS

RXD

CTS DSR

DCD

DTR TXD

RTS

DTE Device

2.8V signals

Note: GND is not represented

DCE point of view

Figure 19: Complete V24 connection between HiLoNC V2 and host

This configuration allows to use the flow control RTS & CTS to avoid any overflow error during the data transfer, CTS is moreover used to signal when the HiLoNC V2 is ready to receive an AT command after a power up sequence or a wake up from sleep mode. This configuration allows as well all the signalling signals like:

• RI signal used when programmed to indicate an incoming voice or data call or SMS incoming etc…

• DCD signal used to signal the GPRS connections

• DSR signal used to signal the module UART interface is ON

• DTR signal used to prevent the HiLoNC V2 module from entering into sleep mode or to switch between

Data and AT commands or to hang up a call or to wake up the module etc…

DTE point of view

2.8V signals

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 22/66

6 9



sequence.

Avoid supplying the UART before the HiLoNC V2 module is ON, this could result in bad power up

Figure 20: CTS versus POK_IN signal during the power on sequence.

4.7.3 Complete V24 interface with PC

It supports speeds up to 115.2 Kbps and may be used in auto bauding mode. To use the V24 interface, some adaptation components are necessary to convert the +2.8V signals from the HiLoNC V2 to +/- 5V signals compatible with a PC.

HiLoNC V2 Module

2.8V signals

TXD

CTS

DSR

DCD

DTR

RXD

RTS

DCE point of view

RS232 Transceiver

IN IN IN IN IN OUT OUT OUT

3.1V to +/-5.5V

Figure 21: connection to a data cable

OUT OUT OUT OUT OUT

IN IN IN

signals

RXD

CTS

DSR

DCD

DTR TXD

RTS

DTE point of view

2 8 6 1 9

4 3 7

SUBD9 Female Note: pin 5 is GND



sequence. To have a proper behaviour use the signal VGPIO to enable the RS232 Transceiver.

To create your own data cable (for software download purpose…etc…) refer to the following schematic as an example with a MAX3238E:

Avoid supplying the UART before the HiLoNC V2 module is ON, this could result in bad power up

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 23/66

• VCC_3V1 is an LDO output (VBAT to VCC_3V1) enabled by VGPIO from the module.

• 180Ω are serial resistors aimed to limit the EMC and ESD propagation.

Figure 22: Example of a connection to a data cable with a MAX3238E

4.7.4 Partial V24 (RX-TX-RTS-CTS) – connection HiLoNC V2 - host

When using only RX/TX/RTS/CTS instead of the complete V24 link, the following schematic could be used.

HiLoNC V2 Module

TXD

CTS

DSR

DCD

DTR

RXD

RTS

2.8V signals

DCE point of view

Figure 23: Partial V24 connection (4 wires) between HiLoNC V2 and host

Note: GND is not represented

RXD

CTS

DSR

DCD

DTR TXD

RTS

DTE point of view

DTE Device

2.8V signals



electrical level), therefore AT command AT+Ksleep can switch between the two sleeps mode available for the HiLoNC V2.

As DSR is active (low electrical level) once the HiLoNC V2 is switched on, DTR is also active (low

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 24/66

DTR input signal is internally pull upped to VGPIO with a 100KΩ, this result in 28µA of extra consumption.



DCD and RI can stay not connected and floating when not used.



RI signal is a stand alone signal that can be used with anyone of the following configuration. Consult the



AT command specification for more information about this signal and its use.

Figure 24: CTS versus POK_IN signal during the power on sequence.

However this configuration does not allow the signalling signals like:



• RI signal used when programmed to indicate an incoming voice or data call or SMS incoming etc…

• DCD signal used to signal the GPRS connections

• DSR signal used to signal the module UART interface is ON

• DTR signal used to prevent the HiLoNC V2 module from entering into sleep mode or to switch between

Data and AT commands or to hang up a call or to wake up the module etc…

Consult the AT command Specification document for the uses of the UART signals.



4.7.5 Partial V24 (RX-TX) – connection HiLoNC V2 - host

When using only RX/TX instead of the complete V24 link, the following schematic could be used.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 25/66

HiLoNC V2 Module

39 40 33 34 35

36 38 37

TXD

CTS DSR

DCD

DTR RXD

RTS

RXD

CTS

DSR

DCD

DTR TXD

RTS

DTE Device

2.8V signals

DCE point of view DTE point of view

Figure 25: Partial V24 connection (2 wires) between HiloNC V2 and host



electrical level), therefore AT command AT+Ksleep can switch between the two sleep modes available for the HiLoNC V2.

 

electrical level), therefore AT command AT+Ksleep can switch between the two sleep modes available for the HiLoNC V2. The HiLoNC V2's firmware allows the rise of CTS during the sleep state even when looped to RTS signal.

 

AT command specification for more information about this signal and its use.

This configuration does not allow to use the flow control RTS & CTS. Those signals are used to avoid any overflow error during the data transfer, CTS is moreover used to signal when the HiLoNC V2 is ready to receive an AT command after a power up sequence or a wake up from sleep mode.

As DSR is active (low electrical level) once the HiLoNC V2 is switched on, DTR is also active (low

DTR input signal is internally pull upped to VGPIO with a 100KΩ, this result in 28µA of extra consumption.

As CTS is active (low electrical level) once the HiLoNC V2 is switched on, RTS is also active (low

DCD and RI can stay not connected and floating when not used.

RI signal is a stand alone signal that can be used with anyone of the following configuration. Consult the

Note: GND is not represented

2.8V signals

Figure 26: CTS versus POK_IN signal during the power on sequence.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 26/66

Moreover this configuration does not allow the signalling signals like:



• RI signal used when programmed to indicate an incoming voice or data call or SMS incoming etc…

• DCD signal used to signal the GPRS connections

• DSR signal used to signal the module UART interface is ON

• DTR signal used to prevent the HiLoNC V2 module from entering into sleep mode or to switch between

Data and AT commands or to hang up a call or to wake up the module etc…

Consult the AT command Specification document for the uses of the UART signals.



4.8 UART0

HiLoNC V2 module manages a 2-wire UART interface. This UART interface is only dedicated for software traces.

SAGEMCOM strongly recommends leaving this interface externally accessible for trace (e.g. access by



test point pads).

4.9 GPIO

There are Three GPIOs available on HiloNC V2. All GPIOs have internal pull-up resistors. GPIOs can directly be controlled with dedicated AT commands. Thanks to some other special AT commands, GPIOs can for example be used:

• to make an I/O toggling while the module is attached to the network

• to make an I/O toggling when a programmed temperature is reached

• as input to detect the presence of an antenna (with some external additional electronic)

• as input to detect the SIM card presence …etc

4.10 ADC

There is one ADC input pad which can be used to read the value of the voltage applied. Following characteristics must be met to allow proper performances:

• The input signal voltage must be within 0V and up to 3V

• The input impedance of the pad is 150KΩ

• The input capacitance is typically 10pF.

The AT command AT+KADC will give voltage value with following characteristics:

• 10 bits resolution

• Maximum sampling frequency is 200 KHz.

Consult the AT command Specification document for more information about KADC AT command.



4.11 PCM

There is a master PCM interface available on HiLoNC V2. The PCM interface can be configured by dedicate AT commands. Following characteristics must be met:

• 16 bits PCM data word length

• Configurable PCM clock rate must not exceed 1MHz

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 27/66

Figure 27: PCM interface timing

4.12 RF BURST INDICATOR

There is one digital output named RF_TX available on HiLoNC V2 to indicate the RF transmission. This output can not be controlled by AT commands and can not be used for other purpose.

This output can only connect to a transistor but not to drive a LED directly. Otherwise, the RF



transmission will be unexpected affected.

VBAT

RF_TX

HiLoNC

Figure 28: RF_TX burst indicator

4.13 BACKUP BATTERY

4.13.1 Backup battery function feature

4.13.1.1 With backup battery

A backup battery can be connected to the module in order to supply internal RTC (Real Time Clock) when the main power supply is removed. Thus, when the main power supply is removed, the RTC is still supplied and the module keeps the time register running.

With external backup battery:

• If VBAT < 3V, internal RTC is supplied by VBACKUP.

• If VBAT ≥3V, internal RTC is supplied by VBAT.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 28/66

4.13.1.2 Without backup battery

Without backup battery

• If VBAT ≥ 1.5V, internal RTC is supplied by VBAT.

• If VBAT < 1.5V, internal RTC is not supplied.

VBACKUP input of the module has to be connected to a 10µF capacitor (between VBACKUP and GND).



SAGEMCOM does not recommend to connecting VBACKUP signal to VBAT as for former SAGEMCOM



MOXX modules.

4.13.2 Current consumption on the backup battery

When the power supply is removed, the internal RTC will be supplied by backup battery.



To calculate the backup battery capacity, consider that current consumption for RTC on the backup

battery is up to 1000µA depending on the temperature.

Pad Name VBACKUP

Min Max

1000µA

4.13.3 Charge by internal HiLoNC V2 charging function

The charging function is available on the HiLoNC V2 without any additional external power supply (the charging power supply is provided by the HiLoNC V2).

Charge of the back-up battery occurs only when main power supply VBAT is provided.



The recommended schematic is given hereafter:

VBACKUP

HiLoNC V2

The resistor R depends on the charging current value provided by the battery manufacturer. The charging curve which is done by the HiLoNC V2 is given hereafter:

Backup battery

Figure 29: Backup battery or 10µF Capacitor internally charged

VBACKUP

HiLoNC V2

10µF capacitor

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 29/66

Figure 30: Charging curve of backup battery

4.13.4 Backup Battery technology

4.13.4.1 Manganese Silicon Lithium-Ion rechargeable Battery

SAGEMCOM does not recommend using this kind of technology because of the following drawbacks:

• The maximum discharge current is limited (Shall be compliant with the module characteristics).

• The over-discharge problem: most of the Lithium Ion rechargeable batteries are not able to recover their

charge when their voltage reaches a low-level voltage. To avoid this, it is necessary to add a safety component to disconnect the backup .battery in case of over–discharge condition. In such a case, this implementation is too complicated (too much components for that function).

• The charging current has to be regulated.

SAGEMCOM does not recommend using this kind of backup battery technology.



4.13.4.2 Capacitor battery

These kinds of backup battery have not the drawbacks of the Lithium Ion rechargeable battery. As there are only capacitors:

• The maximum discharge current is generally bigger,

• There is no problem of over-discharge: the capacitor is able to recover its full charge even if its voltage

has previously fallen to 0V.

• There is no need to regulate the charging current.

Moreover, this kind of battery is available in the same kind of package than the Lithium Ion cell and fully compatible on a mechanical point of view. The only disadvantage is that the capacity of this kind of battery is significantly smaller than Manganese Silicon Lithium Ion battery. But for this kind of use (supply internal RTC when the main battery is removed), the capacity is generally enough.

SAGEMCOM strongly recommends using this kind of backup battery technology.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 30/66

4.14 START THE MODULE PROPERLY AND AVOID POWER UP ISSUES.

This chapter gives advices on how to make a proper start of the HiLoNC V2 module and sums up the side effects of a non compliant power up sequence or a non compliant hardware connection between the HiLoNC V2 and the host CPU.

4.14.1 Power domains

Each HiLoNC V2 pad is linked to a specific internal power domain as the following:

• VANA is typically 2.85V and is a general purpose analogue dedicated voltage.

• VBAT is typically 3.2V to 4.5V and is the main system voltage.

• VRTC is typically 3.0V and is the real time clock dedicated voltage.

• VGPIO is typically 2.8V and is a general purpose digital dedicated voltage.

• VSIM is typically 1.8V or 2.9V and is the digital SIM card function dedicated voltage.

• VPERM is typically 3.0V and is the permanent voltage dedicated to launch the power up sequence.

The next table gives the 51 HiLoNC V2 pads with all their relative power domains.

HiLoNC

Pads

Signal Name Function Power domain

E1 /INTMIC_P AUDIO 2.85V E2 /AUX_ADC0 ADC 2.85V

E3 GND POWER 0V E4 VGPIO EXT_VDD 2.8V E5 VBACKUP EXT_VDD 3.0V E6 /PWM0 PWM 2.85V E7 /RESET_IN RESET 2.8V E8 SAGEMCOM FACTORY USE 2.8V

E9 SAGEMCOM FACTORY USE 2.8V E10 SAGEMCOM FACTORY USE 2.8V E11 NTRST

JTAG/FACTORY

2.8V

E12 SAGEMCOM FACTORY USE 2.8V E13 SAGEMCOM FACTORY USE 2.8V E14 /GPIO2 GPIO 2.8V E15 /GPIO1 GPIO 2.8V E16 /RF_TX RF 2.8V E17 /PCM_CLK PCM 2.85V E18 /PCM_SYNC PCM 2.85V E19 /PCM_OUT PCM 2.85V E20 /PCM_IN PCM 2.85V E21 GND POWER 0V E22 SAGEMCOM FACTORY USE 2.8V E23 SAGEMCOM FACTORY USE 2.8V E24 SAGEMCOM FACTORY USE 2.8V E25 /UART0_RXD UART 0 2.85V

Figure 31 : HiLoNC V2 51 pads with their power domains

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 31/66

HiLoNC

Pads

Signal Name Function Power domain

E26 /GPIO3 GPIO 2.8V E27 GND RF 0V E28 /ANTENNA RF 3.7V E29 GND RF 0V E30 VBATT POWER 3.7V E31 VBATT POWER 3.7V E32 /UART0_TXD UART 0 2.85V E33 /UART1_DSR UART 1 2.8V E34 /UART1_DCD UART 1 2.8V E35 /UART1_RI UART 1 2.8V E36 /UART1_DTR UART 1 2.8V E37 /UART1_RTS UART 1 2.85V E38 /UART1_RX UART 1 2.85V E39 /UART1_TX UART 1 2.85V E40 /UART1_CTS UART 1 2.85V E41 /POK_IN POWER ON 3.0V E42 /PWM2 PWM 2.85V E43 /PWM1 PWM 2.85V E44 /SIM_CLK SIM 1.8V or 2.9V E45 /SIM_RST SIM 1.8V or 2.9V E46 /SIM_DATA SIM 1.8V or 2.9V E47 VSIM SIM 1.8V or 2.9V E48 VBATT POWER 3.7V E49 GND POWER 0V E50 /HSET_OUT_P AUDIO 3.7V E51 /HSET_OUT_N AUDIO 3.7V

Figure 32 : HiLoNC V2 51 pads with their power domains…continued

4.14.2 IO DC PRESENCE BEFORE POWER ON.

When the VBAT is available but the module not yet started, the following I/O's raised their output.

• VBACKUP raise to 3V

• POK_IN raise to 3V

• HSET_N raise to 1.4V

• HSET_P raise to 1.4V

4.14.3 SIDE EFFECTS OF A RETRO SUPPLY (CURRENT RE-INJECTION)

Interactions or connections between the HiLoNC V2 module and the external systems can lead to retro power supply side effects, or current re-injection through pads while the module is not yet fully powered up (means VBAT lower than its minimum 3.2V). If some precaution and simple rules are not followed, those effects can in worst case result in a deadlock module, not able to start up or to communicate.

Deadlock could happen if the retro supply occurs before the module start. The flow back current could in the worst case prevent the module to start.

The very same behaviour can happen in a normal use conditions when the lines connecting to the module to the external system uses a non compliant voltage higher than the module IO power domain (2.85V). This results in a current flow back inside the module and can lead to a deadlock system on the next start if this retro supply has continued while the system was powered off or under powered (under 3.2V). An over voltage on any line can also damage the HiLoNC V2 module.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 32/66

Those consequences are very rare but exist. Therefore, the rules and advises given on every chapter of this application note must be followed.

To avoid any power up issue, here are the rules:

Avoid any over voltage on the buses lines connected to the module.



When the module is off, do not apply any voltage on lines connected to the module.



The over voltage can be avoided by using the same power domain voltage.

 Avoid 5V or 3.3V systems straight connection to 2.8V HiLoNC V2 lines.  Use level adaptors when the power domain requires it.

When the module is off:  Powers off the buses lines of the main system that are connected to the module, this avoid any flow back current (re-injection) and of course help a lot to improve and control the power consumption. This last issue is important as in off mode there is not control of the current inside the module and can results in a loss of current by leakage through the I/Os of the module.

4.14.4 EXAMPLE OF A CURRENT RE-INJECTION ON U.A.R.T.

Current re-injection appears when the module is off or not powered and I/Os connected to the module still powered. Example: UART bus powered from the DTE side before the module is powered. This can result in a bad starting behaviour.

To avoid current re-injection, simply do not supply the lines connected to the module before the module



switches on. Power up the module first using the POK_IN Line then open the UART lines for the DTE side and all necessary I/O, this will avoid leakage of current improving the power consumption and avoid any possible deadlock issue during the power up process.

Power supply domain

I max = 15mA

Clamp

Diode

IN Buffer

Clamp

Diode

OUT Buffer

Figure 33: Digital Pad-out clamp diode

All the digital pads have this structure a current re-injection by supplying the lines with a non compliant



voltage range must be avoided. (From -0.4V up to 2.8V+0.4V)

Vd = 0.4V

Pad_X

Vd = 0.4V

I max = 15mA

Reverse currents over 15mA will damage the chip. Avoid this issue. Keep the connected line voltage



between 0 and 2.8V.

For an interface with a CMOS 3.3V system or TTL 5V system, use level adapters powered by 2 supplies:



a 2.8V from a LDO IC which is enabled by VGPIO signal and the other external required voltage 3.3V or 5V.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 33/66

If a Level shifter is used or a RS232 adapter, use the VGPIO signal as the enable signal to avoid any



current re-injection before the module start.

If a straight connection is used between the HiLoNC V2 and the DTE UART it is necessary to isolate host



and HiLoNC V2 module in order to avoid generating current re-injection through when HiLoNC V2 is switchedoff.

Example of schematic (only useful signals are represented):

VGPIO

DTR, RTS, RXD

HiLoNC V2

DCD, DSR, CTS, TXD, RI

Host

Figure 34: Hardware interface diodes solution between HiLoNC V2 and host

HiLoNC V2

DTR, RTS, RXD

DCD, DSR, CTS, TXD, RI

Figure 35: Hardware interface buffers solution between HiLoNC V2 and host

Buffer

Tri state command

Host

4.14.5 ADVICES FOR EVERY POWER DOMAIN

• To avoid any current re-injection on VANA (2.85V)

 If an external bias voltage over VANA is used for the microphone, use a 10µF serial capacitor to block the DC voltage.

 If a voltage higher than VANA has to be measured by the ADC, use external resistor divider to limit it.  if PWM bus is output only, the external system is supposed to be in input on the same voltage domain, if it is

not the case or if its inputs are pulled up and able to source current while the module is off, then simply use open drain or open collector transistors to avoid any flow back current to the module.  The external system connected to the module by the UART has to switch its UART lines off while the module is off. If the external system cannot commands its UART lines off, then it is necessary to add a buffer between the module and the external system to prevent any issue. In this last case, the buffer would have to be enabled by the VGPIO voltage that is only available when the module starts. This applies to TXD, RXD, RTS, CTS which are on this power domain and also to the lines on the VGPIO power domain (see here after).

• To avoid any current re-injection on VGPIO (2.80V)

 Do not connect a power supply to the VGPIO pad. This pad is an LDO output only.  The reset signal is internally pulled up and can be connected to an open drain transistor.  The GPIOs have to be used in compliance of the power domain and when the module is off, the external

system has to shut off its GPIOs.

 The SPI bus has to be not connected to the external system.  The JTAG bus has to be not connected to the external system.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 34/66

 The UART lines on this power domain (DCD, DTR, DSR, RI) have to follow the same rules as those on VANA domain (TXD, RXD, RTS, CTS). See have above.  A resistor of 10KΩ has to be connected to the E11 (NTRST) pad and GND to pull down this I/0, preventing any deadlock due to VGPIO current re-injection.

• To avoid any current re-injection on VPERM (3.0V)

 The POK_IN signal is internally pulled up and can be connected to an open drain transistor.

• To avoid any current re-injection on VRTC (3.0V)

 The VBACKUP signal has to be only connected to a DC coin 3V battery or a capacitor of 10µF.

• To avoid any current re-injection on VSIM (1.8V or 2.9V)

 Use only VSIM pads to supply the sim card or sim chip.

• To avoid any current re-injection on VBAT (3.2V to 4.5V)

 Use a VBAT signal with a fast rise time to have a VBAT final value as fast as possible. (see hereafter)  In case of needs, use 2 serial capacitors of 10µF to connect the audio speaker lines to the external system

inputs.

4.14.6 CASE OF VBAT RISE TIME

The VBAT rise time from 0V to its final value has to be lower than 1ms possible failure during the power up. If this value cannot be guaranteed, then some MOS transistors could be used to create a fast rise time switch able to quickly commute from the VBAT final value to the modules power pads.

(1)

This value will be updated to a higher final value including the worst case.

(1)

. This is necessary in order to avoid any

4.14.7 START- UP

To start the module, first power up VBAT, which must be in the range 3.2V ~ 4.5V, and able to provide 2.2A during the TX bursts (Refer to the module specification for more details).

POK_IN is a low level active signal internally pulled up to a dedicated power domain to 3V.



As POK_IN is internally pulled up, a simple open collector or open drain transistor can be used for ignition.

Warning: The POK_IN will become low after module is ready. An open collector or open drain transistor must be used. The POK_IN can not be directly driven by a GPIO signal.

To start the module, a low level pulse must be applied on POK_IN during 2000 ms.



RESET must not be Low during that period of time



After a few seconds, the CTS goes to the active state when the module is ready to receive AT commands.

VGPIO is a supply output from the module that can be used to check if the module is alive.



• When VGPIO = 0V the module is OFF

• When VGPIO = 2.8V the module is ON (It can be in Idle, communication or sleep modes)

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 35/66

commands

Max 7 seconds

Module is

OFF

2000ms

POK_IN

Software Loading

spike

CTS

Typ 5 seconds

Figure 36: Power ON sequence

4.15 UART SIGNALS AT POWER ON

Module is

VGPIO

Module is ready

to receive AT

The UART signals are low level active therefore these signals rise up when the module starts. During around 70ms (see figure below), those signals present a transient spike. Those spikes behaviour at start up are normal, however pay attention to them when a CTS low level detection is used do send AT commands. Only DSR and CTS signals get low after the end of the start up procedure.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 36/66

TXD

RXD

DTR

DCD

DSR

RTS

Max 7 seconds

70ms

30ms

150ms

OFF

POK_IN

CTS

Module is

2000ms

Module is ON

Module UART interface is ON

Module is ready to

receive AT commands

Typ 5 seconds

Transients spikes during power on sequence

Figure 37: Full UART signals during the power on sequence.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 37/66

send AT

4.16 POWER ON AND SLEEP DIAGRAMS

Those 2 diagrams show the behaviours of the module and the DTE during the power on and then in the sleep modes.

DTE is in idle mode

U.A.R.T.

closed ?

VBAT≥3.2

Volts min

POK_IN

LOW for 2s

AND Reset

High?

KSUP notified if KSREP

VGPIO rise to 2.8V

CTS is Low and /or

activated

Figure 38: Diagram for the power on

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

Module is ready

to receive and

HiLoNC V2 Application Note

11 March 2011 - page 38/66

or the

mode

Module is ready to receive and send AT

Sleep mode request

Ksleep = 1 OR

( Ksleep = 0

AND

DTR = High)

Delay to enter the sleep

mode

DTE could also

be in sleep

VGPIO remains at 2.8V

Module is in

sleep mode

Wake up incoming event such as:

RI signal

connected

and

programmed?

CTS is High

The wakes up periods are set by the network DRX

• Network event.

• Alarm interruption.

• DTR interruption.

• RTS interruption.

Figure 39: Diagram for the sleep mode

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

RI wakes the DTE

DTE is in idle mode

HiLoNC V2 Application Note

11 March 2011 - page 39/66

GPIO

4.17 MODULE RESET

To reset the module, a low level pulse must be sent on RESET pad during 10 ms. This action will immediately restart the HiLoNC V2 module. It is therefore useless to perform a new ignition sequence (POK_IN) after.

SAGEMCOM recommends using this feature in case of emergency, freeze of module or abnormal longer



time to respond to AT Commands, this signal is the only way to get the control back over the HiLoNC V2 module.

RESET is a low level active signal internally pulled up to a dedicated power domain.



As RESET is internally pulled up, a simple open collector or open drain transistor can be used to control it.

2.4V min

2.8V

RESET_IN: 7

SAGEM HiLoNC

V2 Module

DCE

Figure 40: Reset command of the HiLoNC V2 by an external GPIO

The RESET signal will reset the registers of the CPU and reset the RAM memory as well.

As RESET is referenced to VGPIO domain (internally to the module) it is impossible to make a reset



before the module starts or try to use the RESET as a way to start the module.

Another solution more costly would be to use MOS transistor to switch off the power supply and restart the power up procedure using the POK_IN input line.

0.4V max

10ms

HOST DTE

4.18 MODULE SWITCH OFF

An AT command “AT*PSCPOF” allows to switch off "properly" the HiLoNC V2 module. In case of necessary the module can be switched off by controlling the power supply. This can be used for example when the system freezes and no reset line is connected to the HiLoNC V2. In this case the only way to get the control back over the module is to switch off the power line. If the system is on a battery, it is wise to have a control of the power supply by a GPIO with for example the following schematic.

Figure 41: Power supply command by a GPIO

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 40/66

This kind of schematic could also be used to save few micro amperes in case of need. As the module has



a drain current of up to 56µA, this kind of function could lower it to the current through R4.

These, are the behaviours of the VGPIO and the CTS signal during the power off sequence.

AT*PSCPOF

Module is ON

POK_IN is low

Typ 2 seconds

Module is

OFF

POK_IN is high

VGPIO

CTS

Figure 42: Power OFF sequence for POK_IN, VGPIO and CTS

4.19 SLEEP MODE MANAGEMENT AND POWER CONSUMPTION

The AT command “AT+KSLEEP” allows to configure the sleep mode.

When AT+KSLEEP=1 is configured:

• The HiLoNC V2 module decides by itself when it enters in sleep mode (no more task running).

• “0x00” character on serial link wakes up the HiLoNC V2 module.

When AT+KSLEEP=0 is configured:

• The HiLoNC V2 module is active when DTR signal is active (low electrical level).

• When DTR is deactivated (high electrical level), the HiLoNC V2 module enters in sleep mode after a

while.

• On DTR activation (low electrical level), the HiLoNC V2 module wakes up.

When AT+KSLEEP=2 is configured:

• The HiLoNC V2 module never enters in sleep mode.

In sleep mode the module reduces its power consumption and remains waiting for the wake up signals either from the network (i.e. Read paging block depending on the DRX value of the network) or the operating system (i.e. timers wake up timers activated) or the host controller (i.e. character on serial link or DTR signal).The power consumption should look like the following example for DRX9.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 41/66

Figure 43: Power consumption at DRX9 (with RS-NGMO2 power supply)

When the HiLoNC V2 module leaves the sleep mode thanks to the network incoming signal or by action of the user the power consumption will step from the <1.7mA to 15mA and then to 25mA in around 2 seconds.

The behaviour of the system at wake-up:



• System resumes from clock 32 MHz, the power consumption rises to around 15mA.

• System resumes the hardware blocks, the power consumption rises to around 25mA.

To perform the correct measurement of the power supply of a system using a HiLoNC V2 module, refer to



the specification TW0.9 version 4.7 June 2008 chapter "standby test procedure" from the GSM association. This specification explains how to proceed and what apparatus have to be used to perform the test.

Check also SAGEMCOM document "Getting started with the current consumption measurement"



The main parameters for a compliant measurement are:

Parameter Idle Mode Setting Idle Mode Setting

Measurement Serial Resistance 0.5 ohms Tolerance/Type. 1%, 0.5W, high precision metal film resistor

Sampling frequency 50 k samples/s Resolution 0.1mA over the full dynamic range of module currents Noise floor Less than lowest ADC step

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 42/66

5. RECOMMENDED I/OS AND COMPONENTS ON THE FINAL PRODUCT

The design of the customer’s board (on which the module is soldered) must provide an access to following signals when the final product will be completely integrated.

To upgrade the module software, SAGEMCOM recommends providing a direct access to the module



serial link through an external connector or any mechanism allowing the upgrade of the module without opening the whole product.

Serial link:

TXD Output UART transmit

RXD Input UART receive

To trace the module software, SAGEMCOM recommends providing a direct access to the module trace



port UART0 (2 I/Os) through internal test points (TP) located on the customer's main board.

The board has to feature as minimum those external components.

A capacitor of 47µF on the VBAT near pads 30 and 31.



A capacitor of 10µF on VBACKUP when no backup battery is used.



6. ESD & EMC RECOMMENDATIONS

6.1 HILONC V2 ALONE

The HiLoNC V2 module alone can hold up to 2KV on each of the 51 pads including the RF pad.

6.2 HANDLING THE MODULE

HiLoNC V2 modules are designed and packaged in tape-and-real for factories SMT process. HiLoNC V2 modules contain electronic circuits sensitive to human hand's electrostatic electricity. Handling without ESD protection could result in permanent damages or even destruction of the module.

6.3 Customer’s product with HiLONC V2

If customer’s design must stand more than 2kV on electrostatic discharge, following recommendation must be followed.

6.4 Analysis

ESD current can penetrate inside the device via the typical following components:

• SIM connector

• Microphone

• Speaker

• Battery / data connector

• All pieces with conductive paint.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 43/66

In order to avoid ESD issues, efforts shall be done to decrease the level of ESD current on electronic



components located inside the device (customer’s board, input of the HiLoNC V2 module, etc…)

6.5 Recommendations to avoid ESD issues

Insure good ground connections of the HiLoNC V2 module to the customer’s board.



Flex (if any) shall be shielded and FPC connectors shall be correctly grounded at each extremity.



Put capacitor 100nF on battery, or better put varistor or ESD diode in parallel on battery and charger wires



(if any) and on all power wires connected to the module.



devices.

Uncouple microphone and speaker by putting capacitor or varistor in parallel of each wire of these

7. RADIO INTEGRATION

Note that radio engineering competences are mandatory to get accurate radio performance on customer’s



product.

7.1 ANTENNA

A 50Ω line matching between module and customer’s board, and the RF antenna is required.

Figure 44: Antenna connection



Keep matching circuit on customer’s board but with direct connection in the first step – it could be

necessary to make some adjustment later, during RF qualification stage.

The selected antenna must comply with FCC RF exposure limits in GSM850 and PCS1900 band :

• GSM850 : MPE < 0.55mW/cm

• PCS1900 : ERP < 3W

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

(Distance is 20 cm)

HiLoNC V2 Application Note

11 March 2011 - page 44/66

For antenna detection presence circuit refer to the dedicated document:



URD1 OTL 5365.1 065 71466 ed 01 - Hilo-HiLoNC Antenna Detection

Figure 45: Antenna detection circuit

7.2 GROUND LINK AREA

SAGEMCOM emphasizes the fact that a good ground GND contact is needed between the module and the customer’s board to have the best radio performances (spurious, sensitivity…).

All HiLoNC V2 GND pads must be connected to the GND of the customer’s board.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 45/66

Not correct

connection

Correct

connection

7.3 LAYOUT

Isolate RF line and antenna from others bus or signals



No signals on 50 ohms area and if that is not possible, add ground shielding using different layers.



Do not add any ground layer under the antenna contact area.



Varnish must be present on all the grey area of the customer's board (expect solder pads) to isolate



HiLoNC V2 module from the customer’s board

Figure 46: Mandatory area for varnish

This recommendation is due to the presence of signals (below varnish) and fiducials and golden tests



points and UL PCB marking (without varnish area in Yellow on the picture above) on the back side of the module. If customer’s board has layout or via without varnish below the HiLoNC V2 module, short-circuits could occur between them.

Free CAD software can be used to compute the stack-up parameter that leads to a compliant 50Ω RF



track.

Connection between two RF tracks of different widths or of a FR line with a smaller pad component must be smoothed to keep a correct RF adaptation.

Figure 47: Connection of RF lines with different width

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 46/66

7.4 MECHANICAL SURROUNDING

 Do not apply mechanical pressure over the HiLoNC V2 shield, this could damage the mechanical

structure of the shield and lead to internal short-circuits or other undesirable issues.

Avoid any metallic part around the antenna area



Keep FPCs and battery contact (if any) far from antenna area.



FPC's (if any) have to be shielded



7.5 OTHER RECOMMENDATIONS – TESTS FOR PRODUCTION/DESIGN

SAGEMCOM guarantees the RF performances in conductive mode but strongly recommends making RF measurements in an anechoic chamber in radiated mode (tests conditions for FTA): the radiated performances strongly depend on radio integration (layout, antenna, matching circuit, ground area…..)

8. AUDIO INTEGRATION

Audio mandatory tests for FTA are in handset mode only so a particular care must be brought to the design of audio (mechanical integration, gasket, electronic) in this mode. The audio norms which describe the audio tests are 3GPP TS 26.131 & 3GPP TS 26.132.

Note that acoustic competences are mandatory to get accurate audio performance on customer’s product.



8.1 MECHANICAL INTEGRATION AND ACOUSTICS

Particular care to Handset Mode:

To get a better audio output design (speaker part):

The speaker must be completely sealed on front side.



The front aperture must be compliant with speaker supplier’s specifications



The back volume must be completely sealed.



The sealed back volume must be compliant with speaker supplier’s specifications



Take care of the design of the speaker gasket (elastomer).



Foresee a stable and large enough area for the gasket of the artificial ear.



To get a better audio input design (microphone part):

Take care of the design of the microphone (elastomer).



All receivers must be completely sealed on front side.



Microphone sensitivity depends on the shape of the device e.g. about –40 ±3 dBV/Pa.



Promote the use of pre-amplified microphone. If needed, use a pre-amplification stage.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 47/66

As audio input and output are strongly linked:

Place the microphone and the speaker as far as possible from one another.



8.2 ELECTRONICS AND LAYOUT

Avoid Distortion & Burst noise

Audio signals must be symmetric (same components on each path).



Differential signals must be routed parallel.



Audio layer must be surrounded by 2 ground layers.



The link from one component to the ground must be as short as possible.



If possible separate the PCB of the microphone and the one of the speaker.



Reduce as much as possible the number of electronics components (loss of quality, more dispersion).



Audio tracks must be larger than 0.5 mm.



9. RECOMMENDATIONS ON LAYOUT OF CUSTOMER’S BOARD

9.1 GENERAL RECOMMENDATIONS ON LAYOUT

There are many different types of signals in the module which are disturbing each other. Particularly, Audio signals are very sensitive to external signals as VBAT... Therefore it is very important to respect some rules to avoid disruptions or abnormal behaviour.

Magnetic field generated by VBAT tracks may disturb the speaker, causing audio burst noise. In this case,



modify layout of the VBAT tracks to reduce the phenomena.

9.1.1 Ground

A ground plane as complete as possible

 



of the layout of those two layers with a ground plane connected to main ground with as much vias as possible.

9.1.2 Power supplies

Ground of components has to be connected to the ground layer through many vias not regularly

distributed.

Top and bottom layer shall have as much as possible of ground planes. Flood the empty remain surface

Layer for power supply signals (VBAT, VGPIO) is recommended.



Any loop of power signals layout must be avoided on the design.



Suitable power supply (VBAT, VGPIO) track width and thickness.



Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 48/66

9.1.3 Clocks

Clock signals must be shielded between two grounds layer and bordered with ground vias.



9.1.4 Data bus and other signals

Data bus and commands have to be routed on the same layer; none of the lines of the bus shall be



parallel to other lines

Lines crossing shall be perpendicular



Suitable other signals track width, thickness.



Data bus must be protected by upper and lower ground plans



9.1.5 Radio

Provide a 50 Ohm micro strip line for antenna connection



9.1.6 Audio

Differential signals have to be routed together, parallel (for example HSET_OUT_P/HSET_OUT_N).



Audio signals have to be isolated, by pair, from all the other signals (ground all around each pair).



Cancel any loops between VBAT and GND next to the speaker to avoid the TDMA burst noise in the



speaker during a communication.

The single-end audio signal should be adopted the same rules as differential signals.



GND

HSET_OUT_P

HSET_OUT_N

GND

Figure 48: Layout of audio differential signals on a layer n

GND

Layer n-1

HSET_OUT_P

GND

Figure 49: Adjacent layers of audio differential signals

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

Layer n

Layer n+1

HiLoNC V2 Application Note

11 March 2011 - page 49/66

9.2 EXAMPLE OF LAYOUT FOR CUSTOMER’S BOARD

The following figure shows an example of layer allocation for a 6 layers circuit (for reference only): Depending on the customer’s design the layout could also be done using 4 layers.

Layer 1: Components (HiloNC)

Layer 2: Bus

Layer 3: Power supply

Layer 4: Complete GND layer

Layer 5: Audio, clocks, sensitive signals

Layer 6: GND,test points

Figure 50: layer allocation for a 6 layers circuit

10. RECOMMANDATIONS FOR CUSTOMER PRODUCTION

Note for following chapters that except where standards are indicated, the given characteristics should be considered as validated conditions used on SAGEMCOM product.

Other conditions depending of the customer’s factory process are not validated but can be submitted to



SAGEMCOM for proficiency.

10.1 MOISTURE LEVEL

According to IPC/JEDEC J-STD 20, the HiLoNC V2 has the following MSL level: 3 Customer’s module are shipped under a Dry package with all the MSL information labelled.

Floor Life

Standard Accelerated Equivalent

Time Conditions Time (hours) Conditions Time (hours) Conditions

3 168

hours It means that the customer’s factory must process and solder the HiLoNC V2 on the customer’s board at least 168 hours (7 days) after the HiLoNC V2 sealed package have been opened. This duration is given for factory floor conditions of T°<30°C, HR 60%.

<= 30°C/60% RH 192 +5/-0 30°C / 60% RH 40 +1/-0 60°C / 60%RH

Soak requirements Level

If this maximum 7 days duration can not be fulfilled, the HiLoNC V2 part must be baked again.



Unless the factory floor conditions are perfectly controlled, SAGEMCOM does not recommend to wait



until this maximum 7 days duration before soldering the HiLoNC V2 on customer’s board.

For any module exposed to ambient moisture it is therefore highly recommended to proceed to a baking



according to the JEDEC (125°C during 24H) to dry the module before any soldering process

10.2 PACKAGE

The HiLoNC V2 module is delivered in Tape and Reel package which is hermetically sealed to prevent from moisture and ESD. The characteristics of the T&R are given in the drawing below.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 50/66

Figure 51: Factory Tape dimensions

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 51/66

10.3 STENCIL

Below are given soldering characteristics to report the HiLoNC V2 on the customer’s board. Copper footprint is shown in solid line on the figure below. Stencil footprint is shown in dotted line.

Note that the opening and the pads do not strictly recover themselves.



Figure 52 : Solder mask design

10.4 SOLDER PASTE

SAGEMCOM recommends a stencil thickness of 135 µm.



SAGEMCOM recommends use of a “no clean” solder paste. Flux cleaning after module soldering on the



customer’s board is not recommended as it can lead to short circuit, label degradation.

Solder paste: M705-GRN360-K-V (Senju Metal Industry Co., Ltd.) Alloy composition: Sn96.5-Ag3.0-Cu0.5 Melting temperature: solidus 216°C / Peak 217°C / liquidus 220°C

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 52/66

10.5 PROFILE FOR REFLOW SOLDERING

A convection type soldering oven is recommended. Typical usable profile is shown on the next figure. The final profile has to be tuned depending on other elements like solder paste, customer’s board, other components…

Peak temperature: 245°C Average ramp up rate: 3°C/second max Average ramp dacay rate: 3°C/second max

Figure 53 : Typical thermal profile

The HiLoNC V2 module is a Lead-free product which has been validated integrated in a lead-free product, using a lead-free factory process.

No test has been performed using a leaded process. SAGEMCOM does not recommend using a factory



leaded process and does not guarantee any reliable result on the final product.

10.6 SMT MACHINE

HiLoNC V2 is a compact postage stamp sized module optimized for use with pick-and-place machines.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 53/66

10.6.1 Nozzles

SAGEMCOM recommends using SMT machine with nozzle diameters up to 8 mm in order to always have



best prehension of the HiLoNC V2 module.

SAGEMCOM recommends using the following two references of nozzles:



• For the UNIVERSAL GSM FLEXJET the nozzle 340F

• For the SIEMENS, the nozzle type 417

Figure 54 : Flexjet nozzle 340F

Figure 55 : Siemens nozzle 417

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 54/66

10.6.2 Fiducials

Optical inspection for placement is possible with SMD fiducials placed on the bottom side of the HiLoNC V2. SMD fiducials are not symmetrical in order to help optical inspection to define the right orientation.

Figure 56 : Fiducials positions

10.7 UNDERFILL

Despite its important reliability, some customer could request for some specific and extreme applications the underfill of onboard components. The HiLoNC V2’s shield has be designed accordingly to allow this process, as shown in the figure below. More details will be given in a specific application note.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 55/66

Holes

Underfill Injection

Figure 57 : Underfill injection holes

10.8 SECOND REFLOW SOLDERING

Even if SAGEMCOM recommends a single reflow soldering, a second reflow soldering can be conceivable (only if underfill has not been already performed). Positive tests have been performed with HiLoNC V2 on the bottom side.

Second reflow soldering is not possible if HiLoNC V2 module has been already under filled.



10.9 HAND SOLDERING

Hand soldering is possible.

An especial care must be considered to properly position the HiLoNC V2 on its copper footprint during



hand soldering. Begin with pads diagonally opposite to help in proper positioning.

10.10 UNSOLDERING

Manual unsoldering is possible, for repair purpose for example.

A special care must be considered in order to avoid overheating the HiLoNC V2.



For repairing: Usage of hot plate like example below can be considered with additional metallic cubic plate whose dimensions are HiLoNC V2's ones (to heat only HiLoNC V2 surface)

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 56/66

HiLoNC

Electronic board

Cube to

concentrate

the heat

Unsoldering hot

plate

Figure 58 : Laboratory hot plate to unsolder the module

Customer must remember to not have components on the HiLoNC V2 opposite side of the customer’s



board.

11. LABEL

The HiLoNC V2 module is labelled with its own FCC ID (VW3HILONCV2) on the shield side. When the module is installed in customer’s product, the FCC ID label on the module will not be visible. To avoid this case, an exterior label must be stuck on the surface of customer’s product signally to indicate the FCC ID of the enclosed module. This label can use wording such as the following: “Contains Transmitter module FCC ID: VW3HILONCV2” or “Contains FCC ID: VW3HILONCV2”.

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 57/66

12. REFERENCE DESIGN: HiLoNC V2 DEVELOPMENT KIT

Note d’étude / Technical document : URD1– OTL 5665.3– 003 / 72238 Edition 02

HiLoNC V2 Application Note

11 March 2011 - page 58/66

sagemcommunications

16/03/10

Schema electrique

3000348582_R43_000_01

MODULE & SOCKET

CIE HILONC V2 DEMO BOARD

NP in socket version

NPNP

3 6

STEVEN LONG

2 7

50V22pF

C112

CERA_COG

5 4

CMAL

P101

2 3

4 5

GND

189631613

CMAL

VSIM_2V9

COAXFEM_5

189619159

R125

5.6k

VGPIO_2V8

TB101

R123

15k

0.063W

CERA_COG

22pF

C114

0.063W

R115

15k

50V

powvolt47nH

L101

0.063W

100

R119

5% 0.063W

VBACKUP_3V

TB103

CMAL

7 2

CMAL

189631613

8 1

100

CH1

CH2

CH3

CH4

0.063W5%

R121

C119

100nF

CM1218

MX103

100

R120

10V CERA_X5R

0.063W5%

R118

15k

0.063W

8 167

#4#

6 3

5 4

C110

22pFCERA_COG 50V

R110

GND

R111

R108

C113

33pF

CERA_COG

50V

1 3

2 4

VBAT_3V7

R104

100k

R116

KSC221J

S101

0.063W

GND

CMAL

189631613

TB102

CMAL

0.063W5%

R122

100

R102

R101

0.063W5%

R124

100

MX102

CM1218

CH1

CH2

CH3

CH4

GND

TDI

TDO

GND

TB104

189631613

CMAL

VBAT

E48

E49

GND

VBACKUP

E50

HSET_OUT

E51

PWM0

RESET

UART1_CTS

E40

E41

POK_IN

PWM2

E42

E43

PWM1

SIM_CLK

E44

E45

SIM_RST

SIM_DATA

E46

E47

VSIM

E33

DCD

E34RIE35

E36

DTR

E37

RTS

E38

UART1

E39

VGPIO

GPIO3

E26

GND_RF

E27

E28

GND_RF

E29

GND

E30

VBAT

E31

E32

UART0_TXD

DSR

PCM_OUT

E19

AUX_ADC0

E20

PCM_IN GND

E21 E22

JTAG1 JTAG2

E23 E24

TEST

E25

UART0_RXD

E11

TRST

E12

TCK

E13

RTCK

GPIO2

E14

GPIO1

E15 E16

RF_TX PCM_CLK

E17

PCM_SYNC

E18

GND

MODULE_HILONC_V2

HILONC_V2_MODULE

MX101

INTMIC_P

E10

TMS

50V

CERA_COG

22pF

C118

R112

8 1

7 2

C103

5 4

CMAL

50VCERA_COG 22pF

C107

330uF

ALU_2KH/105

25V

C109

10nF

CERA_X7R

16V

GND

C108

6.8pF CERA_COG

50V

GND

16V

CERA_X7R

C144

10nF

GND

50V

CERA_COG

22pF

C117

1 2

#4#

5 6

3 4

5 #

R109

7 8

R106

2 7

50VCERA_COG 22pF

C111

1 8

3 6

4 5

1 8

R105

4 5

C106

22pFCERA_COG 50V

3 6

2 7

22pFCERA_COG 50V

1 8

4 5

C104

22pF

CERA_COG

50V

GND

CR103

5.6V

GND

VGPIO_2V8

C115

# 78

VGPIO_2V8

VBACKUP_3V

CR101

5.6V

CR102

6 3

3 6

2 7

50VCERA_COG 22pF

C102

1 8

50VCERA_COG 22pF

C105

1 8

2 7

4 5

GND

3 6

2 7

C101

22pFCERA_COG 50V

1 8

RESET

TDI

TDO

GND

VSIM_2V9

SIM_DATA

E46

E47

VSIM

VBAT

E48

E49

GND

VBACKUP

E50

HSET_OUT

E51

PWM0

E39

VGPIO

UART1_CTS

E40

E41

POK_IN

PWM2

E42

E43

PWM1

SIM_CLK

E44

E45

SIM_RST

E32

UART0_TXD

DSR

E33

DCD

E34RIE35

E36

DTR

E37

RTS

E38

UART1

TEST

E25

UART0_RXD

GPIO3

E26

GND_RF

E27

E28

GND_RF

E29

GND

E30

VBAT

E31

E17

PCM_SYNC

E18

PCM_OUT

E19

AUX_ADC0

E20

PCM_IN GND

E21 E22

JTAG1 JTAG2

E23 E24

INTMIC_P

E10

TMS

E11

TRST

E12

TCK

E13

RTCK

GPIO2

E14

GPIO1

E15 E16

RF_TX PCM_CLK

GND

SUP_HILONC_V2

HILONC_V2_MODULE

MX104

C120

33pF

CERA_COG

50V

C116

22pF CERA_COG

50V

R114

3 #

R113

5 6

GND

VSIM_2V9

4 5

6 3

0.063W5%

R117

100k

N/P_PMOSFET

Q101

ON/OFF

R1_C1

VIN_R1

VOUT_C1

VBAT_3V7

R103

# 12

FET_PMOS

FDC6331L

189778891

R107

SIM_CLK

SIM_RSTSIM_DATA

VBACKUP_3V_S

HSET_OUT_P

HSET_OUT_N

PWM0_S

RESET_IN_S

JTAG_TDI_S

JTAG_TDO_S

ANTENNA

JTAG_RTCK_S

GPIO2_S

GPIO1_S

RF_TX_S

PCM_CLK_S

PCM_SYNC_S

PCM_OUT_S

AUX_ADC0

PCM_IN_S

JTAG1_S

JTAG2_S

TEST_S

UART0_RXD_S

GPIO3_S

ANTENNA

VBAT_3V7_S

UART0_TXD_S

UART1_DSR_S

UART1_DCD_S

UART1_RI_S

UART1_DTR_S

UART1_RTS_S

UART1_RXD_S

UART1_TXD_S

VGPIO_2V8_S

UART1_CTS_S

POK_IN

PWM2_S

PWM1_S

ANTENNA

GPIO1

AUX_ADC0

INTMIC_P

JTAG_TMS_S

JTAG_TRST_S

JTAG_TCK_S

PCM_IN

JTAG1

GPIO2

GPIO1

RF_TX

PCM_CLK

JTAG_RTCK

JTAG_TCK

JTAG_TRST

JTAG_TMS

INTMIC_P

HSET_OUT_N

HSET_OUT_P

VBAT_3V7_S

GPIO3

SIM_DATA

SIM_RST

SIM_CLK

PWM1

UART1_RXD

UART1_RTS

UART1_DTR

UART1_RI

GPIO3

UART0_RXD

TEST

JTAG2

JTAG_TDO

JTAG_TDI

RESET_IN

PWM0

UART1_TXD

UART1_CTS

POK_IN

PWM2

UART0_TXD

UART1_DSR

UART1_DCD

PCM_SYNC

PCM_OUT

VBAT_3V7_S

UART1_DTR

UART1_RI

UART1_DCD

UART1_DSR

UART0_TXD_S

UART1_TXD

UART1_RXD

UART1_RTS

UART0_TXD

UART1_CTS

PWM2

PWM1

INTMIC_P

HSET_OUT_N

HSET_OUT_P

SIM_RST

SIM_CLK

VBACKUP_3V_S

JTAG_TMS

JTAG_TRST_S

JTAG_TCK

JTAG_RTCK_S

PWM0

PWM0_S

RESET_IN_S

JTAG_TDI_S

RESET_IN

JTAG_TDO

JTAG_TRST

JTAG_RTCK

JTAG_TDI

GPIO2

GPIO2_S

RF_TX

RF_TX_S

GPIO3

TEST

JTAG1

PCM_OUT

GPIO1

PCM_CLK

JTAG2

PCM_IN

PCM_SYNC

UART0_RXD

JTAG_TMS_S

JTAG_TCK_S

GPIO1_S

PCM_CLK_S PCM_SYNC_S

PCM_OUT_S

AUX_ADC0

PCM_IN_S

JTAG1_S

JTAG2_S

TEST_S

UART0_RXD_S

GPIO3_S

UART1_DSR_S

UART1_DCD_S

UART1_RI_S

UART1_DTR_S

UART1_RTS_S

UART1_RXD_S

UART1_TXD_S

VGPIO_2V8_S

UART1_CTS_S

POK_IN

PWM2_S

PWM1_S

SIM_DATA

JTAG_TDO_S

HiloNC V2 Application Note

sagemcommunications

16/03/10

Schema electrique

3000348582_R43_000_01

UART1

CIE HILONC V2 DEMO BOARD

253309613

STEVEN LONG

MENTOR

CH4

GND

5.5V

CM1218

MX202

CH1

CH2

CH3

T2IN

T2OUT

T3IN

T3OUT

T4IN

T4OUT

T5IN

T5OUT

VCC

R1OUTB

R2IN

R2OUT

R3IN

R3OUT

T1IN

T1OUT

FORCEOFF

FORCEON

GND

INVALID

R1IN

R1OUT

MAX3238E

MX205

TRSCV

R201

180

5% 0.063W

200

R220

5% 0.063W

DS206

R221

200

5% 0.063W

11 10

DS205

MX204

MC74LCX04DT

9 8

MC74LCX04DT

MX204

vcc=vcc_2v9,ground=gnd

3 4

R232

10k

5% 0.063W

MX204

MC74LCX04DT

1 2

MC74LCX04DT

MX204

vcc=vcc_2v9,ground=gnd

MX203

MC74LCX04DT

3 4

vcc=vcc_2v9,ground=gnd

R218

180

VBAT_3V7

5% 0.063W

0.063W5%

0.063W

180

R219

100k

R216

5% 0.063W

R217

100k

DS202

DS201

330nF

CERA_X5R

6.3V

330nF

C204

CERA_X5R6.3V

C205

vcc=vcc_2v9,ground=gnd

MX203

MC74LCX04DT

9 8

MC74LCX04DT

MX203

vcc=vcc_2v9,ground=gnd

5 6

MC74LCX04DT

MX204

vcc=vcc_2v9,ground=gnd

13 12

C209

vcc=vcc_2v9,ground=gnd

MX204

MC74LCX04DT

10V

CERA_X5R

100nF

R231

180

5% 0.063W

R229

180

5% 0.063W

R228

180

5% 0.063W

R226

180

5% 0.063W

DS209

DS210

DS207

DS208

TB201

CERA_X5R

10V

GND

188094303

[MX203]

CERA_X5R10V

C203 100nF

CERA_X5R10V

VCC_2V9

GND

C207

100nF

VCC_3V1

100nF

C206 [MX204]

DS204

DS203

180

R206

0.063W

CERA_X5R10V

R205

180

0.063W

CERA_X5R10V

100nF

C202

C201 100nF

P202

5% 0.063W

189734229

5% 0.063W

R210

200

0.063W

200

R209

0.063W

180

R208

5% 0.063W

R207

180

VCC_2V9

R215

100k

CH1

CH2

CH3

CH4

MX201

CM1218

R227

180

0.063W

R225

180

0.063W

200

R222

5% 0.063W

R223

200

5% 0.063W

180

R204

GND

R230

180

GND

VCC_3V1

10k

R233

0.063W

R224

180

5% 0.063W

MC74LCX04DT

MX203

vcc=vcc_2v9,ground=gnd

1 2

11 10

vcc=vcc_2v9,ground=gnd

MX203

MC74LCX04DT

MX203

vcc=vcc_2v9,ground=gnd

GND

100nF

C208

CERA_X5R 10V

R203

180

0.063W

VCC_3V1

VCC_2V9

180

R202

5% 0.063W

GND

R214

200

5% 0.063W

200

R213

5% 0.063W

R212

200

5% 0.063W

UART1_RXD

UART0_TXD

UART0_RXD

200

R211

5% 0.063W

UART1_RTS_TB

UART1_DCD_TB

UART1_CTS_TB

UART1_RI_TB

UART1_DSR_TB

UART1_TXD_TB

UART1_DTR_TB

UART1_RXD_TB

UART1_TXD

UART1_RTS UART1_DTR

UART1_DCD

UART1_CTS

UART1_RI

UART1_DSR

UART1_TXD

UART1_CTS_TB

UART1_DSR_TB

UART1_RTS_TB

UART1_DTR_TB

UART1_RXD_TB UART1_TXD_TB

UART1_DCD_TBUART1_RI_TB

UART1_CTS

UART1_DSR

UART1_DCD

UART1_RTS

UART1_RXD

UART1_RI

UART1_DTR

HiloNC V2 Application Note

sagemcommunications

253309613

Schema electrique

16/03/10

MENTOR

STEVEN LONG

CIE HILONC V2 DEMO BOARD

MICELLANEOUS

3000348582_R43_000_01

S305

091020102

S306

R305

VGPIO_2V8

GND

10nF

VGPIO_2V8

GND

22pF

16VCERA_X7R

C305

50VCERA_COG

C304

R315

S302

GND

GND_ANA

CMAL

VBACKUP_3V

CMAL

GND_ANA

CMAL

GND

C308

VGPIO_2V8

CMAL

TB301

189631296

GND

50VCERA_X7R

1nF

VGPIO_2V8

275V

RV302

0.063W

R318

10k

0.063W5%

R319

100k

846

TB305

188078721

100

R320

KSC221J

GND

0.063W5%

330

R317

S303

R314

330

0.063W

0.063W5%

0.063W

R312

0.063W

47k

R306

0.063W5%

47k

R304

0.063W5%

R303

47k

0.063W5%

47k

R302

0.063W5%

47k

R301

C306

10uF

CERA_X5R

6.3V

PILE_3V

E301

cms.supsmtu2032.r

R311

R310

R309

R308

R307

091020102

S304

GND

NO_PLACE

X301

VGPIO_2V8

16VCERA_X7R

C303

10nF

50VCERA_COG

C302

22pF

189599604

P301

GND_ANA

50VCERA_COG

C301

3.9pF

0.063W5%

R316

RV301

275V

CH1

CH2

CH3

CH4

S301

KSC221J

GND

MX301

CM1218

92735

TB304

188078721

10V

CERA_X5R

100nF

C307

GND

R313

GND

CH1

CH2

CH3

CH4

MX303

CH1

CH2

CH3

CH4

MX302

CM1218

TMS_TB TCK_TB

TRST_TB

RESET_IN

JTAG1

JTAG2

RESET_TB

CM1218

JTAG_TDI

TMS_TB

JTAG_TMS

JTAG_TCK

TCK_TB

RTCK_TB

JTAG_RTCK

TDO_TB

JTAG_TDO

TEST

RESET_TB

TDO_TB RTCK_TB

TDI_TB

AUX_ADC0

POK_IN

AUX_ADC0

POK_IN

RESET_IN

TRST_TB

JTAG_TRST

TDI_TB

HiloNC V2 Application Note

sagemcommunications

CIE HILONC V2 DEMO BOARD

Should be 420pF

STEVEN LONG

MENTOR

16/03/10

Schema electrique

3000348582_R43_000_01

UART0 & PCM

GND_ANA

253309613

GND

10V

CERA_X5R

100nF

C409

189734229

P402

C404

330nF

6.3V CERA_X5R

330nF

C402

6.3V CERA_X5R

0.063W5%

GND

10k

R402

0.063W5%

R401

10k

T4IN

T4OUT

T5IN

T5OUT

VCC

5.5V

VCC_3V1

R3OUT

T1IN

T1OUT

T2IN

T2OUT

T3IN

T3OUT

FORCEON

GND

INVALID

R1IN

R1OUT16R1OUTB

R2IN

R2OUT

R3IN

MAX3238E

MX401

TRSCV

25C128

FORCEOFF

VCC_2V9

GND

GND_ANA

200

R405

0.063W5%

0.063W

R410

C406

R408

0.063W

GND

16V

TANTAL

68uF

MX402

CM1218

CH1

CH2

CH3

CH4

63mW

R416

75k

C411

470pF

CERA_X7R

50V

C408

75k

R411

63mW

DS401

50V

CERA_X7R

470pF

R407

100k

0.063W5%

5% 0.063W

Q401

100k

R406

CMAL

NPN

BC847A

TB403

189631613

CMAL

189631613

TB402

CMAL

180

R404

0.063W5%

5% 0.063W

R403

180

189631613

TB401

VCC_3V1

0.063W

VAG

VAG_Ref

VDD

VSS

20k

R414

MCLK11PDI

3 4

MC145483EJR2

CODEC

MX403

FILTER

BCLKR9BCLKT

FSR7FST

0.063W

R427

180

R424

0.063W

R420

180

10V CERA_X5R

180

R418

0.063W

10V CERA_X5R

C405

100nF

10V

CERA_X5R

100nF

C403

C401

100nF

R425

VCC_2V9

GND

R422

196

0.063W

R426

180

R423

0.063W

R419

180

R417

0.063W

R421

189631613

CMAL

TB404

CMAL

TB405

CERA_X5R

100nF

C412

CMAL

189631613

100nF

CERA_X5R

10V

0.063W

R415

C410

0.063W

CMAL

R412

10V

VCC_2V9

GND_ANA

VCC_2V9

GND_ANA

C413

100nF

CERA_X5R

R409

C407

10nF

CERA_X7R

16V

R413

20k

MX405

CM1218

CH1

CH2

CH3

CH4

0.063W

CH1

CH2

CH3

CH4

CM1218

MX404

PCM_MIC

PCM_SYNC_TB_2 PCM_SYNC_TB_1

PCM_IN_TB_2PCM_IN_TB_1

PCM_CLK_TB_2 PCM_CLK_TB_1

PCM_OUT_TB_2

PCM_OUT_TB_1

PCM_SYNC

PCM_IN

PCM_CLK

PCM_OUT

PCM_OUT_N

PCM_OUT_P

UART0_TXD

UART0_RXD

RF_TX

PCM_IN_TB_1

PCM_IN_TB_2

PCM_SYNC_TB_2

PCM_SYNC_TB_1

PCM_OUT_TB_1

PCM_OUT_TB_2 PCM_CLK_TB_2

PCM_CLK_TB_1

HiloNC V2 Application Note

sagemcommunications

16/03/10

MENTOR

STEVEN LONG

253309613

22pF

C506

CIE HILONC V2 DEMO BOARD

AUDIO

3000348582_R43_000_01

Schema electrique

22pF

C504

CERA_COG

50V

GND_ANA

CERA_COG

50V

189171980

P502

100pF

C510

50VCERA_COG

C509

100pF

50V CERA_COG

CERA_COG50V

100pF

C501

L503

22nH

powvolt

22nH

L504

GND

IN1

IN2

OUT1

OUT2

5% powvolt

FILTRE

FL501

IP4048CX5

EMI/ESD

189602480

CMAL

TB501

CMAL

189602480

CMAL

TB504

CMAL

100pF

P501

189171980

CMAL

CERA_COG 50V

C503

CMAL

GND_ANA

CMAL

TB502

189602480

GND_ANA

GND

CMAL

GND

R504

R502

R501

200mA

25%

GND_ANA

50V CERA_COG

GND

600ohms

L505

100pF

C502

C508

100pF

CMAL

CERA_COG50V

CM1218

MX502

CH1

CH2

CH3

CH4

C514

50V

CERA_COG

22pF

50V

CERA_COG

22pF

C511

22pF

50V

CERA_COG

C513

R503

22pF

GND_ANA

C507

22pF

CERA_COG 50V

C505

CMAL

CERA_COG

50V

CMAL

powvolt5%

L508

22nH

powvolt

IN1

IN2

OUT1

OUT2

22nH

L506

EMI/ESD

IP4048CX5

FL502

FILTRE

GND

L507

600ohm

tol powvolt

CMAL

189602480

CMAL

TB503

25%

200mA

L501

600ohms

GND_ANA

50VCERA_COG

GND

L502

22pF

C512

CH1

CH2

CH3

CH4

powvolttol

600ohm

PCM_MIC

PCM_OUT_N

PCM_OUT_P

MX501

CM1218

INTMIC_P

HSET_OUT_N

HSET_OUT_P

HiloNC V2 Application Note

sagemcommunications

253309613

SIM

3000348582_R43_000_01

Schema electrique

16/03/10

MENTOR

STEVEN LONG

MX603

CM1218

CH1

CH2

CH3

CH4

CIE HILONC V2 DEMO BOARD

22pF

C613

VCC_2V9

CMAL

GND

CERA_COG 50V

CMAL

CERA_COG 50V

C602

33pF

CERA_COG 50V

C603

22pF

5% 0.063W

R603 10

5% 0.063W

R602 56

1 5

P601

CH1

CH2

CH3

CH4

GND

189618305

GND

CM1218

MX601

CMAL

189602480

TB602

CMAL

GND

VDD

GND

SPDT SWITCH

MX604

ADG719

GND

5% 0.063W

R605

180

5% 0.063W

2.2k

R604

I/O_0

GND

FIX1

RST

VDD1VSS

VCC_2V9

GND

SLM76CF

MX602

CLK

470nF

C606

C609

470nF

GND

CERA_X5R 6.3V

GND

CERA_X5R 6.3V

CERA_X5R 10V

C605

100nF

CERA_X5R 10V

100nF

C607

R613

VSIM_2V9

GND

091020102

S601

GND

R612

S3A

S3B

VDD16VSS

GND

5% 0.063W

R614

47k

GND

S1A

S1B

S2A

S2B

SWITCHES

TRIPLE_SPDT

MX605

ADG733

CMAL

TB601

189602480

CMAL

C601

10nF

R601

CERA_X7R 16V

5% 0.063W

NCNC

1 2

R611

VSIM_2V9

CERA_X5R 10V

100nF

C608

R630

R629

R628

R627

5% 0.063W

R610

180

0.063W

R609

180

5% 0.063W

R608

180

5% 0.063W

R607

180

SIM_CLK

SIM_DATA_IC

0.063W

R606

180

SIM_RST_IC_TB

SIM_CLK_IC_TB

SIM_DATA_IC_TBVSIM_IC

SIM_RST_IC_TB

SIM_DATA_CARD_TB

SIM_CLK_CARD_TB

SIM_RST_CARD_TB

VSIM_CARD

SIM_RST_CARD

SIM_RST

SIM_DATA_CARD

SIM_DATA

SIM_CLK_CARD

SIM_CLK_IC

SIM_RST

SIM_DATA

SIM_CLK

SIM_CLK_IC

SIM_RST_IC

VSIM_IC

SIM_DATA_IC

SIM_DATA_IC_TB

SIM_CLK_IC

SIM_CLK_IC_TB

SIM_RST_IC

VSIM_CARD

SIM_GPIO

SIM_CLK_CARD

SIM_RST_CARD

SIM_DATA_CARD

VSIM_CARD

SIM_RST_CARD_TB

VSIM_CARD

SIM_CLK_CARD_TB

SIM_DATA_CARD_TB

VSIM_CARD

SIM_DATA_CARD

SIM_CLK_CARD

SIM_RST_CARD

VSIM_CARD

VSIM_IC

SIM_RST_CARD

SIM_RST_IC

SIM_DATA_CARD

SIM_DATA_IC

HiloNC V2 Application Note

sagemcommunications

MENTOR

STEVEN LONG

253309613

CIE HILONC V2 DEMO BOARD

GPIO & PWM

3000348582_R43_000_01

Schema electrique

16/03/10

200

R711

0.063W5%

22k

R702

0.063W

CMAL

TB704

189631613

VCC_2V9

A6S_8104

13 14

CMAL

DS705

GND

6.3V CERA_X5R

R714

180

0.063W

CH3

CH4

GND

470nF

C702

GND

CM1218

MX704

CH1

CH2

R715

180

0.063W5%

R716

180

0.063W5%

R717

180

0.063W5%

GND

CM1218

MX702

CH1

CH2

CH3

CH4

GND

MC74LCX04DT

MX703

vcc=vcc_2v9,ground=gnd

3 4

VCC_2V9

200

R709

0.063W5%

DS703

CMAL4CMAL

A6S_8104

15 16

11 12

A6S_8104

13 14

0.063W5%

A6S_8104

CMAL

189631296

TB702

R719

CMAL

R708

200

0.063W5%

1 2

180

R718

0.063W5%

VCC_2V9

GND

vcc=vcc_2v9,ground=gnd

MX703

MC74LCX04DT

100nF

C701 [MX703]

10V CERA_X5R

A6S_8104

S701

189836718

1 2

R706

0.063W

Q701

BC847A

NPN

PKM22EPP4001

LS701

R712

100

0.063W5%

DS704

DS702

DS701

A6S_8104

9 10

3 4

A6S_8104

15 16

GND

189836718

S702

A6S_8104

1 2

A6S_8104

0.063W5%

R710

200

A6S_8104

5 6

R703

22k

A6S_8104

7 8

CMAL

TB701

189602480

MX701

CH1

CH2

CH3

CH4

GND

VGPIO_2V8

CERA_X5R

10V

CM1218

MC74LCX04DT

MX703

vcc=vcc_2v9,ground=gnd

13 12

VCC_2V9

C703

100nF

vcc=vcc_2v9,ground=gnd

MX703

MC74LCX04DT

9 8

5 6

MC74LCX04DT

MX703

vcc=vcc_2v9,ground=gnd

11 10

vcc=vcc_2v9,ground=gnd

MX703

MC74LCX04DT

R704

0.063W

22k

R701

0.063W5%

0.063W

200

R707

0.063W5%

R705

GND

CMAL3CMAL

TB703

189631613

CMAL

A6S_8104

11 12

R713

0.063W

A6S_8104

9 10

5 6

A6S_8104

7 8

A6S_8104

3 4

A6S_8104

SIM_GPIO

PWM2

PWM0

PWM1

PWM2_TB

PWM1

PWM0

GPIO1

GPIO2

GPIO3

GPIO1

GPIO2

GPIO3_TB

GPIO2_TBGPIO1_TB

GPIO3

GPIO1_TB

GPIO2_TB

GPIO3_TB

HiloNC V2 Application Note

sagemcommunications

MENTOR

STEVEN LONG

253309613

VDD

CIE HILONC V2 DEMO BOARD

POWER

3000348582_R43_000_01

Schema electrique

16/03/10

ADG719

MX805

SPDT SWITCH

GND IN

R807

100

ALIM_LAB

GND

0.063W

16V

10nF

C807

DS802

1_1

F801

CERA_X7R

1_1

CFEM_2

TB802

189602620

C806

1uF

CFEM_2

TB801

189602500

100

R804

CERA_X5R 16V

0.063W

5% 0.100W

R806

1.2

ALM_EXT_REG

5% 0.063W

R805

510

ADJ

GND

GND(TAB)

OUT

DS801

MIC29302WU_TR

MX801

VREG

0.063W

R835

49.9k

0.063W

R834

150k

1% 0.063W

R831

133k

100nF

C832

CERA_X5R

10V

C836

100nF

CERA_X5R 10V

C833

CERA_X5R 10V

C834

C837

10uF

TANTAL 16V

10uF

ADJ

GND

GND(TAB)

OUT

TANTAL 16V

GND(TAB)

OUT

GND

VCC_3V1

VREG

MX803

MIC29302WU_TR

MX802

VREG

ADJ

GND

VBAT_3V7

VCC_2V9

6.8V

DS805

NTHS2101PT1G

Q802

GND

CR802

FET_PMOS

Q801

NTHS2101PT1G

GND

ALIM_LAB

FET_PMOS

GND

5% 0.063W

R812

100k

5%0.063W

R813

10k

CR801

C821

1% 0.063W

R811

560k

C820

CERA_COG 50V

22pF

C818

22pF

CERA_X5R 10V

47nF

1uF

C819

CERA_COG 50V

CTL

GATE

GND

SENSE

STAT

VIN

CERA_X5R 16V

TB805

GND

LTC4412

MX804

CTRL_PWR

TB804

CMAL

TB803

1% 0.063W

R801

100k

C805

TANTAL 16V

47uF

C810

22pF

CERA_X5R 10V

100nF

10nF

C802

CERA_COG 50V

C803

C804

CERA_X7R 16V

47uF

C801

CERA_X5R 16V

1uF

330uF

C808

TANTAL 16V

R802

49.9k

GND

ALU_2KH/105 25V

3_1

3_2

1%0.063W

VGPIO_2V8

189282163

P802

JACK_4PIN_1

0.063W

R851

47k

5% 0.063W

47k

R852

CR803

GND

ALM_EXT_REG

GND

CR804

CERA_X5R 10V

100nF

C838

TANTAL 16V

C831

10uF

TANTAL 16V

10uF

C835

0.063W

47k

R833

0.063W

R832

47k

0.063W

49.9k

R836

HiloNC V2 Application Note

ge without prior notice. Sagemcom tries to ensure that all information in this document is correct, but does not accept liability for error or

omission. Non contractual document.. All trademarks are registered by their respective owners.

Sagem HILONC APPLICATION NOTE User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual