A
High Reliability Serial EEPROMs
WL-CSP EEPROM family
I2C BUS
BU99901GUZ-W
●Description
BU99901GUZ-W series is a serial EEPROM of I
●Features
1) Completely conforming to the world standard I
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.7～3.6V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.7～3.6V
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write operation (3.3V) : 0.6mA (Typ.)
At read operation (3.6V) : 0.6mA (Typ.)
At standby operation (3.6V) : 0.1µA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) Compact package
10) Data rewrite up to 100,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●Page write
Product number BU99901GUZ-W
Number of pages 32Byte
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Ratings Unit
Impressed voltage VCC -0.3～+6.5 V
Permissible dissipation Pd 220 *1 mW
Storage temperature range Tstg -65～+125 ℃
Action temperature range Topr -40～+85 ℃
Terminal voltage － -0.3～Vcc+1.0 *2 V
*1 When using at Ta=25℃ or higher, 2.2mW to be reduced per 1℃
*2 The Max value of Terminal Voltage is not over 6.5V.
●Memory cell characteristics (Ta=25℃, Vcc=1.7～3.6V)
Parameter
Number of data rewrite times *1 1,000,000 － － Times
Data hold years *1 40 － － Years
*1 Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Ratings Unit
Power source voltage
Input voltage VIN 0～Vcc V
Write
Read 1.7～3.6
Min. Typ. Max.
Vcc
2
C BUS interface method.
2
C BUS.
Limits
2.7～3.3
Unit
V
No.10001EAT15
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
Technical Note
●Electrical characteristics (Unless otherwise specified Ta=-40～85℃､VCC=1.7～3.6V)
Parameter Symbol
"H" Input Voltage1 V
"L" Input Voltage1 V
"H" Input Voltage2 V
"L" Input Voltage2 V
"H" Input Voltage3 V
"L" Input Voltage3 V
"L" Output Voltage1 V
"L" Output Voltage2 V
Min Typ. Max.
0.7Vcc － Vcc+1.0 V 2.5V≦Vcc≦3.6V
IH1
-0.3 － 0.3Vcc V 2.5V≦Vcc≦3.6V
IL1
0.8Vcc Vcc+1.0 V 1.8V≦Vcc＜2.5V
IH2
-0.3 0.2Vcc V 1.8V≦Vcc＜2.5V
IL2
0.9Vcc Vcc+1.0 V 1.7V≦Vcc＜1.8V
IH3
-0.3 0.1Vcc V 1.7V≦Vcc＜1.8V
IL3
－ － 0.4 V IOL=3.0mA , 2.5V≦Vcc≦3.6V (SDA)
OL1
－ － 0.2 V IOL=0.7mA , 1.7V≦Vcc＜2.5V (SDA)
OL2
Limits
Unit Condition
Input Leakage Current ILI -1 － 1 µA VIN=0～Vcc (WP, TEST)
Pull Up Resistance I
Output Leakage Current ILO -1 － 1 µA V
Current consumption
at action
6 － 14 kΩ (SCL,SDA)
LI2
OUT
I
CC1
I
－ － 1.7
CC2
－ － 4.1
Vcc=3.3V , f
Byte Write, Page Write
mA
Vcc=3.6V , f
Random read, Current read, Sequential read
=0～Vcc (SDA)
=400kHz, tWR=5ms
SCL
=400kHz
SCL
Standby Current ISB － － 2.0 µA Vcc=3.6V, SDA ,SCL=Vcc, WP=GND
○Radiation resistance design is not made.
●Action timing characteristics(Unless otherwise specified Ta=-40～85℃､V
FAST-MODE
Parameter Symbol
2.5V≦Vcc≦3.6V
=1.7～3.6V)
CC
STANDARD-MODE
1.7V≦Vcc≦3.6V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL Frequency fSCL － － 400 － － 100 kHz
Data clock "High" time tHIGH 0.6 － － 4.0 － － µs
Data clock "Low" time tLOW 1.2 － － 4.7 － － µs
SDA, SCL rise time *1 tR － － 0.3 － － 1.0 µs
SDA, SCL fall time *1 tF － － 0.3 － － 0.3 µs
Start condition hold time tHD:STA 0.6 － － 4.0 － － µs
Start condition setup time tSU:STA 0.6 － － 4.7 － － µs
Input data hold time tHD:DAT 0 － － 0 － － ns
Input data setup time tSU:DAT 100 － － 250 － － ns
Output data delay time tPD 0.1 － 0.9 0.2 － 3.5 µs
Output data hold time tDH 0.1 － － 0.2 － － µs
Stop condition data setup time tSU:STO 0.6 － － 4.7 － － µs
Bus release time before transfer start tBUF 1.2 － － 4.7 － － µs
Internal write cycle time tWR － － 5 － － 5 ms
Noise removal valid period
(SDA,SCL terminal)
tI － － 0.1 － － 0.1 µs
WP hold time tHD:WP 0 － － 0 － － ns
WP setup time tSU:WP 0.1 － － 0.1 － － µs
WP valid time tHIGH:WP 1.0 － － 1.0 － － µs
*1 Not 100% TESTED
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action
at high speed is not carried out, therefore, at Vcc=2.5V～5.5V , 400kHz, namely, action is made in FASTMODE. (Action is
made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE.
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
t
A
f
A
g
A
●Sync data input/output timing
SCL
(Input)
tHD :STA tHD :DAT
SDA
tBUF
SDA
(Output)
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tSU :DAT
Fig.1-(a) Sync data input / output timing
SCL
tSU:STA tSU:STOtHD:STA
SDA
SCL
START BIT
Fig.1-(b) Start - stop bit
SDA
WRITE DATA( n)
D0 ACK
STOP
CONDITION
Fig.1-(c) Write cycle timing
●Block diagram
TEST
GND
tHIGH
tR tF
tLOW
tPD tDH
WR
START
CONDITIO N
STOP BIT
32Kbi t EEPROM ar ray
12bit
dddress
decoder
12bit
START STOP
Control circuit
High voltage
generating circuit
TEST terminal,please connect GND
Fig.2 Block diagram
Technical Note
SCL
DATA(1)
D1 D0ACK
SDA
WP
tSU：WP
Fig.1-(d) WP timing at write execution
SCL
DATA(1)
D1 D0 ACK ACK
SDA
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data o
address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancels
Slave - word
address regi ster
Power source
e detection
vol ta
CK
DATA(n)
DATA(n)
tHIGH:WP
8bit
Da ta
register
CK
Stop condition
Vcc
WP
SCL
SDA
t
WR
tWR
tWR
ｔHD：
WP
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
A
●Pin assignment and function
B
B1
TEST
A1
SDA
B2
GND
A2
SCL
B3
VDD
A3
WP
1
2
3
Fig.3 BU99901GUZ-W(bottom view)
Land No. Terminal name Input / output Unit
B3 VDD － Power Supply
B2 GND － Reference voltage of all input / output
B1 TEST Input TEST terminal, Connect GND
A3 WP Input Write protect terminal
Technical Note
A2 SCL Input Serial clock input
A1 SDA Input /output Slave and word address, Serial data input serial data output
●Characteristic data (The following values are Typ. ones.)
6
Ta=-40℃
5
Ta=25℃
Ta=85℃
4
3
VIH1,2(V)
2
1
0
0123456
Fig.4 'H' input voltage V
1
0.8
Ta=-40℃
0.6
Ta=25℃
Ta=85℃
VOL2(V)
0.4
0.2
0
0123456
Fig.7 'L' output voltage VOL-IOL(Vcc=2.5V)
SPEC
Vcc(V)
1,2 (SCL,SDA,WP)
IH
SPEC
IOL2(mA)
6
5
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
VIL1,2(V)
2
1
0
0123456
Fig.5 'L' input voltage V
1.2
1
0.8
0.6
Ta=-40℃
ILI(uA)
Ta=25℃
0.4
Ta=85℃
0.2
0
0123456
Fig.8 Input leak current I
SPEC
Vcc(V)
Vcc(V)
SPEC
(SCL,SDA,WP)
IL
(SCL,WP)
LI
1
Ta=-40℃
0.8
Ta=25℃
Ta=85℃
0.6
VOL1(V)
0.4
SPEC
0.2
0
0123456
Fig.6 'L' output voltage VOL-IOL(Vcc=1.7V)
1.2
1
0.8
0.6
ILO(uA)
Ta=-40℃
0.4
Ta=25℃
Ta=85℃
0.2
0
0123456
IOL1(mA)
SPEC
Vcc(V)
Fig.9 Output leak current
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
(
)
●Characteristic data (The following values are Typ. ones.)
4.5
4
3.5
3
ICC1(mA)
Ta=-40℃
Ta=25℃
2.5
Ta=85℃
2
1.5
1
0.5
0
0123456
Fig.10 Current consumption at WRITE operation Icc1
0.6
0.5
0.4
Ta=-40℃
Ta=25℃
0.3
Ta=85℃
ICC2(mA)
0.2
0.1
0
0123456
Fig.13 Current consumption at READ operation Iｃｃ2
5
4
3
Ta=-40℃
Ta=25℃
Ta=85℃
2
tHIGH(us)
1
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.16 Data clock High Period
SPEC
Vcc(V)
(fscl=400kHz)
SPEC
Vcc(V)
fscl=100kHz)
（
SPEC
tHIGH
2
1.5
1
Ta=-40℃
Ta=25℃
Ta=85℃
ICC2(mA)
0.5
0
-0.5
0123456
Fig.11 Current consumption at READ operation Iｃｃ2
2.5
2
1.5
Ta=-40℃
Ta=25℃
ISB(uA)
Ta=85℃
1
0.5
0
0123456
Fig.14 Stanby operation ISB
5
4
Ta=-40℃
3
Ta=25℃
Ta=85℃
2
tLOW(us)
1
0
0123456
Fig.17 Data clock Low Period tLOW
5.9
4.9
3.9
2.9
tSU:STA(us)
1.9
0.9
-0.1
0123456
Fig.19 Start Condition Setup Time
300
200
(ns)
100
0
Ta=-40℃
tSU: DAT(HIGH)
Ta=25℃
-100
Ta=85℃
-200
0123456
Fig.22 Input Data Setup Time
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Vcc(V)
t
Vcc(V)
SPEC
SU : STA
ｔSU: DAT(HIGH)
50
0
-50
-100
Ta=-40℃
tHD:DAT(HIGH) (ns)
tSU : DAT(LOW) (ns)
Ta=25℃
-150
Ta=85℃
-200
0123456
Fig.20 Input Data Hold Time
300
200
100
0
Ta=-40℃
-100
-200
Ta=25℃
Ta=85℃
0123456
Fig.23 Input Data Setup Time tSU : DAT(LOW)
Vcc(V)
(fscl=400kHz)
SPEC
Vcc(V)
SPEC
Vcc（V）
SPEC
Vcc(V)
tHD : DAT
SPEC
Vcc(V)
SPEC
（HIGH）
Technical Note
3.5
3
2.5
Ta=-40℃
2
Ta=25℃
Ta=85℃
1.5
ICC1(mA)
1
0.5
0
0123456
Fig.12 Current consumption at WRITE operation Icc1
10000
1000
100
10
fSCL（ｋHZ）
Ta=-40℃
Ta=25℃
1
Ta=85℃
0.1
0123456
Fig.15 SCL frequency fSCL
5
4
3
Ta=-40℃
Ta=25℃
Ta=85℃
2
tHD : STA(us)
1
0
0123456
Fig.18 Start Condition Hold Time
50
0
-50
-100
tHD :DAT(ns)
-150
-200
Ta=-40℃
Ta=25℃
Ta=85℃
0123456
Fig.21 Input Data Hold Time
4
Ta=-40℃
Ta=25℃
Ta=85℃
3
2
tPD0(us)
1
0
0123456
Fig.24 Data output delay time tPD0
SPEC
Vcc(V)
fscl=100kHz
SPEC
Vcc(V)
SPEC
Vcc(V)
t
HD : STA
SPEC
Vcc(V)
ｔHD : DAT(LOW）
SPEC
Vcc(V)
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
●Characteristic data (The following values are Typ. ones.)
4
tPD1(us)
3
2
1
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0
0123456
Fig.25 Data output delay time
1
0.8
Ta=-40℃
0.6
Ta=25℃
Ta=85℃
0.4
tI(SCL H) (us)
0.2
Vcc(V)
SPEC
0
0123456
Fig.28 Noise reduction efection time
Vcc(V)
ｔPD1
tI（SCL H）
5
4
Ta=-40℃
Ta=25℃
3
Ta=85℃
tBUF(us)
2
1
0
0123456
Fig.26 BUS open time before transmission
0.6
Ta=-40℃
0.5
Ta=25℃
Ta=85℃
0.4
0.3
tI(SCL L) (us)
0.2
0.1
0
0123456
Fig.29 Noise reduction efection time
0.6
0.5
0.4
Ta=-40℃
0.3
Ta=25℃
Ta=85℃
0.2
tI(SAD L) (us)
0.1
0
0123456
Fig.31 Noise reduction efection time tI（SDA L
Vcc(V)
SPEC
）
0.2
0.1
0
Ta=-40℃
-0.1
Ta=25℃
Ta=85℃
-0.2
-0.3
tSU : WP(us)
-0.4
-0.5
-0.6
0123456
Fig.32 WP setup time
Vcc(V)
SPEC
Vcc(V)
Vcc(V)
SPEC
SPEC
tI（SCL L）
tSU : WP
ｔBUF
Technical Note
6
5
4
3
tWR(ms)
2
Ta=-40℃
Ta=25℃
1
Ta=85℃
0
0123456
Fig.27 Internal writing cycle time
0.6
0.5
0.4
0.3
tI(SDA H) (us)
0.2
0.1
0
0246
Fig.30 Noise reduction efection time
1.2
1
0.8
0.6
0.4
tHIGH : WP(us)
Ta=-40℃
Ta=25℃
0.2
Ta=85℃
0
0123456
Fig.33 WP efective time
Vcc(V)
SPEC
Vcc(V)
Vcc(V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
ｔWR
ｔI（SDA H）
tHIGH : WP
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
S
Technical Note
●I2C BUS communication
○I2C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
I
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7 1-7
SCL
S P
START R/W ACK
condition condition
89 89 89
1-7
ACK STOPACKDATA DATAADDRES
Fig.34 Data transfer timing
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is 'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・The most insignificant bit (
W/R
---
WRITE/READ
) of slave address is used for designating write or read action, and is
as shown below.
W/R
Setting
Setting
to 0 --- write (setting 0 to word address setting of random read)
W/R
to 1 --- read
Type Slave address
BU99901GUZ-W 1 1 1 0 0 0 0
W/R
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
Technical Note
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.
Up to 32 arbitrary bytes can be written.
SDA
LINE
S
T
A
R
T
1 1 0 0
SLAVE
ADDRESS
W
R
I
1st WORD
T
ADDRESS
E
＊
＊ WA
0 0
＊
0 D0
R
A
/
C
W
K
11
2nd WORD
ADDRESS
WA
0
A
C
K
A
C
K
DATA
D7
S
T
O
P
A
C
K
Fig.35 Byte write cycle
SDA
LINE
S
T
A
R
T
1
SLAVE
ADDRESS
0
10 0 0
0
W
R
T
E
R
W
I
A
C
/
K
1st WORD
ADDRESS(n)
＊
＊
＊ ＊ WA
2nd W ORD
ADDRESS(n)
11
A
C
K
Fig.36 Page write cycle
WA
0
S
T
D0
O
P
A
C
K
A
C
K
DATA(n+31)
DATA(n)
D0 D7
A
C
K
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 32 bytes.
(Refer to "Internal address increment of "Notes on page write cycle" in P9/16.)
・As for page write command of BU99901GUZ-W, after page select bit(PS) of slave address is designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to
16 bytes can be written.
・As for page write cycle of BU99901GUZ-W , after the significant 7 bits of word address, are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32
bytes can be written.
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
A
A
A
A
○Notes on write cycle continuous input
SDA
LINE
S
T
A
R
ADDRESS
T
10 0 1P0
SLAVE
P2
P1
W
R
I
T
ADDRESS (n)
E
WA
7
WORD
WA
0
R
/
C
W
K
C
K
Fig.37 Page write cycle
○Notes on page write cycle
List of numbers of page write
Number of pages 32Byte
Product number BU99901GUZ-W
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case of BU99901GUZ-W, 1 page = 32bytes,
but the page write cycle write time is 5ms at maximum
for 32byte bulk write.
It does not stand 5ms at maximum × 32byte = 160ms(Max.).
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level),
data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level.
Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated
DATA (n)
Technical Note
At S TOP (stop bit)
write starts.
S
T
DATA (n+31)
D0 D7 D0
C
K
O
P
C
K
○Internal address increment
Page write mode
WA11 ----- WA5 WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0 0
0 ----- 0 0 0 0 0 1
0 ----- 0 0 0 0 1 0
0 ----- 0 1 1 1 1 0
IEh
0 ----- 0 1 1 1 1 1
0 ----- 0 0 0 0 0 0
---------
Significant bit is fixed.
No digit up
For example, when it is started from address 1Eh,
therefore, increment is made as below,
1Eh→1Fh→00h→01h･･･, which please note.
* 1Eh･･･16 in hexadecimal,
therefore, 00011110 becomes a binary number.
S
T
A
R
T
1 100
Ne xt comman d
tWR (maxim um :5m s)
Command is not ac cepted for this period.
increment
---------
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9/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
(n)
R
R
R
(n)
S
)
Technical Note
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
SDA
LINE
S
T
A
R
ADDRESS
T
10 0 10 0 0
SDA
LINE
Fig.38 Random read cycle
S
T
A
R
T
10 0 1 0 0 0 D0 D7
LINE
DA
S
T
A
R
ADDRESS
T
10 0
W
R
I
SLAVE
SLAVE
ADDRESS
T
E
R
A
/
C
W
K
1st WORD
ADDRESS(n)
＊
＊ ＊ WA
＊
R
E
A
D
A
R
C
/
K
W
11
A
C
K
DA TA(n)
2nd WORD
ADDRES S(n)
Fig. 39 Current read cycle
SLAVE
E
A
D
0 0
0
1
A
/
C
W
K
DATA
D0
D7 D0 D7
A
C
K
Fig.40 Sequential read cycle (in the case of current read cycle)
S
T
A
R
ADDRESS
T
WA
10 0 1
0
A
C
K
S
T
O
P
A
C
K
SLAVE
A
C
K
A1
A2
DATA(n+x
E
A
DATA
D
D7 D0
A0
A
R
C
/
K
W
A
C
K
S
T
O
P
A
C
K
It is necessary to input 'H'
to the last ACK.
It is necessary to input 'H'
to the last ACK.
S
T
O
P
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL
signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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10/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
A
A
A
A
A
A
Technical Note
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.41(a), Fig.41(b), Fig.41(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level)
may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
SCL
SDA
SCL
SDA
Fig.41-(a) The case of 14 Dummy clock + START + START+ command input
Star t
Dummy clock×14 Start×2
2 13
1
Dummy clock×9
1
2
14
Normal command
Normal command
Star t
8
9
Normal command
Normal command
Fig.41-(b) The case of START+9 Dummy clock + START + command input
Star t×9
SCL
1 2 3 8 9 7
Normal command
SDA
Normal command
Fig.41-(c) START × 9 + command input
* Start command from START input.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously,
W/R
= 0, when to carry out current read cycle after write, slave address
W/R
= 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data so forth.
First write command
S
T
Write command
A
R
T
S
T
A
R
T
Slave
address
S
T
O
P
Second write command
During internal write,
ACK = HIGH is sent back.
S
T
tWR
A
R
T
Slave
address
C
K
H
C
…
K
H
…
S
T
A
R
T
Slave
address
t
WR
C
K
H
S
T
A
R
T
Slave
address
C
K
L
Word
address
C
Data
K
L
S
C
T
K
O
L
P
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
Fig.42 Case to continuously write by acknowledge polling
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11/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
A
A
A
A
Technical Note
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.43.)
After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
SDA
WP
・Rise of D0 taken clock
SCL
SDA
Enlarged view
S
T
Slave
A
address
R
T
Word
C
K
address
L
WP cancel invalid area
D1
D0
C
K
L
ACK
D7 D6
D5
D4
D3
D2
SCL
SDA
C
D0
D1
K
L
WP cancel valid area
Data is not written.
Data
・Rise of SDA
D0
C
K
L
ACK
Enlarged view
S
T
O
P
Write forced end
Data not guaranteed
tWR
Fig.43 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig.44.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1 1
0 0
Start condition
Stop condition
Fig.44 Case of cancel by start, stop condition during slave address input
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12/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
A
A
Technical Note
●Cautions on microcontroller connection
○Rs
2
C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
In I
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
R
S
SCL
SDA
'H' output of microcontroller
CK
'L' output of EEPROM
Microcontroller
EEPROM
Fig.45 I/O circuit diagram
Over current flows to SDA line by 'H' output of microcontroller
and 'L' output of EEPROM.
Fig.46 Input/output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2) The bus electric potential ○A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
should sufficiently secure the input 'L' level (V
) of microcontroller including recommended noise margin 0.1Vcc.
IL
R
IOL
S
VCC
RPU=10ｋΩ
VOL
(V
CC
V
－
R
PU+RS
R
S
OL
≦
)×R
S
+∴VOL+0.1V
V
V
－
IL
1.1V
OL
CC
－
0.1V
－
≦
V
CC
IL
CC
V
IL
×R
VIL
Microcontroller
Bus line
capacity CBUS
EEPROM
Example
Fig.47 I/O circuit diagram
When VCC=3V, VIL=0.3V
）
from(2),
R
≦
S
≦
0.3×3－0.4－0.1×3
1.1×3－0.3×3
0.835［kΩ
V
CC,
=0.4V, RPU=10kΩ ,
OL
×
］
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
R
S
RPU=10Ω
'L' output
'H' output
Over current I
Microcontroller
EEPROM
Fig.48 I/O circuit diagram
CC
V
≦
S
R
V
S
R
∴
≧
Example）When V
I
CC
I
CC
=3V, I=10mA
S
R
≧
≧
3
10×10
300［Ω］
-3
PU
10×10
3
www.rohm.com
13/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
Technical Note
●I2C BUS input / output circuit
○Input (SCL, SDA)
Fig.49 Input pin circuit diagram
○Input/Output (SDA)
VDD
Fig.50 Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC
tR
Recommended conditions of tR,tOFF,Vbot
tR tOFF Vbot
10ms or below 10ms or longer 0.3V or below
tOFF
0
Fig.51 Rise waveform diagram
Vbot
100ms or below 10ms or longer 0.2V or below
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
SCL
tL OW
SDA
After Vc c becomes s table
tSU:DAT tDH
Fig.52 When SCL='H' and SDA='L'
After Vcc becomes stab le
tSU:DAT
Fig.53 When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Technical Note
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15/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
BU99901GUZ-W
A
●Ordering part number
B U 9 9 9 0 1 G U Z - W E 2
Technical Note
Part No. Part No.
VCSP30L1
6-φ0.25±0.05
0.05
(BU99901GUZ-W)
1PIN MARK
1.76±0.05
0.06 S
BA
0.38±0.05
A
B
B
A
3
21
P=0.5×2
1.05±0.05
0.275±0.05
0.5
0.08±0.05
0.35MAX
S
(Unit : mm)
Package
GUZ: VCSP30L1
<Tape and Reel information>
Embossed carrier tape(heat sealing method)Tape
Quantity
Direction
of feed
3000pcs
E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
1pin
W-CELL Packaging and forming specification
E2: Embossed tape and reel
Direction of feed
Order quantity needs to be multiple of the minimum quantity.
∗
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16/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.09 - Rev.
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
Notice
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, of ce-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
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A
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