ROHM BU9882F-W Technical data

Memory for Plug & Play

EDID Memory
(For display)

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV

●Description

BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1
for Plug and Play displays.

●Features

1) Compatible with both DDC1

2) Operating voltage range: 2.5V to 5.5V

3) Page write function: 8bytes

4) Low power consumption
Active (at 5V) : 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)

5) Address auto increment function during Read operation

6) Data security
Write enable feature (VCLK)
Write protection at low Vcc

7) Various packages available: DIP-T8(BR24C21) / SOP8(BR24C21F) / SOP-J8(BR24C21FJ) / SSOP-B8(BR24C21FV)

8) Initial data=FFh

9) Data retention: 10years

10) Rewriting possible up to 100,000 times

●Absolute maximum ratings (Ta=25℃)

Parameter Symbol Rating Unit

Supply Voltage VCC -0.3～+6.5 V

Power Dissipation Pd

Storage Temperature

Operating Temperature

Terminal Voltage

* Reduce by 8.0 mW/C over 25C (*1), 4.5mW/℃ (*2,3), and 3.5mW/℃ (*4)

●Memory cell characteristics

Parameter Symbol Rating Unit

Supply Voltage VCC 2.5～5.5 V
Input Voltage VIN 0～VCC V

●Recommended operating conditions

Parameter

Write/Erase Cycle 100,000 - - Cycle

Data Retention 10 - - Year

TM

/DDC2TM

800 (DIP-T8)

450 (SOP8)

450 (SOP-J8)

350 (SSOP-B8)

Tst g - 65 ～+125 ℃
Topr -40～+85 ℃

- -0.3～VCC+0.3 V

Limits

Min. Typ. Max.

TM

*1

*2

*3

*4

Unit

/DDC2

mW

TM

interfaces

No.11002ECT02

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1/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W

Technical Note

●Electrical characteristics - DC (Unless otherwise specified, Ta=-40℃～+85℃､VCC=2.5V～5.5V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Condition

“H” Input Voltage 1 VIH1 0.7VCC - - V SCL, SDA
“L” Input Voltage 1 VIL1 - - 0.3VCC V SCL, SDA
“H” Input Voltage 2 VIH2 2.0 - - V VCLK
“L” Input Voltage 2 VIL2 - - 0.8 V VCLK, VCC≧4.0V
“L” Input Voltage 3 VIL3 - - 0.2VCC V VCLK, VCC＜4.0V
“L” Output Voltage VOL - - 0.4 V SDA, IOL=3.0mA
Input Leakage Current ILI -1 - 1 µA SCL, VCLK, VIN=0V～VCC
Output Leakage Current ILO -1 - 1 µA SDA, VOUT=0V～VCC
Operating Current ICC - - 3.0 mA VCC=5.5V, fSCL=400kHz
Standby Current ISB - 10 100 µA VCC=5.5V, SDA=SCL=VCC,VCLK=GND *1

Note: This IC is not designed to be radiation-resistant
*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the VCLK pin.
After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the operating current flows.
Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.

●Electrical characteristics - AC (Unless otherwise specified, Ta=-40℃～+85℃,V

Fast-mode

CC=2.5V～5.5V

Parameter Symbol

V

CC=2.5V～5.5V)

Standard-mode

VCC=2.5V～5.5V

Unit

Min. Typ. Max. Min. Typ. Max.

Clock Frequency fSCL - - 400 - - 100 kHz

Data Clock High Period tHIGH 0.6 - - 4.0 - -

Data Clock Low Period tLOW 1.3 - - 4.7 - - µs

SDA and SCL Rise Time tR - - 0.3 - - 1.0 µs

SDA and SCL Fall Time tF - - 0.3 - - 0.3 µs

Start Condition Hold Time tHD:STA 0.6 - - 4.0 - - µs

Start Condition Setup Time tSU:STA 0.6 - - 4.7 - - µs

Input Data Hold Time tHD:DAT 0 - - 0 - - ns

Input Data Setup Time tSU:DAT 100 - - 250 - - ns

Output Data Delay Time(SCL) tPD - - 0.9 - - 3.5 µs

Stop Condition Setup Time tSU:STO 0.6 - - 4.0 - - µs

Bus Free Time tBUF 1.3 - - 4.7 - - µs

Write Cycle Time tWR - - 10 - - 10 ms

Noise Spike Width (SDA and SCL) tI - - 0.1 - - 0.1 µs

AC OPERATING CHARACTERISTICS (Transmit-Only Mode)

Output Data Delay Time(VCLK) tVPD - - 1.0 - - 2.0 µs

VCLK High Period tVHIGH 0.6 - - 4.0 - - µs

VCLK Low Period tVLOW 1.3 - - 4.7 - - µs

VCLK Setup Time tVSU 0 - - 0 - - µs

VCLK Hold Time tVHD 0.6 - - 4.0 - - µs

Mode Transition Time tVHZ - - 0.5 - - 1.0 µs

Transmit-Only Powerup Time tVPU 0 - - 0 - - µs

Noise Spike Width (VCLK) tVI - - 0.1 - - 0.1 µs

µs

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2/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W

●Block diagram

1

N.C.

1 Kbit EEPROM ARRAY

Technical Note

8

VCC

N.C.

N.C.

GND

●Pin layout diagram

7bit

2

3

ADDRESS

DECODER

CONTROL LOGIC

HIGH VOLTAGE VCC LEVEL DETECT

7bit

START STOP

SLAVE・WORD

ADDRESS REGISTER

DATA

REGISTER

ACK

Fig.1 Block Diagram

VCC VCLK

(

入力)

BR24C21

SCL SDA

BR24C21F

BR24C21FJ

BR24C21FV

N.C.

N.C.

GND N.C.

Fig.2 Pin Layout

Pin Name I/O Functions

VCC - Power Supply

GND - Ground (0V)

N.C. - No Connection
SCL IN Serial Clock Input for Bi-directional Mode

SDA IN/OUT

VCLK IN

*1 An open drain output requires a pull-up resistor.

Slave and Word Address,
Serial Data Input, Serial Data Output
Clock Input (Transmit-Only Mode)
Write Enable (Bi-directional Mode)

8bit

7

VCLK

6

SCL

5 4

SDA

*1

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3/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,

A

BU9882-W,BU9882F-W,BU9882FV-W

Technical Note

●Synchronous data timing

t

tR tF

HIGH

SCL

SDA
(IN)

SDA
(OUT)

tHD:STA

t

t

BUF

t

SU

:DAT

t

LOW

PD

t

HD

:DAT

SCL

SD

D0 ACK

WRITE DATA(n)

tWR

STOP CONDI TI ON START CONDI TION

Fig.4 Write Cycle Timing

START BIT

STOP BIT

SCL

tSU:STA

SDA

tHD:STA

Fig.3 Synchronous Data Timing

START BIT

t

SU:STO

STOP BIT

SCL

SDA

VCLK

・SDA data is latched into the chip at the rising edge of the SCL clock.

・Output data toggles at the falling edge of the SCL clock.

t

VSU

Fig.5 Write Enable Timing

WRITE COMMAND

●Transmit-only mode
・After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock

to the VCLK pin.

・When the power is on, the SCL pin needs to be set to VCC(High level).
・SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After

power on, the output data is as follows:

00h address data → 01h address data → 02h address data →

…

The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)

・In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)
・The read operation is in Transmit-Only Mode and can be started after the power is stabilized.

Vcc

SCL

VCLK

ｔVPU

SDA

Fig.6 Transmit Only Mode

9

101

D7 D6 D5 D4 D3

00h ADDRESS DATA

VCLK

SDA

tVPD

ADDRESS n
DATA

D0D1 D7 D6

Fig.7 Null Bit

NULL BIT
DATA=1

tVHIGH tVLOW

ADDRESS n+1
DATA

t

VHD

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4/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W

Technical Note

●Bi-directional mode

○Bi-directional Mode and Recovery Function

・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low

transition at the SCL pin, while the state of SDA is at high-impedance.

・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK

counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode
(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal
to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.

・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional

Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down
way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does
Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert

not respond with an

to Transmit-Only Mode for

is the only

Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,
it is possible to revert to Transmit-Only Mode.

・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.

ＭＯＤＥ

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

Transmit-only

Trans mit -on ly

Bi-directional

Bi-directional

Transition Mode with possibility

Transition Mode with possibility to

to retune to Transmit-Only Mode

return to Transmit-Only Mode

２１

３ ４

ｔＶＨＺ

Fig.8 Recovery Mode

１２７

１２８

１２９

Transmit-Only

Transmit-Only

ADDRESS 00h

ADDRESS 00h

Ｄ７

Ｄ６Ｄ５Ｄ４

ＭＯＤＥ

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

Transmit-oOnly

Trans mit -on ly

ｔＶＨＺ

Bi-directional

Bi-directional

Transition Mode with possibility

Transition Mode with possibility to

to retune to Transmit-Only Mode

return to Transmit-Only Mode

ｎ＜１２８

２１ｎ

１０ １ ＊＊＊０

Fig.9 Mode Change

○Bi-directional Mode

START Condition

・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.
・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to

any commands until this condition has been met.
(See Fig. 3 Synchronous Data Timing)

STOP Condition

・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.
・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.
・The STOP condition is also used to place the device into standby power mode after read sequences.
・A STOP condition can only be issued after the transmitting device has released the bus.

(See Fig.3 Synchronous Data Timing)

Device Addressing

・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most

significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as
“1010.”

・The next three bits of the slave address are inconsequential.
・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.

When set to “0”, a WRITE operation is initiated.

R/W set to "0"
R/W set to "1"

・ ・ ・ ・ ・ ・ ・ ・ WRITE (This bit is also set to "0" for random read operation)
・ ・ ・ ・ ・ ・ ・ ・ READ

1010

＊ ＊ ＊

_

R/W

＊：Don’t care
○Write Protect Function
・Write Enable (VCLK)

When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting
VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.
(See Fig.5 Write Enable Timing)
Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.

Bi-directional
parmanently

ＡＣＫ

Ｒ/ＷＳ

*Don’t care

Bi-directional
parmanently

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5/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,

S

R

S

P

S

E

S

R

S

)

E

)

BU9882-W,BU9882F-W,BU9882FV-W

●Bidirectional mode command
○Byte Write

When the Master generates a STOP condition, the BR24C21/F/FJ/FV begins the internal write cycle to the nonvolatile array.

DA

LINE

VCLK

T
A

SLAVE

R

ADDRESS

T

○Page Write

If the Master transmits the next data instead of generating a STOP condition during the byte write cycle, the
BR24C21/F/FJ/FV transfers from byte write function to page write function. After receipt of each word, the three lower
order address bits are internally incremented by one, while the high order four bits of the word address remains
constant.
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll
over,” and the previous transmitted data will be overwritten.

SDA
LINE

T
A
R
T

1

SLAV

ADDRESS

1

0 0

VCLK

○Current Read

The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,
incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will
access data from address “n+1” and increment the current address counter. If the last accessed address is address
”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an
Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of

At this point, the device discontinues transmission.

data.
(See Fig.14 Sequential Read Cycle Timing)

SDA
LINE

S
T
A
R
T

W

R

I
T
E

* *

*

WORD

ADDRESS

WA

*

6

WA

D7 1 1 0 0

0

A
C

/

K

W

A
C
K

Fig.10 Byte Write Cycle Timing

W
R

I

T

＊

＊ ＊

W

WORD

ADDRESS

WA

*

6

A

/

C
K

WA

0

DATA(n

A
C
K

Fig.11 Page Write Cycle Timing

R

SLAVE

ADRESS

E
A
D

＊ ＊

＊

A

R

C

/

K

W

DATA

D7 1 1 0 0

*:Don’tcare

Fig.12 Current Read Cycle Timing

DATA

D0

D7 D0

A
C
K

D0

*:Don’t care

DATA(n +7

*:Don’t care

S
T
O
P

D0

A
C
K

Technical Note

T
O

A
C
K

T
O
P

A
C
K

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6/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W

○Random Read

The Random read operation allows the Master to access any memory location. This operation involves a two-step
process. First, the Master issues a Write command that includes the START condition and the Slave address field
(with R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address
counter of the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the
Master, the Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.”
The device will respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the
Master does not acknowledge the transmission but does generate the STOP condition, the IC will discontinue
transmission.

SDA
LINE

S
T
A
R
T

10 0

SLAVE

ADDRESS

1* * *

W
R

I
T
E

R

/
W

Fig.13 Random Read Cycle Timing

○Sequential Read

･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read

operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits
in the address counter are incremented, allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.

･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device

discontinues transmission.

･The sequential Read operation can be performed with both Current Read and Random Read.

SDA
LINE

S
T

A

SLAVE

R

ADDRESS

T

10 0

R
E
A
D

1* * * D0 D7 D0 D7

R

/

W

Fig.14 Sequential Read Cycle Timing

*

A
C
K

A
C
K

WORD

ADDRESS（ｎ）

WA

6

DATA(n)

(Current Read)

WA

0

S

T
A
R
T

A
C

K

A
C
K

SLAVE

ADDRESS

10 01* *

R
E
A
D

*

D0

R
/
W

DATA(n)

D7

A
C
K

DATA(n+x)

A
C
K

*:Don’t care

*:Don’t care

Technical Note

S
T
O
P

A
C
K

S
T
O
P

A
C
K

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7/22

© 2011 ROHM Co., Ltd. All rights reserved.

2011.08 - Rev.C