A
High Reliability Series Serial EEPROMs
WL-CSP EEPROM family
I2C BUS
BU9880GUL-W
●Description
BU9880GUL-W is a serial EEPROM of I
●Features
1) Completely conforming to the world standard I
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.7 ~ 5.5V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.7 ~ 5.5V
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write operation (5.0V) : 0.5mA (Typ.)
At read operation (5.0V) : 0.2mA (Typ.)
At standby operation (5.0V) : 0.1µA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) Compact package
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●Page write
2
C BUS interface method.
2
C BUS.
No.10001EAT19
Product number Number of pages
BU9880GUL-W 32Byte
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Ratings Unit
Impressed voltage VCC -0.3 ~ 6.5 V
Permissible dissipation Pd 220 *1 mW
Storage temperature range Tstg -65 ~ 125 ℃
Action temperature range Topr -40 ~ 85 ℃
Terminal voltage － -0.3 ~ VCC+1.0 *2 V
*1 When using at Ta=25℃or higher, 2.2mW to be reduced per 1℃
*2 The Max value of Terminal Voltage is not over 6.5V.
●Recommended operating conditions
Parameter Symbol Ratings Unit
Power source voltage VCC 1.7 ~ 5.5
Input voltage VIN 0 ~ VCC
V
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1/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
●Memory cell characteristics (Ta=25℃, Vcc=1.7~5.5V)
Parameter
Min. Typ. Max.
Limits
Number of data rewrite times *1 1,000,000 － － Times
Data hold years *1 40 － － Years
*1 Not 100% TESTED
●Electrical characteristics (Unless otherwise specified Ta=-40~85℃, V
Parameter Symbol
Min Typ. Max.
Limits
Technical Note
Unit
CC=1.7~5.5V)
Unit Condition
"H" Input Voltage1 V
"L" Input Voltage1 V
"L" Output Voltage1 V
"L" Output Voltage2 V
0.7V
IH1
－0.3 － 0.3Vcc V
IL1
－ － 0.4 V IOL=3.0mA, 2.5V≦VCC≦5.5V(SDA)
OL1
－ － 0.2 V IOL=0.7mA, 1.7V≦VCC＜2.5V(SDA)
OL2
－ VCC+1.0 V
CC
Input Leakage Current ILI －1 － 1 µA VIN=0V ~ VCC
Output Leakage Current ILO －1 － 1 µA V
I
CC1
－ － 2.0 mA
Current consumption
at action
I
－ － 0.5 mA
CC2
=0V ~ VCC(SDA)
OUT
VCC=5.5V , f
=400kHz, tWR=5ms
SCL
Byte Write, Page Write
V
=5.5V , f
CC
=400kHz
SCL
Random read, Current read,
Sequential read
Standby Current ISB － － 2.0 µA VCC=5.5V , SDA・SCL=VCC, WP=GND
○This product is not designed for protection against radioactive rays.
●Action timing characteristics(Unless otherwise specified Ta=-40 ~ 85℃､V
Parameter Symbol
=1.7 ~ 5.5V)
CC
Limits
Min. Typ. Max.
Unit
SCL Frequency fSCL － － 400 kHz
Data clock "High" time tHIGH 0.6 － － µs
Data clock "Low" time tLOW 1.2 － － µs
SDA, SCL rise time *1 tR － － 0.3 µs
SDA, SCL fall time *1 tF － － 0.3 µs
Start condition hold time tHD:STA 0.6 － － µs
Start condition setup time tSU:STA 0.6 － － µs
Input data hold time tHD:DAT 0 － － ns
Input data setup time tSU:DAT 100 － － ns
Output data delay time tPD 0.1 － 0.9 µs
Output data hold time tDH 0.1 － － µs
Stop condition data setup time tSU:STO 0.6 － － µs
Bus release time before transfer start tBUF 1.2 － － µs
Internal write cycle time tWR － － 5 ms
Noise removal valid period (SDA,SCL terminal) tI － － 0.1 µs
WP hold time tHD:WP 0 － － ns
WP setup time tSU:WP 0.1 － － µs
WP valid time tHIGH:WP 1.0 － － µs
*1 : Not 100% TESTED
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2/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
A
A
A
A
A2 A1 A
A
g
g
A
●Sync data input/output timing
SCL
SDA
(Input)
SDA
(Output)
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tHD :STA tHD :DAT
tBUF
Fig.1-(a) Sync data input / output timing
SCL
tSU :STA tSU :STO tHD :STA
SDA
START BIT
Fig.1-(b) Start - stop bit timing
SCL
SDA
WRITE DATA(n)
D0
ACK
STOP
CONDITION
Fig.1-(c) Write cycle timing
●Block diagram
1
0
2
3
GND
tSU :DAT
tLOW
tPD tDH
tWR
CONDITION
13bit
dddress
decoder
Control circuit
High voltage
generating circuit
tHIGH
tR tF
STOP BIT
START
64Kbit EEPROM array
13bit
START STOP
Power source
volta
Fig.2 Block diagram
SCL
SD
WP
SCL
SDA
WP
Slave - word
address register
e detection
Technical Note
DATA(1)
D1 D0ACK
tSU：WP
Fig.1-(d) WP timing at write execution
DATA(1)
D1 D0
○At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
Fig.1-(e) WP timing at write cancel
8bit
Data
re
CK
CK
ister
DATA(n)
tHIGH:WP
DATA(n)
8
7
6
5 4
CK
Stop condition
Vcc
WP
SCL
SDA
CK
tWR
tHD：WP
tWR
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3/16
© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
A
●Pin assignment and description
C
VSS
A2
A1
B
SDA
A0
SCL WP VCC
1
23
Fig.3 BU9880GUL-W(bottom view)
Land No. Terminal name Input / output Function
C3 A1 Input Slave address
Technical Note
C2 A2 Input Slave address
C1 GND - Reference voltage of all input / output
B3 A0 Input Slave address
B1 SDA Input / output Slave and word address, Serial data input serial data output
A3 Vcc - Power Supply
A2 WP Input Write protect terminal
A1 SCL Input Serial clock input
●Characteristic data (The following values are Typ. ones.)
6
(V)
L OUTPUT VOLTAGE : V
Ta=-40℃
5
Ta=25℃
(V)
IH
Ta=85℃
4
3
2
H INPUT VOLTAGE : V
1
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.4 'H' input voltage V
(A0,A1,A2,SCL,SDA,W P)
1
0.8
OL
Ta=-40℃
0.6
Ta=25℃
Ta=85℃
0.4
0.2
0
0123456
L OUTPUT CURRENT : I
Fig.7 'L' output voltage VOL-IOL(Vcc=2.5V)
SPEC
SPEC
IH
(mA)
OL
6
5
Ta=-40℃
(V)
Ta=25℃
IL
Ta=85℃
4
3
2
L INPUT VOLTAGE : V
1
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.5 'L' input voltage V
1.2
(uA)
LI
0.8
0.6
0.4
0.2
INPUT LEAK CURRENT : I
1
Ta=-40℃
Ta=25℃
Ta=85℃
0
0123456
SUPPLYVOLTAGE : Vcc(V)
Fig.8 Input leak current I
SPEC
(A0,A1,A2,SCL,SDA,WP)
SPEC
IL
(A0,A1,A2,SCL,WP)
0.6
0.5
(V)
OL
0.4
0.3
0.2
0.1
L OUTPUT VOLTAGE : V
0
1.2
(uA)
LO
0.8
0.6
0.4
0.2
OUTPUT LEAK CURRENT : I
LI
SPEC
012345678
L OUTPUT CURRENT : I
Fig.6 'L' output voltage VOL-IOL(Vcc=1.7V)
1
Ta=-40℃
Ta=25℃
Ta=85℃
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Output leak current I
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
(mA)
OL
(SDA)
LO
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
●Characteristic data (The following values are Typ. ones.)
2.5
2
1.5
Ta=-40℃
Ta=25℃
1
Ta=85℃
AT WRITING : Icc1(mA)
0.5
CURRENT CONSUMPTION
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.10 Current consumption at WRITE operation ICC1
10000
SPEC
(fscl=400kHz)
0.6
0.5
0.4
0.3
0.2
AT READING : Icc2(mA)
0.1
CURRENT CONSUMPTION
Fig.11 Current consumption at READ operation I
Ta=-40℃
Ta=25℃
Ta=85℃
0
0123456
5
1000
100
10
1
SCL FREQUENCY : fｓｃｌ（ｋHZ）
0.1
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.13 SCL frequency f
(us)
5
HD : STA
4
3
Ta=-40℃
2
Ta=25℃
Ta=85℃
1
0
START CONDITION HOLD TIME : t
0123456
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SCL
4
(uA)
HIGH
3
Ta=-40℃
Ta=25℃
2
Ta=85℃
1
DATA CLK H TIME : t
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.14 Data clock High Period t
5.9
4.9
3.9
2.9
Ta=-40℃
Ta=25℃
1.9
Ta=85℃
START CONDITION
0.9
SET UP TIME : tSU:STA(uA)
-0.1
0123456
Fig.16 Start Condition Hold Time t
HD : STA
Fig.17 Start Condition Setup Time t
50
(ns)
0
HD :DAT
-50
-100
-150
INPUT DATA HOLD TIME : t
-200
0123456
Fig.19 Input Data Hold Time
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
ｔ
HD : DAT
(LOW）
300
(ns)
200
SU: DAT
100
0
-100
-200
INPUT DATA SET UP TIME : t
0123456
Fig.20 Input Data Setup Time
(us)
4
Ta=-40℃
PD
Ta=25℃
3
Ta=85℃
2
SPEC
(us)
PD
4
3
2
Ta=-40℃
Ta=25℃
Ta=85℃
1
1
0
OUTPUT DATA DELAY TIME : t
0123456
SUPPLY VOLTAGE : Vcc(V)
' Data output delay time
Fig.22 'L
tPD0
OUTPUT DATA DELAY TIME : t
0
0123456
Fig.23 'H' Data output delay time
SPEC
SUPPLY VOLTAGE : Vcc(V)
(fscl=400kHz)
SPEC
SPEC
SUPPLY VOLTAGE : Vcc(V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
ｔ
SPEC
SUPPLY VOLTAGE : Vcc(V)
SU: DAT
SU : STA
(HIGH)
ｔPD1
HIGH
Technical Note
2.5
SPEC
SPEC
SPEC
SPEC
SPEC
HD : DAT
SU : DAT
SB
LOW
（HIGH）
(LOW)
ｔ
BUF
2
(uA)
SB
1.5
Ta=-40℃
1
Ta=25℃
Ta=85℃
0.5
STANBY CURRENT : I
0
0123456
SUPPLY VOLTAGE : Vcc(V)
2
CC
(ns)
HD: STA
INPUT DATA HOLD TIME : t
(ns)
SU : DAT
INPUT DATA SET UP TIME : t
Fig.12 Stanby operation I
5
(us)
4
LOW
3
Ta=-40℃
Ta=25℃
2
Ta=85℃
1
ＤＡＴＡ CLK L TIME : t
0
0123456
SUPPLY VOLTAGE : Vcc（V）
Fig.15 Data clock Low Period t
50
0
-50
Ta=-40℃
-100
Ta=25℃
Ta=85℃
-150
-200
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.18 Input Data Hold Time t
300
200
100
0
Ta=-40℃
Ta=25℃
-100
Ta=85℃
-200
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.21 Input Data setup time t
5
(us)
Ta=-40℃
BUF
4
Ta=25℃
Ta=85℃
3
2
BUS OPEN TIME
1
BEFORE TRANSMISSION : t
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.24 BUS open time before transmission
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
●Characteristic data (The following values are Typ. ones.)
6
5
(ms)
WR
4
3
2
INTERNAL WRITING
CYCLE TIME : t
1
0
0123456
Fig.25 Internal writing cycle time
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
ｔ
WR
1
0.8
Ta=-40℃
(SCL H) (us)
Ta=25℃
l
0.6
Ta=85℃
0.4
NOISE REDUCTION
0.2
EFECTIVE TIME : t
0
0123456
SUPPLY VOLTAG E : Vcc(V)
Fig.26 Noise reduction efection time
0.6
0.5
0.4
(SDA H)(us)
l
0.3
0.2
NOISE REDUCTION
0.1
EFECTIVE TIME : t
0
0246
SUPPLY VOLATGE : Vcc(V)
Fig.28 Noise resuction efecctive time
1.2
(us)
1
HIGH : WP
0.8
0.6
0.4
Ta=-40℃
Ta=25℃
0.2
WP EFFECTIVE TIME : t
Ta=85℃
0
0123456
SUPPLYVOLTAGE : Vcc(V)
Fig.31 WP efective time
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
t
HIGH : WP
ｔ
（SDA H）
ｌ
0.6
0.5
0.4
(SAD L)(us)
l
0.3
Ta=-40℃
Ta=25℃
0.2
NOISE REDUCTION
Fig.29 Noise reduction efective time t
Ta=85℃
0.1
EFFECTIVE TIME : t
0
0123456
SUPPLY VOLTAGE : Vcc(V)
SPEC
SPEC
（SCL H）
t
l
SDA L
（
l
Technical Note
0.6
Ta=-40℃
0.5
Ta=25℃
Ta=85℃
0.4
(SCL L)(us)
l
0.3
0.2
NOISE REDUCTION
0.1
EFECTIVE TIME : t
0
0123456
Fig.27 Noise reduction efective time
0.2
0.1
(us)
0
SU : WP
-0.1
-0.2
-0.3
-0.4
WP SET UP TIME : t
-0.5
-0.6
0123456
）
SPEC
SUPPLY VOLTAGE : Vcc(V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
Fig.30 WP setup time
t
SU : WP
t
（SCL L）
l
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
A
ACK
A
Technical Note
●I2C BUS communication
○I2C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
I
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7 1-7
SCL
P
S
DDRESS START R/W ACK
condition condition
89 89 89
DATA DATA
1-7
CK STOP
Fig.32 Data transfer timing
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・The most insignificant bit (
W/R --- WRITE/READ ) of slave address is used for designating write or read action,
and is as shown below.
Setting
Setting
W/R to 0 --- write (setting 0 to word address setting of random read)
W/R to 1 --- read
Type Slave address
BU9880GUL-W 1 0 1 0 0 0 0
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© 2010 ROHM Co., Ltd. All rights reserved.
W/R
2010.11 - Rev.
BU9880GUL-W
A
Technical Note
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.Up to 32 arbitrary bytes can be written.
SDA
LINE
S
T
A
R
T
1 1 0 0
SLAVE
ADDRESS
W
R
I
1st WORD
T
ADDRESS
E
＊ WA
＊
W
＊
12
R
A
/
C
K
0 0
0 D0
2nd WORD
ADDRESS
WA
0
A
C
K
A
C
K
DATA
D7
S
T
O
P
A
C
K
Fig.33 Byte write cycle
SDA
LINE
S
T
A
SLAVE
R
ADDRESS
T
0
10 D0
1
W
R
I
1st WORD
T
ADDRESS(n)
E
WA
＊
0 0
0
＊ ＊
12
A
R
C
/
K
W
A
C
K
2nd WORD
ADDRESS(n)
WA
DATA(n)
0
A
C
K
D0 D7
A
C
K
DATA(n+31)
S
T
O
P
A
C
K
Fig.34 Page write cycle
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 32 bytes.
(Refer to "Internal address increment of "Notes on page write cycle" in P9/16.)
・As for page write cycle of BU9880GUL-W , after the significant 7 bits of word address, are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32
bytes can be written.
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
○Notes on write cycle continuous input
SDA
LINE
S
T
A
R
ADDRESS
T
10 0 1
SLAVE
W
R
I
WORD
T
ADDRESS(n)
E
WA
A1 A2
A0
7
A
R
C
/
K
W
WA
0
DATA(n)
A
C
K
DATA(n+31)
D0 D7 D0
A
C
K
A
C
K
Fig.35 Page write cycle
○Notes on page write cycle ○Internal address increment
List of numbers of page write
Product number Number of pages
BU9880GUL-W 32Byte
The above numbers are maximum bytes for respective
types. Any bytes below these can be written.
In the case of BU9880GUL-W, 1 page = 32bytes,
but the page write cycle write time is 5ms at maximum
for 32byte bulk write. It does not stand 5ms
at maximum × 32byte = 160ms(Max.).
1Eh
Page write mode
WA12 ----- WA5 WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0 0
0 ----- 0 0 0 0 0 1
0 ----- 0 0 0 0 1 0
0 ----- 0 1 1 1 0 1
0 ----- 0 1 1 1 1 0
0 ----- 0 0 0 0 0 0
---------
For example, when it is started from address 1Eh,
therefore, increment is made as below,
1Eh→1Fh→00h→01h･･･
* 1Eh･･･16 in hexadecimal, therefore,
00011110 becomes a binary number.
Significant bit is fixed.
No digit up
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level),
data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level.
Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be
prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
S
T
O
P
Technical Note
At STOP (stop bit)
write starts.
1 100
Next command
tWR(maximum：5ms)
Command is not accepted
for this period.
---------
Iincrement
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
A
A
(n)
)
Technical Note
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
SDA
LINE
S
T
A
R
ADDRESS
T
10 0 10 0
SLAVE
SDA
LINE
S
T
A
R
T
10 0
SLAVE
ADDRESS
1
0
SD
LINE
0
W
R
I
T
E
R
/
W
ADDRESS(n)
＊
＊
A
C
K
1st WORD
WA
＊
12
ADDRESS(n)
A
C
K
2nd WORD
Fig.36 Random read cycle
S
T
A
SLAVE
R
ADDRESS
T
10 0 1 0 D0 D7
R
E
A
D
0
0
A
R
C
/
K
W
Fig.37 Current read cycle
R
E
A
D
0
0
D7 D0
DATA
D0
WA
0
A
C
K
DATA(n)
S
T
A
R
T
100
SLAVE
ADDRESS
1
A2
S
T
O
P
A
C
K
D7
R
E
A
DATA(n)
D
D7 D0
A1
A0
R
A
/
C
W
K
DATA(n+x
S
T
O
P
A
C
K
S
T
O
P
It is necessary to input 'H'
to the last ACK.
It is necessary to input 'H'
to the last ACK.
A
Fig.38 Sequential read cycle (in the case of current read cycle)
R
C
/
K
W
A
C
K
A
C
K
A
C
K
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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2010.11 - Rev.
BU9880GUL-W
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A
A
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Technical Note
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.39(a), Fig.39(b), Fig.39(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level)
may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Dummy clock×14
Star t×2
SCL
SDA
SCL
SDA
2 13
1
14
Fig.39-(a) The case of 14 Dummy clock + START + START+ command input
Star t
Dummy clock×9
1
2
8
Star t
9
Fig.39-(b) The case of START+9 Dummy clock + START + command input
Normal command
Normal command
Normal command
Normal command
Star t×9
SCL
SDA
1 2 3 8 9 7
Normal command
Normal command
Fig.39-(c) START × 9 + command input
* Start command from START input.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously,
W/R = 0, when to carry out current read cycle after write, slave address W/R = 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data so forth.
First write command
S
T
A
Write command
R
T
S
S
T
T
O
P
Slave
A
address
R
T
Second write command
During internal write,
ACK = HIGH is sent back.
S
T
A
R
T
Slave
address
C
K
H
tWR
C
…
K
H
…
S
T
A
R
T
Slave
address
t
WR
C
K
H
S
T
A
R
T
Slave
address
Word
C
K
address
L
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
C
Data
K
L
S
C
T
K
O
L
P
Fig.40 Case to continuously write by acknowledge polling
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2010.11 - Rev.
BU9880GUL-W
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Technical Note
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.41.) After
execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
SDA
S
T
A
R
T
WP
・Rise of D0 taken clock
SCL
SDA
A
Slave
C
address
K
L
D0
D1
Enlarged view
Word
address
WP cancel invalid area
A
C
K
L
ACK
D7 D6
D5
D2
D0
D1
D3
D4
WP cancel valid area
Data is not written.
Fig.41 WP valid timing
SCL
SDA
A
C
K
L
D0
Data
・Rise of SDA
ACK
Enlarged view
S
A
T
C
O
K
P
L
Write forced end
Data not guaranteed
tWR
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to
Fig. 42.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and
stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is
cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting
address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read
cycle in succession, carry out random read cycle.
SCL
SDA
1
0 0
1
Start condition
Stop condition
Fig.42 Case of cancel by start, stop condition during slave address input
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.11 - Rev.
BU9880GUL-W
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Technical Note
●Cautions on microcontroller connection
○Rs
2
C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
In I
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
CK
R
S
SCL
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Fig.43 I/O circuit diagram
Over current flows to SDA line by 'H'
output of microcontroller and 'L' output
of EEPROM.
Fig.44 Input/output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2) The bus electric potential
should sufficiently secure the input 'L' level (V
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
○
) of microcontroller including recommended noise margin 0.1Vcc.
IL
(V
CC－VOL)×RS
S
R
IOL
VCC
RPU=10ｋΩ
VOL
∴ R
Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=10kΩ,
RPU+RS
S ≦
+VOL+0.1VCC≦VIL
V
IL－VOL－0.1VCC
1.1VCC－VIL
× RPU
0.3×3－0.4－0.1×3
S ≦
1.1×3－0.3×3
≦ 0.835［kΩ］
× 10×10
VIL
Microcontroller
Bus line
capacity CBUS
EEPROM
from(2), R
Fig.45 I/O circuit diagram
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
CC
R
S
Over currentⅠ
'H' output
RPU=10Ω
'L' output
V
∴ RS ≧
≦ I
S
R
V
CC
I
Example）When VCC=3V, I=10mA
3
S ≧
Microcontroller
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13/16
© 2010 ROHM Co., Ltd. All rights reserved.
Fig.46 I/O circuit diagram
EEPROM
R
3
10×10
-3
2010.11 - Rev.
BU9880GUL-W
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Technical Note
●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, SDA)
Fig.47 Input pin circuit diagram
○Input/Output (SDA)
Fig.48 Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC
tR
Recommended conditions of t
, t
, Vbot
R
OFF
tOF F
0
Fig.49 Rise waveform diagram
Vbot
tR t
Vbot
OFF
10ms or below 10ms or higher 0.3V or below
100ms or below 10ms or higher 0.2V or below
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
SCL
tLOW
SDA
After Vcc becomes st able
tSU:DAT tDH
Fig.50 When SCL='H' and SDA='L'
After Vcc becomes stable
tSU:DAT
Fig.51 When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P26).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
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●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
noise countermeasures
●V
CC
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Technical Note
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2010.11 - Rev.
BU9880GUL-W
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●Ordering part number
B U 9 8 8 0 G U L - W E 2
Technical Note
Part No. Part No. Package
VCSP50L1
(BU9880GUL-W)
1PIN MARK
8-φ0.25±0.05
0.05
(φ0.15)INDEX POST
0.49±0.05
1.59±0.05
1.98±0.05
0.55MAX
0.1±0.05
S
0.06 S
BA
A
C
B
A
1
23
P=0.5×2
0.295±0.05
B
P=0.5×2
(Unit : mm)
GUL : VCSP50L1
<Tape and Reel information>
Embossed carrier tape(heat sealing method)Tape
Quantity
Direction
of feed
3000pcs
E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
W-CELL Packaging and forming specification
E2: Embossed tape and reel
1pin
Order quantity needs to be multiple of the minimum quantity.
∗
Direction of feed
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2010.11 - Rev.
Notes
No copying or reproduction of this document, in par t or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
Notice
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, of ce-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
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shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
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