1) Completely conforming to the world standard I
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.7 ~ 5.5V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.7 ~ 5.5V
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write operation (5.0V) : 0.5mA (Typ.)
At read operation (5.0V) : 0.2mA (Typ.)
At standby operation (5.0V) : 0.1µA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) Compact package
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●Page write
2
C BUS interface method.
2
C BUS.
No.10001EAT19
Product number Number of pages
BU9880GUL-W 32Byte
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Ratings Unit
Impressed voltage VCC -0.3 ~ 6.5 V
Permissible dissipation Pd 220 *1 mW
Storage temperature range Tstg -65 ~ 125 ℃
Action temperature range Topr -40 ~ 85 ℃
Terminal voltage --0.3 ~ VCC+1.0 *2 V
*1 When using at Ta=25℃or higher, 2.2mW to be reduced per 1℃
*2 The Max value of Terminal Voltage is not over 6.5V.
SCL Frequency fSCL - - 400 kHz
Data clock "High" time tHIGH 0.6 - - µs
Data clock "Low" time tLOW 1.2 - - µs
SDA, SCL rise time *1 tR - - 0.3 µs
SDA, SCL fall time *1 tF - - 0.3 µs
Start condition hold time tHD:STA 0.6 - - µs
Start condition setup time tSU:STA 0.6 - - µs
Input data hold time tHD:DAT 0 - - ns
Input data setup time tSU:DAT 100 - - ns
Output data delay time tPD 0.1 - 0.9 µs
Output data hold time tDH 0.1 - - µs
Stop condition data setup time tSU:STO 0.6 - - µs
Bus release time before transfer start tBUF 1.2 - - µs
Internal write cycle time tWR - - 5 ms
Noise removal valid period (SDA,SCL terminal) tI - - 0.1 µs
WP hold time tHD:WP 0 - - ns
WP setup time tSU:WP 0.1 - - µs
WP valid time tHIGH:WP 1.0 - - µs
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tHD:STAtHD :DAT
tBUF
Fig.1-(a) Sync data input / output timing
SCL
tSU:STAtSU:STOtHD:STA
SDA
START BIT
Fig.1-(b) Start - stop bit timing
SCL
SDA
WRITE DATA(n)
D0
ACK
STOP
CONDITION
Fig.1-(c) Write cycle timing
●Block diagram
1
0
2
3
GND
tSU :DAT
tLOW
tPDtDH
tWR
CONDITION
13bit
dddress
decoder
Control circuit
High voltage
generating circuit
tHIGH
tRtF
STOP BIT
START
64Kbit EEPROM array
13bit
STARTSTOP
Power source
volta
Fig.2 Block diagram
SCL
SD
WP
SCL
SDA
WP
Slave - word
address register
e detection
Technical Note
DATA(1)
D1D0ACK
tSU:WP
Fig.1-(d) WP timing at write execution
DATA(1)
D1 D0
○At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.