ROHM BU9414FV Technical data

A
32bit Audio DSP
BU9414FV
General Description
This LSI is the digital sound processor which made the use digital signal processing for FPD TVs. DSP of ROHM original is used for the TV sound processor unit, and it excels in cost performance. There are two digital input systems. An output is a digital output corresponding to 2.1ch.
Features
Digital Signal Processor unit
Word length: 32bit (Data RAM) The fastest machine cycle: 40.7ns (512fs, fs = 48kHz) Multiplier: 32 x 24 → 56bit
Adder: 32 + 32 → 32bit Data RAM: 256 x 32bit Coefficient RAM: 128 x 24bit Sampling frequency: fs = 48kHz Master clock : 512fs (It is a slave to 256fs of fs = 48kHz, 44.1 kHz, and 32 kHz)
Digital signal input (Stereo 2 lines): 16/20/24bit(I2S, Left-Justified, Right-Justified) Digital signal output (Stereo 2 lines): 16/20/24bit(I2S, Left-Justified, Right-Justified, S/PDIF)
The sound signal processing function for FPD TVs
Pre-Scaler, DC cut HPF, Channel Mixer, P TREBLE, Pseudo BASS, Surround, P Master Volume, L/R balance, Post-Scaler, Output signal clipper (P2Volume, P2Bass, and P2Treble are the sound effect functions of ROHM original.)
Applications
Flat Panel TVs (LCD, Plasma)
2
Volume(Perfect Pure Volume), BASS, MIDDLE,
2
Bass, P2Treble, 7Band Parametric EQ,
No.12083EAT04
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Absolute maximum ratingTa=25°C
Item Symbol Rating Unit Power-supply voltage VDD 4.5 V Allowable dissipation Pd 700 (*1) mW operating temperature range T Storage temperature range T
-25+85 °C
opr
-55+125 °C
stg
*1 7mW is decreased for 1°C when using it with Ta=25°C or more.
*Operation can’t be guaranteed.
Operating conditionTa =- 25+85°C
Item Symbol Rating Unit Power-supply voltage VDD 3.03.6 V
* It isn’t Radiation-proof designed for the product.
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Electric characteristic(Digital serial)
V
=3.3V unless specified, Ta=25°C
DD
Rating value
Unit Terms Adaptive
terminal
V
=03.3V
IN
*1
Hysteresis
Input voltage
Item Symbol
H Level voltage VIH 2.5 - - V *1,2,3 L Level voltage VIL - - 0.8 V *1,2,3
Min. Standard Max.
Input current II -1 - +1 µA
Pull-up resistor input L current IIL -150 -100 -50 µA VIN=0V *2
Pull-down resistor input H current IIH 35 70 105 µA VIN=3.3V *3
Output voltage
H Level voltage V L Level voltage VOL - - 0.55 V IO=0.6mA *4
2.75 - - V IO=-0.6mA *4
OH
SDA terminal Output voltage
L Level voltage V
- - 0.4 V IO=3mA *5
OL
Adaptive terminal *1 CMOS hysteresis input terminal SCLI(8pin), SDAI(9pin), MODE(20pin) *2 Pull-up resistor built-in CMOS hysteresis input terminal LRCKI(2pin), SDATA1(3pin), SDATA2(4pin), MCLK(39pin), BCKI(40pin) *3 Pull-down resistor built-in CMOS hysteresis input terminal RESETX(5pin), MUTEX_SP(6pin), MUTEX_DAC(7pin), ADDR(21pin)
*4 CMOS output terminal SPDIFO(22pin), SDAO(28pin), SCLO(29pin), MUTEX_DACO(30pin), MUTEX_SPO(31pin), RESETXO(32pin), DATAO2(33pin), DATAO1(34pin), LRCKO(35pin), BCKO(36pin), SYSCKO(37pin)
*5 Open drain output terminal SDAI(9pin)
Electric characteristic(Analogue serial)
V
=3.3V Unless specified, Ta=25°C,RL=10k, VC standard
DD
Item Symbol
Min Standard Max
Rating Value
Unit Object pin/Condition
whole Circuit current IQ - 15 30 mA VDD Regulator part Output voltage V
1.3 1.5 1.7 V IO=100mA
REG
PLL part Lock frequency F
- 24.576 - MHz 256fs(fs=48kHz) input
LK8
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Block diagram
BCKI
MCLK
VSS3
39
BCKO
LRCKO
SDATAO1
SYSCLKO
3740 38 36 27
35
SDATAO2
RESETXO
33 32 31 30 29 2834
MUTEX_DACO
MUTEX_SPO
SDAO
SCLO
N.C.
N.C.
N.C.
N.C.
2526
24 23 22 21
SPDIFO
N.C.
ADDR
CLK
DSP
SP
Conv.
TEST
I2S
IF
2 3 4 5 6 7 8 9 10 11 13 14 15
1
N.C.
LRCKI
SDATA1
SDATA2
RESETX
Control
IF
MUTEX_SP
MUTEX_DAC
I2C
IF
SCLI
SDAI
VSS
LDO15
DVDDCORE
12
16
N.C.
REG15
LDOPOFF
VDD
ANATEST
PLLA
17 18 19 20
N.C.
VSS
PLLFIL
MODE
Block diagram
Fig.2
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Pin Description(s)
No.
Name Description of terminals
1 N.C (*2)
Type
-
No.
Name Description of terminals
21 ADDR I2C Slave address selection
Type
B
terminal 2 LRCKI I2S Audio LR signal input 3 SDATA1 I2S Audio data input 1 4 SDATA2 I2S Audio data input 2 5 RESETX Reset status with “L” 6 MUTEX_SP DAC mute signal input(*1) 7 MUTEX_DAC SP mute signal input(*1) 8 SCLI I2C Forwarding clock input 9 SDAI I2C Data input output
10 VSS1 Digital I/O GND 11 DVDDCORE Connect to REG15 terminal 12 REG15 Built-in regulator voltage output 13 LDOPOFF Built-in regulator POFF signal
D
22 SPDIFO S/PDIF Signal output
D
23 N.C
D
24 N.C
B
25 N.C
B
26 N.C
B
27 N.C
F
28 SDAO 2 line serial data output(*1)
E
29 SCLO 2 line serial clock output(*1)
-
30 MUTEX_DACO DAC mute signal output(*1)
-
31 MUTEX_SPO SP mute signal output(*1)
G
32 RESETXO Reset signal output(*1)
G
33 SDATAO2 I2S Audio data output 2
C
-
-
-
-
­C C C C C C
input 14 ANATEST Analog test monitor terminal 15 VDD Digital I/O power supply 16 N.C 17 N.C 18 PLLFIL Filter connection terminal for PLL 19 VSS2 Digital I/O GND 20 MODE Test mode selection input
N.C.Non Connection (*1)signal terminal is used with D class amplifier IC (BD5446EFV etc.) for input I2S made by Rohm. (*2) It connects with the lead frame of a package. Please use by OPEN or GND connection.
G
34 SDATAO1 I2S Audio data output 1
-
35 LRCKO I2S Audio LR signal output 1
-
36 BCKO I2S Audio clock output 1
-
37 SYSCLKO System clock output(*1)
G
38 VSS3 Digital I/O GND
-
39 MCLK Master clock input
A
40 BCKI I2S Audio clock input
C C C C
­H D
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Pin Equivalent Circuit Diagrams
A B C
VDD
VDD
VDD
VSS
VSS
VSS
D E F
VDD
VSS
VSS
VSS
G H
VDD
VSS
VDD
VSS
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
A
6
5
Technical Note
1.Command interface
I2C bus method is used in command interface with host CPU on BU9414FV.
In BU9414FV, not only writing but read-out is possible except for some registers.
Besides the slave address in BU9414FV, one byte select address can be Specified, written and readout.
2
The format of I
C bus slave mode is shown below.
MSB LSB MSB LSB MSB LSB
S Slave Address A Select Address A Data A P
S: Start condition
Slave Address: Putting up the bit of read mode (H") or write mode (L") after slave address (7bit) set with ADDR,
the data of eight bits in total will be sent. (MSB first)
A: The acknowledge bit in each byte adds into the data when acknowledge is sent and received.
When data is correctly sent and received, "L" will be sent and received.
There was no acknowledge for "H".
Select Address: 1 byte select address is used in BU9414FV. (MSB first)
Data: Data-byte, data(MSB first)sent and received
P: Stop Condition
SDAI
MSB
LSB
SCLI
Start condition
Stop condition
When SDAI ,SCLI=”H”
When SDAI , SCLI=H
11--11.. DDaattaa wwrriittiinngg
S Slave Address A Select Address A Data A P
: From master to slave : From slave to master
ADDR=0 MSB LSB
A6 A5 A4 A3 A2 A1 A0 R/W
1 0 0 0 0 0 0 0
ADDR=1 MSB LSB
A6 A5 A4 A3 A2 A1 A0 R/W
Setting of BU9414FV slave address
Terminal setting Write-mode
ADDR
Slave-address 0 80h 1 82h
1 0 0 0 0 0 1 0
S Slave Address
Select Address A Data A Data A Data A P
(example) 80h 20h 00h 00h 00h : From master to slave : From slave to master
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Writing procedure
Step Clock Master Slave(BU9414FV) Note
1 Start Condition
2 7 Slave Address
3 1 R/W (0)
&h80 (&h82)
4 1 Acknowledge
5 8 Select Address Writing object register 8 bit
6 1 Acknowledge
7 8 Data Writing data 8 bit
8 1 Acknowledge
9 Stop Condition
- The select address add +1 by auto increment function when the data is transferred continuously.
Repeat of Step 7~8.
11--22.. DDaattaa rreeaaddoouutt
First of all, the readout target address(ex.&h20h) is written in &hD0 address register at the time of readout.
In the following stream, data is read out after the slave address. Please do not return the acknowledge when ending the
reception.
S Slave Address A Req_Addr A Select Address A P
(example) 80h D0h 20h
S Slave Address A Data 1 A Data 2 A A Data N Ā P
(example) 81h **h **h **h : Master to slave, : Slave to master, A:With acknowledge, Ā:without acknowledge
Readout Procedure
Step Clock Master Slave(BU9414FV) Note
1 Start Condition
2 7 Slave Address
3 1 R/W (0)
&h80 (&h82)
4 1 Acknowledge
5 8 Req_Addr Address for I2C readout &hD0
6 1 Acknowledge
7 8 Select Address Readout object register 8 bit
8 1 Acknowledge
9 1 Stop Condition
10 1 Start Condition
11 7 Slave Address
12 1 R/W (1)
&h81 (&h82)
13 1 Acknowledge
14 8 Data Readout data 8 bit
15 1 Acknowledge
16 Stop Condition
The select address adds +1 by auto increment function when continuous data is transferred.
Repeat Step14~15.
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
1-3. Control signal specification
Bus line, I/O stage electrical specification and timing.
SDAI
t
BUF
t
LOW
t
t
R
F
t
HD;STA
SCLI
t
HD;STA
SP
t
HD;DAT
t
HIGH
t
SU;DATtSU;STA
t
SU;STO
Sr
P
Fig.1-1: Timing chart
Table 1-1: SDAI and SCLI bus-line characteristic (Unless specified, Ta=25°C, Vcc=3.3V)
Parameter Code
High-speed mode
Min. Max.
Unit
1 SCLI clock frequency fSCL 0 400 kHz
Bus-free-time between "Stop" condition and "Start"
2
condition
"Start" condition of hold-time (resending). After this period,
3
the first clock-pulse is generated.
4 LOW status hold-time of SCLI clock
5 HIGH status hold-time of SCLI clock
6 Setup time of resending “Start” condition
7 Data-hold-time
8 Data-setup time
9 Rising time of SDAI and SCL signal
10 Fall time of SDAI and SCL signal
11 Setup time of "Stop" condition
t
BUF 1.3 μS
t
HD;STA 0.6 μS
t
LOW 1.3 μS
t
HIGH 0.6 μS
t
SU;STA 0.6 μS
t
HD;DAT 01) μS
t
SU;DAT
t
R 20+Cb 300 ns
t
F 20+Cb 300 ns
t
SU;STO 0.6 μS
500/250/15
0
ns
12 Capacitive load of each bus-line Cb 400 pF
The above-mentioned numerical values are all the values corresponding to V
IH min
and V
IL max
level.
1) To exceed an undefined area on falling edged of SCLI, transmission device should internally offer the hold-time of
300ns or more for SDAI signal(V
of SCLI signal).
IH min
2) Data-setup time changes with setup of MCLK. In MCLK=512fs, data setup time is 150ns.
In MCLK=256fs, data setup time is 250ns. In MCLK=128fs, data setup time is 500ns.
The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.
When problem occurs by any chance, we talk in good faith and correspond.
Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V.
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
2.Switching of data and clock
I/O system chart of BU9414FV audio data is shown below.
Digital input1
Digital input1
Digital input2
Digital input2
SEL1
SDATA1
SDATA2
Audio DSP (BU9414FV)
S-P
conversi
on1
S-P
conversi
on2
DSP CLK (512fs)
DSP oper atio n part This part is performanced by hardware.
Main Main
Bass
Func.
Main
PLLA
mclk_
P-EQ
div
MCLK
SEL3
Sub
Treble
plla_
div
SYSCLKO
(256fs)
EVR
I2C
Sub
Control I/F
RESET
SEL2
MODE
Convers
Convers
Convers
・・・
ADDR
P-S
SDATAO1(Main)
ion1
P-S
SDATAO2(Sub)
ion2
P-S
ion3
SPDIFO
D Class amp output
(Main SP)
D Class amp output
(Sub Woofer)
Optical output
BU9414FV has 2 digital stereo input and 3 digital stereo output with the same sampling rate.
Output from DSP operation part is converted into I
2
S mode digital output or S/PDIF mode digital serial output.
System clock uses master clock input from MCLK terminal, makes 512fs multiplying clock in PLL block. Moreover, 256fs
synchronous clock can be output from terminal SYSCLKO, and the clock is supplied to external DAC or D class SP amplifier.
SPDIFO and output data selection of SDATAO1 and SDATAO2 should unify the DSP processing after (post) or processing
before (pre) with all outputs.
22--11.. SS--PP ccoonnvveerrssiioonn11 iinnppuutt ddaattaa sseelleeccttiioonn((SSEELL11))
Default = 0
Select Address Value Operating Description
&h03 [ 0 ]
0 Input data from SDATA1
1 Input data from SDATA2
22--22.. SS--PP ccoonnvveerrssiioonn22 iinnppuutt ddaattaa sseelleeccttiioonn((SSEELL11))
Default = 0
Select Address Value Operating Description
&h03 [ 4 ]
0 Input data from SDATA1
1 Input data from SDATA2
22--33.. OOuuttppuutt ddaattaa sseelleeccttiioonn((SSEELL22)) ttoo PP--SS ccoonnvveerrssiioonn11 ((SSDDAATTAAOO11 TTeerrmmiinnaall))
Default = 0
Select Address Value Operating Description
&h04 [ 10 ]
0 Main data output after DSP is processed.
1 Sub data output after DSP is processed.
2 Main data output before DSP is processed.
3 Sub data output before DSP is processed.
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
22--44.. OOuuttppuutt ddaattaa sseelleeccttiioonn((SSEELL22)) ttoo PP--SS ccoonnvveerrssiioonn22 ((SSDDAATTAAOO22 TTeerrmmiinnaall))
Default = 0
Select Address Value Operating Description
&h04 [ 54 ]
0 Sub data output after DSP is processed.
1 Main data output after DSP is processed.
2 Sub data output before DSP is processed.
3 Main data output before DSP is processed.
22--55.. SSPPDDIIFFOO TTeerrmmiinnaall oouuttppuutt ddaattaa sseelleeccttiioonn((SSEELL22))
Default = 0
Select Address Value Operatin
&h05 [ 10 ]
g Description
0 Main data output after DSP is processed.
1 Sub data output after DSP is processed.
2 Main data output before DSP is processed.
3 Sub data output before DSP is processed.
22--66.. SSyysstteemm cclloocckk sseelleeccttiioonn((SSEELL33))
Select the DSP clock supplied to S-P conversion1、S-P conversion2、DSP、P-S conversion1、P-S conversion2、S/PDIF
output part.
Default = 0
Select Address Value Operating Description
&h08 [ 54 ]
0 Chose the input from a MCLK terminal as a clock.
1 Chose the PLL output as a clock.
2
Chose the input from a SDATA2terminal as a clock. (used for IC test).
3
After power on or reset released, system block selection uses clock(even if not 512fs is ok) input from terminal MCLK to
receive I2C command and initialize BU9414. Then set the dividing frequency ratio of PLL block (mclk_div, pll_div) that is
suitable for the clock frequency from terminal MCLK , when PLL_512fs clock from PLL is steady, set &h08 = 10h.
Dividing frequency ratio setting of PLL block which corresponding to input clock from terminal MCLK
22--77..
Sampling rate of input clock Setting of mclk_div
&hF3
512fs24.576MHzfs=48kHz 256fs12.288MHzfs=48kHz
128fs6.144MHzfs=48kHz
10h 01h 00h
08h 01h 00h
04h 01h 00h
Setting of pll_div
&hF5
PLL initialization
&hF6
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2012.03 - Rev.
BU9414FV
A
Technical Note
3. S-P Conversion 1, S-P Conversion 2
BU9414FV has two serial-parallel conversion circuits. S-P conversion 1, S-P conversion 2
S-P conversion 1 & 2 receives the audio data of three-wire serial input from terminal and converts it into parallel data.
They select the inputs from LRCKI (2pin), BCKI (40pin), SDATA1 (3pin), and SDATA2(4pin).
Input format has IIS method, left-justified method and right-justified method. Moreover, for bit clock frequency, 64fs or 48fs
can be selected, and when 48fs is selected, the input format becomes the fixed right-justification. In addition, 16bit, 20bit and
24bit inputs can be selected respectively.
Timing chart of each transmission method is shown in the diagram below.
IIS method
IIS方
LRCKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKI
MSB LSB
S
DATAI
16bit
MSB LSB
S
16bit
20bit
24bit
20bit
24bit
Left-justified method
詰方式
LRCKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKI
MSB LSB
S
DATAI
16bit
20bit
24bit
MSB LSB
S
16bit
20bit
24bit
Right-justified
詰方式
method
LRCKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKI
DATAI
MSB LSB
S
16bit
20bit
24bit
MSB LSB
S
16bit
20bit
24bit
48fs
LRCKO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BCKO
DATAO
MSB L SB
S
16bit
20bit
24bit
MSB LSB
S
16bit
20bit
24bit
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2012.03 - Rev.
BU9414FV
A
Technical Note
33--11.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss bbiitt cclloocckk ffrreeqquueennccyy sseettttiinngg
Default = 0
Select Address Value Operational explanation
S-P conversion1, S-Pconversion2
&h0B [ 4 ]
0 64fs method
1 48fs method
33--22.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss ffoorrmmaatt sseettttiinngg
Default = 0
Select Address Value Operational explanation
S-P conversion1 &h0B [ 32 ]
S-P conversion2 &h0C [ 32 ]
0 IIS method
1 left-justified method
2 right-justified method
33--33.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss ddaattaa bbiitt wwiiddtthh sseettttiinngg
Default =
0
Select Address Value Operational explanation
S-P conversion1 &h0B [ 10 ]
S-P conversion2 &h0C [ 10 ]
0 16 bit
1 20 bit
2 24 bit
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2012.03 - Rev.
BU9414FV
A
Technical Note
4. Digital sound processingDSP
BU9414FV’s Digital Sound Processing(DSP) consists of special hardware most suitable to Thin TV.
BU9414FV uses this special DSP to perform the following processing.
2
Prescaler, DC Cut HPF, Channel Mixer, P
2
Pseudo Stereo, Surround, P
Bass, Pseudo Bass, P2Treble, 7 BandParametric Equalizer, Master Volume, L/R
VolumePerfect Pure Volume), BASS, MIDDLE, TREBLE,
Balance, PostScaler, Output Clipper.
DDSSPP OOuuttlliinnee aanndd SSiiggnnaall FFllooww
Data width 32 bit (DATA RAM
Machine cycle 40.7ns (512fs, fs=48kHz Multiplier 32×24 → 56 bit Adder 32+32 32 bit
Data RAM
Coefficient RAM 128×24 bit
256×32 bit
MUX
Data
Input
RAM
Coefficient
operation
MUX
0
Circuit
Coefficient
M U X
RAM
Decoder
circuit
Sampling frequency fs=48kHz
Master clock 512fs (24.576MHz, fs=48kHz
ADD
Acc
Digital signal from 16bit to 24bit is inputted to DSP,
Output
and it is extended by +8bit(+42dB) as overflow margin on the upper side.
The clip process is performed in DSP when the process exceeding this range is performed.
Input1
Input2
Pre
scaler
DC cut
HPF
Channel
mixer
Digital Audio Processing Signal Flow
P2Volume
Surround
BASS MIDDLE TREBLE
Pseudo
BASS
P2Bass P2Treble
Scaler
7Band
Parametric
EQ
EVR
Blance
EVR
Blance
2Band
DRC
Clipper
Post
scaler
Clipper
Main output
Sub output
44--11.. PPrreessccaalleerr
When digital signal is inputted to audio DSP, if the level is full scale input and the process of surround or equalizer is
performed, then it overflows, therefore the input gain is adjusted by prescaler.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Prescaler does not incorporate the smooth transition function.
Default = 30h
Select Address Operational explanation
&h20 [ 70 ]
command gain
00 01 +23.5dB
30 31
32
FE FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
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2012.03 - Rev.
BU9414FV
A
Technical Note
44--22.. DDCC CCuutt HHPPFF
The DC offset component of digital signal inputted to the audio DSP is cut by this HPF.
The cutoff frequency fc of HPF is 1Hz, and first-order filter is used.
Default = 0
Select Address Value Operational explanation
&h21 [ 0 ]
0 Not using the DC Cut HPF
1 Using the DC Cut HPF
44--33.. CChhaannnneell mmiixxeerr
It performs the setting of mixing the sounds of left channel & right channel of digital signal inputted to the audio DSP.
Here the stereo signal is made to be monaural.
The data inputted to Lch of DSP is mixed.
Default = 0
Select Address Value Operational explanation
&h22 [ 76 ]
0 Inputting the Lch data
1 Inputting the data of Lch + Rch / 2
2 Inputting the data of Lch + Rch / 2
3 Inputting the Rch data
The data inputted to Rch of DSP is mixed.
Default = 0
Select Address Value Operational explanation
&h22 [ 54 ]
0 Inputting the Rch data
1 Inputting the data of Lch + Rch / 2
2 Inputting the data ofLch + Rch / 2
3 Inputting the Lch data
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2012.03 - Rev.
BU9414FV
A
Technical Note
2
2
44--44.. P
P
VVoolluummee ((PPeerrffeecctt PPuurree VVoolluummee))
There are some scenes in which sound suddenly becomes large like plosive sound in TV Commercial or Movie.
2
Volume function automatically controls the volume and adjusts the output level.
P
In addition, it also adjusts in such a way that a whispery sound can be heard easily.
2
Volume function operates in the fields of (1), (2) & (3) divided according to input level.
P
(1) at the time of V
inf
(-)~V
Noise is prevented from being lifted by P
(2) When input level is over V
V
= VI + α
O
min
and output is below V
min
2
Volume function.
Omax
α: Lifting the Whole output level by the offset value α
(3) When output level
V
= K・VI + α
O
exceeds V
Omax
V
O
V
Omax
P2V_MAX
(2)
P2V off
K
(3)
K: Slope for suppressing of D range (P2V_K)
It is also possible to set an output level constant.
2
Selection of using the P
Default = 0
Volume function.
V
Omin
α
V
Oinf
(1)
V
V
Iinf
Imin
P2V_MIN
0dB
V
I
Select Address Value Operational explanation
&h33 [ 7 ]
0 Not using the P2Volume function
1 Using the P2Volume function
Setting of V
In order to cancel that noise etc. is lifted by P
2
Volume functions.
P
Default = 00h
min
2
Volume, the P2V_MIN sets the minimum level at which (to the minimum) the
command
Select Address Operational explanation
&h34 [ 4:0 ]
command gain
00 -∞ 01 02 03 04 05 06 07
-30dB
-32dB
-34dB
-36dB
-38dB
-40dB
-42dB
command gain
-44dB
08 09
-46dB
0A
-48dB
-50dB
0B 0C
-52dB
0D
-54dB
0E
-56dB
0F
-58dB
command gain
-60dB
10 11
-62dB
12
-64dB
-66dB
13 14
-68dB
15
-70dB
16
-72dB
17
-74dB
コマンド値 ゲイン
-76dB
18 19
-78dB
1A
-80dB
-82dB
1B 1C
-84dB
1D
-86dB
1E
-88dB
1F
-90dB
Setting of V
P2V_MAX sets the output suppression level. It represents the output level V
max
at the time of input level VI = 0dB in the
max
case of setting of P2V_K = “0h”slope is 0).
Default = 00h
Select Address Operational explanation
&h35 [ 4:0 ]
command gain
00 0dB 01 02 03 04 05 06 07
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
command gain
08
-8dB
09
-9dB
-10dB
0A
-11dB
0B 0C
-12dB
0D
-13dB
0E
-14dB
0F
-15dB
command gain
10
-16dB
11
-17dB
-18dB
12
-19dB
13 14
-20dB
15
-21dB
16
-22dB
17
-23dB
command gain
18
19 1A 1B 1C 1D 1E 1F
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© 2012 ROHM Co., Ltd. All rights reserved.
-24dB
-25dB
-26dB
-27dB
-28dB
-29dB
-30dB
-
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of K
P2V_K sets the slop of D range. It sets the P2V_MAX = “1Eh”(-30dB) and represents the output level V
input level V
= 0dB.
I
Default = 00h
at the time of
max
Select Address Operational explanation
&h36 [ 3:0 ]
command gain
0 -30dB 1
-28dB
-26dB
2
-24dB
3 4
-22dB
5
-20dB
6
-18dB
7
-16dB
comman
8
9 A B C D E F
gain
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB 0dB
Setting of α
P2V_OFS makes small voice easy to be heard because the whole output level is lifted.
Default = 00h
Select Address Operational explanation
&h37 [ 4:0 ]
command gain
00 0dB 01 02 03 04 05 06 07
+1dB +2dB +3dB +4dB +5dB +6dB +7dB
command gain
08 09 0A 0B 0C 0D 0E 0F
+8dB
+9dB +10dB +11dB +12dB +13dB +14dB +15dB
command gain
10
+16dB
11
+17dB +18dB
12
+19dB
13 14
+20dB
15
+21dB
16
+22dB
17
+23dB
command gain
18
+24dB 19 1A 1B 1C 1D 1E 1F
-
-
-
-
-
-
-
Setting 1 of transition time at the time of attack
2
A_RATE is the setting of transition time when the state of P
Default = 0
Volume function is transited to (2)→(3).
Select Address Operational explanation
&h38 [ 6:4 ]
command A_RATE time
0 1ms 1 2ms 2 3
3ms 4ms
command
4 5 6 7
A_RATE time
5ms 10ms 20ms 40ms
Setting 1 of transition time at the time of recovery
2
R_RATE is the setting of transition time when the state of P
Default = 0h
Volume function is transited to (3)→(2).
Select Address Operational explanation
&h38 [ 3:0 ]
command R_RATE time
0 0.25s 1 2 3 4 5 6 7
0.5s
0.75s 1s
1.25s
1.5s 2s
2.5s
command
8 9 A B C D E F
R_RATE time
3s 4s 5s 6s 7s 8s 9s
10s
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Explanation of A_RATE,R_RATE(field transition of (2)<->(3))
Input
V
I
Time
T
Field (2) Field (2)Field (3)
V
Omax
Output
V
O
Time
T
Attack operation
A_RATE
The time from exceeding the attack operation detection level V
till the attack operation's
Omax
transition to Field (3) is completed
Recovery operation
R_RATE
The time from falling below the recovery operation detection level V operation's transition to Field
(2) is completed
till the recovery
Omax
Setting 1 of attack detection time
2
A_TIME is the setting of the initiation of P
Volume function’s transition operation. If output level at the time of transiting to
(2)(3) continues for more then A_TIME time in succession, then the state transition of P
Default = 0
Select Address Operational explanation
&h39 [ 6:4 ]
command A_TIME
command 0 0.5ms 1 1ms 2 3
Setting 1 of recovery detection time
2
R_TIME is the setting of the initiation of P (3)(2) continues for more then R_TIME time in succession, then the state transition of P
Default = 0
Select Address Operational explanation
&h39 [ 2:0 ]
Volume function’s transition operation. If output level at the time of transiting to
command R_TIME
1.5ms 2ms
0 50ms 1 100ms 2 3
150ms 200ms
2
Volume is started.
A_TIME 4 5 6 7
2
Volume is started.
command
4 5 6 7
3ms 4ms 5ms 6ms
R_TIME
300ms 400ms 500ms 600ms
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Explanation of A_RATE_Low,R_RATE_Low(field transition of (1)<->(2))
Technical Note
V
Imin
Input
V
I
Tme T
Field (1) Field (1)Field (2)
V
Omin
Output
V
O
Time T
Recovery operation
R_RATE_Low
The time from falling below the recovery operation detection level V
till the recovery
Imin
operation's transition to Field (2) is completed
Attack operation
A_RATE_Low
The time from exceeding the attack operation detection level V attack operation's transition to Field (1) is completed
Imin
till the
Setting 2 of the transition time at the time of attack
A_RATE_LOW is the setting of transition time when the state of P
Default = 0
2
Volume function is transited to (2)→(1).
Select Address Operational explanation
Command
0 1ms
&h3A [ 6:4 ]
1 2ms 2 3
Setting 2 of the transition time at the time of recovery R_RATE_LOW is the setting of transition time when the state of P
Default = 0
A_RATE_LOW Time
Command
4
5 3ms 4ms
2
Volume function is transited to (1)→(2).
6
7
A_RATE_LOW Time
5ms 10ms 20ms 40ms
Select Address Operational explanation
&h3A [ 2:0 ]
Command
R_RATE_LOW Time
0 1ms 1 2ms 2 3
3ms 4ms
Command
4 5 6 7
R_RATE_LOW Time
5ms 10ms 20ms 40ms
Setting 2 of attack recovery detection time
A_TIME_LOW is the setting of the initiation of P2Volume function’s transition operation. If the input level below A continues more than
continuation A_TIME_LOW in the state of (2) or (3), state transition of P2Volume will be started toward the state of
(1).
Default = 0
Select Address Operational explanation
&h3B [ 6:4 ]
Command
0 50ms 1 100ms 2 3
A_TIME_LOW
150ms 200ms
Command
4 5 6 7
A_TIME_LOW
300ms 400ms 500ms 600ms
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting 3 of attack recovery detection time
2
R_TIME_LOW is the setting of the initiation of P
Volume function’s transition operation. If the input level above A continues
more than continuation R_TIME_LOW in the state of (1), state transition of P2Volume will be started toward the state of (2)
or (3).
Default = 0
Select Address Operational explanation
&h3B [ 6:4 ]
Command
0 0.5ms 1 1ms 2 3
R_TIME_LOW
1.5ms 2ms
Command
4 5 6 7
R_TIME_LOW
3ms 4ms 5ms 6ms
Scene change detection and High-speed recovery function(functioning only at the time of transition of (2)<->(3)
2
Volume function makes the P2Volume also compatible with large pulse sounds (clapping of hands, fireworks & shooting
P
2
etc.) in addition to normal P
Volume operation. When large pulse sound is inputted, attack operation (A_RATE) or recovery
operation (R_RATE) is performed at 4 or 64 times the speed of normal attack operation or recovery operation.
Selection of using the scene change detection function.
Default = 0
Select Address Value Operational explanation
&h3C[ 7 ]
0 Not using of pulse sound detection function
1 Using of pulse sound detection function
Selection of operating times of Recovery Time (R_RATE) in the case of using the scene change detection function.
(Operating-time selection at the time of R_RATE / scene detection) serves as a recovery time.
Default = 0
Select Address Value
Operational explanation
&h3D [ 1:0 ]
Command
0 4 1 8 2 3
Value
16 64
Selection of scene change detection time
Default = 0
Select Address Operational explanation
&h3C [ 6:4 ]
Command Time
0 1 2 3
50ms 100ms 150ms 200ms
Command
4 5 6 7
Time
300ms 400ms 500ms 600ms
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Setting of operating level of scene change detection function
Operation is started by the difference between the presently detected value and the last value as a standard.
Default = 0
Select Address Operational explanation
&h3C [ 2:0 ]
Command
0 Over 1.002 1 Over 0.709 2 3
Detection level
Over 0.502 Over 0.355
Command
4 5 6 7
Technical Note
Detection level
Over 0.251 Over 0.178 Over 0.126 Over 0.089
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-5. Surround Matrix Surround 3D
It realizes the Surround with little feeling of fatigue even after wide seat spot and long-time watching & listening to. It
reproduces the feeling of broadening of the natural sounds in medium & high bands and realizes the sound field that do no
damage to the feeling of locating of the vocal.
If loop is used, then the number of stages of phase shifter can be increased in a pseudo way.
Lch
Loop
+
Lch
+
+
L-R
-
+
+
PHASE
SHIFTER
EFFECT
GAIN
LPF
Rch
-
+
Rch
ON/OFF of Surround function
Default = 0
Select Address Value Operational explanation
&h70 [ 7 ]
0 Turning the Surround effect OFF
1 Turning the Surround effect ON
Setting of using the LOOP
Default = 0
Select Address Value Operational explanation
&h70 [ 5 ]
0 Not using of LOOP
1 Using of LOOP
Setting of Surround gain
Default = Fh
Select Address Operational explanation
&h70 [ 30 ]
Command
00dB 1 2 3 4 5 6 7
Gain
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
Command
8
9 A B C D
E
F
Gain
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-6. BASS
BASS of TONE Control can use Peaking filter or Low-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients b0, b1, b2, a1, a2by selecting the F0,Q and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
BASS Control
Selection of filter types
Default = 0
Select Address Value Operational explanation
&h40 [ 7 ]
0 Peaking filter
1 Low-shelf filter
Selection of smooth transition function
Default = 0
Select Address Value Operational explanation
&h40 [ 6 ]
0 Using BASS smooth transition function
1 Not BASS using smooth transition function
Selection of smooth transition time
Default = 0
Select Address Value Operational explanation
&h40 [ 5:4 ]
0 21.4ms
1 10.7ms
2 5.4ms
3 2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h40[0] command, to the coefficient RAM
for smooth transition, the alteration of BASS’s coefficients is completed by using this command.
Default = 0
Select Address Value Operational explanation
&h4C [ 0 ]
0 BASS smooth transition stop
1 BASS smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of Bass smooth transition time,
from the time the BASS smooth transition start &h4C[0] = “1” is executed until the following command is sent. Please
make sure to perform the Bass smooth transition stop&h4C[0] = “0” after the smooth transition is completed.
&h4D [0] and &hF4 [0] are set to H during soft transition.
(Refer to Chapter 15)
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted directly to the coefficient RAM.
Default = 0
Select Address Value Operational explanation
&h40 [ 0 ]
0 BASS coefficient transmission stop
1 BASS coefficient transmission start
selection of frequency(F
Default = 0Eh
0
Select Address Operational explanation
&h41 [ 5:0 ]
Command
00 01 02 03 04 05 06 07
Frequency
20Hz 22Hz 25Hz 28Hz 32Hz 35Hz 40Hz 45Hz
Command
08
09 0A 0B 0C 0D
0E
0F
Frequency
50Hz 56Hz 63Hz 70Hz 80Hz
90Hz 100Hz 110Hz
Command
10 11 12 13 14 15 16 17
Frequency
125Hz 140Hz 160Hz 180Hz 200Hz 220Hz 250Hz 280Hz
Command
18 19 1A 1B 1C 1D 1E 1F
Frequency
315Hz 350Hz 400Hz 450Hz 500Hz 560Hz 630Hz 700Hz
Command
20 21 22 23 24 25 26 27
Frequency
800Hz 900Hz
1kHz
1.1kHz
1.25kHz
1.4kHz
1.6kHz
1.8kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
2kHz
2.2kHz
2.5kHz
2.8kHz
3.15kHz
3.5kHz 4kHz
4.5kHz
Command
30 31 32 33 34 35 36 37
Frequency
5kHz
5.6kHz
6.3kHz 7kHz 8kHz 9kHz
10kHz 11kHz
Command
38
39 3A 3B 3C 3D 3E 3F
Frequency
12.5kHz 14kHz 16kHz 18kHz 20kHz
-
-
-
Selection of quality factor (Q)
Default = 4h
Select Address Operational explanation
&h42 [ 3:0 ]
Command
Quality factor
0 1 2 3 4 5 6 7
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Selection of Gain
Default = 40h
Select Address Operational explanation
&h43 [ 6:0 ]
Command Gain
1C -18dB
3E -1dB 3F 40 41
64
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
Command
8 9 A B C D E F
-0.5dB 0dB
+0.5dB
+1dB42
+18dB
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-7. MIDDLE
MIDDLE of TONE Control uses Peaking filter.
The setting is converted, in the IC, into digital filter’s coefficients b0, b1, b2, a1, a2by selecting the FQ and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
MIDDLE Control
Selection of smooth transition function
Default = 0
Select Address Value Operational explanation
&h44 [ 6 ]
0 Using MIDDLE smooth transition function
1 Not MIDDLE using smooth transition function
Selection of smooth transition time
Default = 0
Select Address Value Operational explanation
&h44 [ 5:4 ]
0 21.4ms
1 10.7ms
2 5.4ms
3 2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h44[0] command, to the coefficient RAM
for smooth transition, the alteration of MIDDLE’s coefficients is completed by using this command.
Default = 0
Select Address Value Operational explanation
&h4C [ 1 ]
0 MIDDLE smooth transition stop
1 MIDDLE smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of MIDDLE smooth transition
time, from the time the MIDDLE smooth transition start &h4C[1] = “1” is executed until the following command is sent.
Please make sure to perform the MIDDLE smooth transition stop&h4C[1] = “0” after the smooth transition is completed.
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted to the direct coefficient RAM.
Default = 0
Select Address Value Operational explanation
&h44 [ 0 ]
0 MIDDLE coefficient transmission stop
1 MIDDLE coefficient transmission sart
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Selection of frequency(F0)
Default = 0Eh
Select Address Operational explanation
&h45 [ 5:0 ]
Command
00 01 02 03 04 05 06 07
Frequency
20Hz 22Hz 25Hz 28Hz 32Hz 35Hz 40Hz 45Hz
Command
08 09 0A 0B 0C 0D 0E 0F
Frequency
50Hz 56Hz 63Hz 70Hz 80Hz
90Hz 100Hz 110Hz
Command
10 11 12 13 14 15 16 17
Frequency
125Hz 140Hz 160Hz 180Hz 200Hz 220Hz 250Hz 280Hz
Command
18
19 1A 1B 1C 1D 1E 1F
Frequency
315Hz 350Hz 400Hz 450Hz 500Hz 560Hz 630Hz 700Hz
Command
20 21 22 23 24 25 26 27
Frequency
800Hz 900Hz
1kHz
1.1kHz
1.25kHz
1.4kHz
1.6kHz
1.8kHz
Command
28
29 2A 2B 2C 2D 2E 2F
Frequency
2kHz
2.2kHz
2.5kHz
2.8kHz
3.15kHz
3.5kHz 4kHz
4.5kHz
Command
30 31 32 33 34 35 36 37
Frequency
5kHz
5.6kHz
6.3kHz 7kHz 8kHz 9kHz
10kHz 11kHz
Command
38 39 3A
3B 3C 3D 3E 3F
Frequency
12.5kHz 14kHz 16kHz 18kHz 20kHz
Selection of quality factor(Q)
Default = 4h
Select Address Operational explanation
&h46 [ 3:0 ]
Command
Quality factor
0 1 2 3 4 5 6 7
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Command
Quality factor
8
9 A B C D
E F
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address Operational explanation
&h47 [ 6:0 ]
Command Gain
1C -18dB
3E -1dB 3F 40 41
-0.5dB 0dB
+0.5dB
+1dB42
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
-
-
-
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2012.03 - Rev.
BU9414FV
A
Technical Note
4-8. TREBLE
TREBLE of TONE Control can use Peaking filter or High-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients b0, b1, b2, a1, a2by selecting the F0,Q and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
TREBLE Control
Selection of filter types
Default = 0
Select Address Value Operational explanation
&h48 [ 7 ]
0 Peaking filter
1 High-shelf filter
Selection of smooth transition function
Default = 0
Select Address Value Operational explanation
&h48 [ 6 ]
0 Using smooth transition function
1 Not using smooth transition function
Selection of smooth transition time
Default = 0
Select Address Value Operational explanation
&h48 [ 5:4 ]
0 21.4ms
1 10.7ms
2 5.4ms
3 2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h48[0] command, to the coefficient RAM
for smooth transition, the alteration of TREBLE’s coefficients is completed by using this command.
Default = 0
Select Address Value Operational explanation
&h4C [ 2 ]
0 TREBLE smooth transition stop
1 TREBLE smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of TREBLE smooth transition
time, from the time the TREBLE smooth transition start &h4C[2] = “1” is executed until the following command is sent.
Please make sure to perform the TREBLE smooth transition stop(&h4C[2] = “0”) after the smooth transition is completed.
&h4D [0] and &hF4 [0] are set to H during soft transition.(Refer to Chapter 15)
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2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted to the direct coefficient RAM.
Default = 0
Select Address Value Operational explanation
&h48 [ 0 ]
0 TREBLE coefficient transmission stop
1 TREBLE coefficient transmission start
Selection of frequency(F
Default = 0Eh
Select
0
Operational explanation
Address
&h49 [ 5:0 ]
Command
00 01 02 03 04 05 06 07
Frequency
20Hz 22Hz 25Hz 28Hz 32Hz 35Hz 40Hz 45Hz
Command
08 09 0A 0B 0C 0D 0E 0F
Frequency
50Hz 56Hz 63Hz 70Hz 80Hz
90Hz 100Hz 110Hz
Command
10 11 12 13 14 15 16 17
Frequency
125Hz 140Hz 160Hz 180Hz 200Hz 220Hz 250Hz 280Hz
Command
18 19 1A 1B 1C 1D 1E 1F
Frequency
315Hz 350Hz 400Hz 450Hz 500Hz 560Hz 630Hz 700Hz
Command
20 21 22 23 24 25 26 27
Frequency
800Hz 900Hz
1kHz
1.1kHz
1.25kHz
1.4kHz
1.6kHz
1.8kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
2kHz
2.2kHz
2.5kHz
2.8kHz
3.15kHz
3.5kHz 4kHz
4.5kHz
Command
30 31 32 33 34 35 36 37
Frequency
5kHz
5.6kHz
6.3kHz 7kHz 8kHz 9kHz
10kHz 11kHz
Command
38
39 3A 3B 3C 3D
3E
3F
Frequency
12.5kHz 14kHz 16kHz 18kHz 20kHz
Selection of quality factor(Q)
Default = 4h
Select Address Operational explanation
&h4A [ 3:0 ]
Command
Quality factor
0 1 2 3
0.33
0.43
0.56
0.75 4 5 6 7
Command
1.0
1.2
1.5
1.8
Quality factor
8
9 A B C D E
F
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address Operational explanation
&h4B [ 6:0 ]
Command Gain
1C -18dB
3E -1dB 3F 40 41
64
-0.5dB 0dB
+0.5dB
+1dB42
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
-
-
-
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
V
l
band
Technical Note
4-9. P2Bass Perfect Pure Bass Deep Bass Equalizer
It is the deep bass equalizer making it possible that even thin-screen TV, by which the enclosure of speaker is restricted, can reproduce the real sound close to powerful deep bass & original sound.
Solid & clear deep bass with little feeling of distortion is realized. Even boosting of bass does not interfere with vocal band,
therefore rich and natural deep band is realized.
Gain
oca
P2Bass gain
P2Bass
ボーカル帯域
f
LPF Cutoff frequency
ON/OFF of P
Default = 0
2
Bass function
HPF Cutoff frequency
HPFカットオ
LPFカ
Select Address Value Operational explanation
&h73 [ 7 ]
0 Not using of P2Bass function
1 Using of P2Bass function
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of P2Bass deep bass gain
Default = 00h
Select Address Operational explanation
&h74 [ 74 ]
Command Gain
0 0dB 1 2 3 4 5 6 7
+1dB +2dB +3dB +4dB +5dB +6dB +7dB
Command
8
9 A B C D
E
F
Gain +8dB +9dB
+10dB +11dB +12dB +13dB +14dB +15dB
2
Setting of P
Bass HPF cutoff frequency
Default = 0
Select Address Value Operational explanation
&h74 [ 32 ]
0 60Hz
1 80Hz
2 100Hz
3 120Hz
2
Setting of P
Bass HPF order
Default = 0
Select Address Value Operational explanation
&h73[ 10 ]
0 1st order
1 2nd order
2 OFF
2
Setting of P
Bass LPF cutoff frequency
Default = 0
Select Address Value Operational explanation
&h74 [ 10 ]
0 120Hz
1 160Hz
2 200Hz
3 240Hz
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-10. Pseudo bassDouble sound
A Pseudo bass function is a function which turns into that it is possible to emphasize low frequency sound effectively also to
the low speaker of low-pass reproduction capability.
In order to be audible as the fundamental wave is sounding in false by adding 2 double sound and 3 time sound to a
fundamental wave, the reproduction capability of the band of a fundamental wave becomes possible.
Although use independently is also possible for a pseudo bass function, low-pitched sound can be emphasized more by
combining with P2Bass function.
Moreover, since it is possible to change the band to emphasize, optimizing to the frequency characteristic of the speaker to
be used is possible.
IN
OUT
A super-low-pass component is intercepted.(ex. f
=40Hz)
L
A fundamental-wave component is extracted.(ex. f
HPF
=120Hz)
H
LPF1
Multiple
sound (even
number)
Generator
The generated noise signal is operated orthopedically.(ex. f
Multiple
sound (odd
number)
Generator
LPF2
LPF2
=240Hz)
C
ON/OFF of pseudo bass function
Pseudo bass sound (3 time sound) is used.
Default = 0
Select Address Value Operational explanation
&h7B [ 7 ]
0 Not using of pseudo bass(3 time sound) function
1 Using of pseudo bass(3 time sound) function
Pseudo bass sound (2 time sound) is used.
Default = 0
Select Address Value Operational explanation
&h7B [ 6 ]
0 Not using of pseudo bass(2 time sound) function
1 Using of pseudo bass(2 time sound) function
Setting of pseudo bass input HPF
Default = 00h
Select Address Operational explanation
&h7B [ 20 ]
Command
0 OFF 1 20Hz 2 3
Frequency
30Hz 40Hz
Command
4 5 6 7
Frequency
50Hz 60Hz 70Hz 80Hz
Setting of order of LPF for 2 or 3 time sound.
Default = 0
Select Address Value Operational explanation
&h7C [ 7 ]
0 2nd order
1 4th order
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of pseudo bass input LPF
Default = 00h
Select Address Operational explanation
&h7C [ 64 ]
Command
0 40Hz 1 60Hz 2 3
Frequency
80Hz
100Hz
Command
4 5 6 7
Frequency
120Hz 140Hz 160Hz 180Hz
Setting of order of LPF for 2 or 3 time sound.
Default = 00h
Select Address Operational explanation
&h7C [ 30 ]
Command Frequency
0 80Hz 1 2 3 4 5 6 7
100Hz 120Hz 140Hz 160Hz 180Hz 200Hz 220Hz
Command
8 9 A B
C
D E F
Frequency
240Hz 260Hz 280Hz 300hz 320Hz 340Hz 360Hz 380Hz
Setting of addition gain for 3 time sound
Default = 00h
Select Address Operational explanation
&h7D[ 7:4 ]
Command Gain
0 0dB 1 2 3 4 5 6 7
1dB 2dB 3dB 4dB 5dB 6dB 7dB
Command
8 9 A B C D E F
Gain
8dB
9dB 10dB 11dB 12dB 13dB 14dB 15dB
Setting of addition gain for 2 time sound
Default = 00h
Select Address Operational explanation
&h7D[ 3:0 ]
Command Gain
0 -6dB 1 2 3 4 5 6 7
-5dB
-4dB
-3dB
-2dB
-1dB 0dB 1dB
Command
8
9 A B C D
E
F
Gain 2dB 3dB 4dB 5dB 6dB
-
-
-
Setting of subtraction gain for 3 time sound
Default = 00h
Select Address Operational explanation
&h7E[ 2:0 ]
Command
0 -∞ 1 -12dB 2 3
Gain
-10dB
-8dB
Command
4 5 6 7
Gain
-6dB
-4dB
-2dB 0dB
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-11. P2Treble (Perfect Pure Treble:Medium・High-band equalizer
It realizes good Clearness, sound stretch, and clear-cut manner.
It realizes such an effect that the sound is raised and can be heard when speaker is located on the underside of a device.
2
ON/OFF of P
Treble function
Default = 0
Select Address Value Operational explanation
&h75 [ 7 ]
0 Not using of P2Treble function
1 Using of P2Treble function
2
Setting of P
Treble mediumhigh-band gain
Default = 0h
Select Address Operational explanation
&h76 [ 74 ]
Command Gain
0 0dB 1 2 3 4 5 6 7
+1dB +2dB +3dB +4dB +5dB +6dB +7dB
Command
8 9 A B C D E F
Gain +8dB +9dB
+10dB +11dB +12dB +13dB +14dB +15dB
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2012.03 - Rev.
BU9414FV
A
Technical Note
4-12. Scaler
Scaler adjusts the gain in order to prevent the overflow in DSP.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Scaler 1 does not incorporate the smooth transition function.
Default = 30h
Select Address Operational explanation
&h24 [ 70 ]
Command Gain
00 01 +23.5dB
30 31 32
FE FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
4-13. 7 bandparametric equalizer
77--bbaanndd ppaarraammeettrriicc eeqquuaalliizzeerr
can use Peaking filter, Low-shelf filter or high-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients b0, b1, b2, a1, a2by selecting the FQ and Gain, and
transmitted to coefficient RAM. There is no smooth transition function.
Band1 Band2 Band3 Band4 Band5 Band6 Band7
f
Level
±18dB
(0.5dB step)
63 160 400 1k 2.5k 6.3k 16k (Hz)
Selection of filter types
Default = 0
Select Address Value Operational explanation
bit[ 7:6 ]
It sets to all band
0 Peaking filter
1 Low-shelf filter
2 High-shelf filter
Setting of the Start of transmitting to coefficient RAM
It is transmitted to direct coefficient RAM.
Default = 0
Select Address Value Operational explanation
bit [ 0 ]
It sets to all band
0 Coefficient transmission stop
1 Coefficient transmission start
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2012.03 - Rev.
BU9414FV
A
Technical Note
Selection of frequency(F0)
Default = 0Eh
Select
Operational explanation
Address
bit [ 5:0 ]
It sets to all
band
Command
00 01 02 03 04 05 06 07
Frequency
20Hz 22Hz 25Hz 28Hz 32Hz 35Hz 40Hz 45Hz
Command
08 09 0A 0B 0C 0D 0E 0F
Frequency
50Hz 56Hz 63Hz 70Hz 80Hz
90Hz 100Hz 110Hz
Command
10 11 12 13 14 15 16 17
Frequency
125Hz 140Hz 160Hz 180Hz 200Hz 220Hz 250Hz 280Hz
Command
18
19 1A 1B 1C 1D 1E 1F
Frequency
315Hz 350Hz 400Hz 450Hz 500Hz 560Hz 630Hz 700Hz
Command
20 21 22 23 24 25 26 27
Frequency
800Hz 900Hz
1kHz
1.1kHz
1.25kHz
1.4kHz
1.6kHz
1.8kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
2kHz
2.2kHz
2.5kHz
2.8kHz
3.15kHz
3.5kHz 4kHz
4.5kHz
Command
30 31 32 33 34 35 36 37
Frequency
5kHz
5.6kHz
6.3kHz 7kHz 8kHz 9kHz
10kHz 11kHz
Command
38 39 3A 3B 3C 3D 3E 3F
Frequency
12.5kHz 14kHz 16kHz 18kHz 20kHz
-
-
-
Selection of quality factor(Q)
Default = 4h
Select Address Operational explanation
bit [ 3:0 ]
It sets to every band
Command
Quality factor
0 1 2 3
0.33
0.43
0.56
0.75 4 5 6 7
Command
1.0
1.2
1.5
1.8
Quality factor
8 9 A B C D E F
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address Operational explanation
bit [ 6:0 ]
It sets to every band
Command Gain
1C -18dB
3E -1dB 3F 40 41
64
-0.5dB 0dB
+0.5dB
+1dB42
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
The Select Address of each band is shown in the table below:
Band1 Band2 Band3 Band4 Band5 Band6 Band7
Selection of filter type bit [ 7:6 ]
Setting of the Start of transmitting to
&h50h &h54h &h58h &h5Ch &h60h &h64h &h68h
coefficient RAM bit [ 0 ]
Ffrequencyselection bit [ 5:0 ] &h51h &h55h &h59h &h5Dh &h61h &h65h &h69h
QQuality Factor selection bit [ 3:0 ] &h52h &h56h &h5Ah &h5Eh &h62h &h66h &h6Ah
Gain selection bit [ 6:0 ] &h53h &h57h &h5Bh &h5Fh &h63h &h67h &h6Bh
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-14. Main output EVR Electronic volume
Volume is from+24dB to -103dB, and can be selected by the step of 0.5dB. At the time of switching of Volume, smooth transition is performed. The smooth transition time takes about 22ms in the case of transiting from 0dB. (Fixed)
Setting of Volume
Default = FFh
Select Address Operational explanation
&h26 [ 70 ]
Command Gain
00 01 +23.5dB
30 31 32
FE
FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
4-15. Main output balance
Balance can be attenuated, by the step width of 1dB, from the Volume setting value. At the time of switching, smooth transition is performed. At the time of switching of Balance, smooth transition is performed. The smooth transition time takes about 22ms. (Fixed)
Setting of L/R Balance
Default = 80h
Select Address Operational explanation
&h27 [ 70 ]
Command Lch
00 01
7F 80 81
FE
-126dB
0dB 0dB
0dB 0dB
-1dB
Rch
-∞
-126dB
-1dB0dB7E 0dB 0dB 0dB
0dB 0dB-∞FF
4-16. Main output postscaler
It performs the level adjustment when the data calculated in the 32-bit-width DSP is outputted in the form of 24bitwidth.
Adjustable range is from +24dB to -103dB and can be set by the step of 0.5dB.
There is no smooth transition function in Postscaler.
Default = 30h
Select Address Operational explanation
&h28 [ 70 ]
Command Gain
00 01 +23.5dB
30 31 32
FE FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-17. 2 Band dynamic range compression
Like the explosion in TV commercials or a movie, it is the function to control volume automatically and to adjust volume so that a televiewer may not be surprised, when sound becomes large suddenly. Compression operation is performed about each two band of low-pass and a high region. Moreover, the high region builds in LPF for preventing the incorrect reaction to the pilot signal of an image.
Input
Max
A_RATE R_RATE
Output
ON/OFF low frequency DRC .
Default = 0
IN OUT
Select Address Value Operational explanation
&h18 [ 7 ]
BASS and MIDDLE frequency component is extracted.
LPF1
MIDDLE and TREBLE frequency component is extracted.
0 Use low frequency DRC
1 Not use low frequency DRC
min
DET
DET
LPF2
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
ON/OFF high frequency DRC .
Default = 0
Select Address Value Operational explanation
&h18 [ 6 ]
0 Use high frequency DRC
1 Not use high frequency DRC
Setting of LPF(LPF2) .
Default = 0
Select Address Value Operational explanation
&h19 [ 5:4 ]
0 OFF
1 1st order
2 2nd order
Setting of LPF(LPF1) .
Default = 00h
Select Address Operational explanation
&h19 [ 30 ]
Command Frequency
0 スルー 1 2 3 4 5 6 7
200Hz 400Hz 600Hz
800Hz 1000Hz 1200Hz 1400Hz
Command
8 9 A B C D E F
Frequency
1600Hz 1800Hz 2000Hz
-
-
-
-
-
Setting of low frequency A_RATE.
Default = 0h
Select Address Operational explanation
&h1A [ 64 ]
Command
0 1ms 1 2ms 2 3
Time
3ms 4ms
Command
4 5 6 7
Time
5ms 10ms 20ms 40ms
Setting of low frequency R_RATE.
Default = 0h
Select Address Operational explanation
&h1A [ 30 ]
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Command R_RATE
0 0.25s 1 2 3 4 5 6 7
0.5s
0.75s 1s
1.25s
1.5s 2s
2.5s
Command
8
9 A B C D
E
F
R_RATE
3s 4s 5s 6s 7s 8s 9s
10s
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of low frequency A_TIME.
Default = 0h
Select Address Operational explanation
&h1B [ 64 ]
Command A_TIME
0 0.5ms 1 1ms 2 3
1.5ms 2ms
Command
4 5 6 7
A_TIME
3ms 4ms 5ms 6ms
Setting of low frequency R_TIME.
Default = 0h
Select Address Operational explanation
&h1B [ 20 ]
Command R_TIME
0 50ms 1 100ms 2 3
150ms 200ms
Command
4 5 6 7
R_TIME
300ms 400ms 500ms 600ms
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
Setting of high frequency A_RATE.
Default = 0h
Select Address Operational explanation
&h1C [ 64 ]
Command
0 1ms 1 2ms 2 3
Time
3ms 4ms
Command
4 5 6 7
Time
5ms 10ms 20ms 40ms
Setting of high frequency R_RATE.
Default = 0h
Select Address Operational explanation
&h1C [ 30 ]
Command R_RATE
0 0.25s 1 2 3 4 5 6 7
0.5s
0.75s 1s
1.25s
1.5s 2s
2.5s
Command
8
9 A B C D
E
F
R_RATE
3s 4s 5s 6s 7s 8s 9s
10s
Setting of high frequency A_TIME.
Default = 0h
Select Address Operational explanation
&h1D [ 64 ]
Setting of high frequency R_TIME.
Default = 0h
Select Address Operational explanation
&h1D [ 20 ]
Command A_TIME
0 0.5ms 1 1ms 2 3
Command R_TIME
0 50ms 1 100ms 2 3
1.5ms 2ms
150ms 200ms
Command
4 5 6 7
Command
4 5 6 7
A_TIME
3ms 4ms 5ms 6ms
R_TIME
300ms 400ms 500ms 600ms
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
4-18. Main output clipper
When measuring the rated output (practical maximum output), it is measured where the total distortion rate (THD+N) is 10%. Clipping with any output amplitude is possible by using of clipper function, for example, the rated output of 10W or 5W can be obtained by using an amplifier with 15W output.
Please set the &h27[7] at “H” when using of clipper function.
Default = 0
Select Address Value Operational explanation
&h29 [ 7 ]
Clip level is set in the form of higher-order 8 bit&h2A[7:0] and lower-order 8 bit&h2B[7:0].
0 Not using clipper function
1 Using clipper function
Clip Level
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10111 1111111111111111111
01000 0000000000000000000 0 1
l becomes narrow if the setting value is reduced.
Negative clip level is set in such a way that it is the inversion data of positive clip level.
4-19. Selection of sub input data
Selection of Sub input (Sub woofer processing etc.).
The Sub woofer output interlocked with P
In addition, in BU9414FV, the data can be inputted from SP conversion2.
Default = 0
clip_level[15:0]
~clip_level[15:0]
2
Bass’s gain setting is possible by inputting the data that after P2Bass processing.
Select Address Value Operational explanation
&h2F [ 1:0 ]
0 Inputting of data that are after scaler 1
1 Inputting of data that are after P2Bass processing
2 Inputting of data from SP conversion2
0000000 1111111
Maximum value
Minimum value
A positive clip level A negative clip level
Technical Note
The
clip
leve
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2012.03 - Rev.
BU9414FV
A
Technical Note
4-20. Sub output EVR (electronic volume)
The volume for sub output can select with 0.5dB step from +24dB to -103dB. When changing volume, smooth transition is done. Smooth transition duration is required approximately 22ms when it is from 0dB. (Fixed)
Volume setting
Default = FFh
Select Address Operating explanation
&h2C [ 70 ]
Command Gain
00 01 +23.5dB
30 31 32
FE FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
4-21. Sub output balance
As for sub output balance, it is possible to be attenuated at 1dB step width from volume setting value. When changing, smooth transition is done. When changing balance, smooth transition is done. Smooth transition duration is required approximately 22ms. (Fixed) L/R Balance setting
Default = 80h
Select Address Operating explanation
&h2D [ 70 ]
Command Lch
00 01
7F 80 81
FE
0dB 0dB
0dB 0dB
-1dB
-126dB
Rch
-∞
-126dB
-1dB0dB7E 0dB 0dB 0dB
0dB 0dB-∞FF
4-22. Sub output post scaler
The occasion when the data which is calculated with DSP of 32bit width is output at 24bit width, level adjustment is done.
The adjustment range can be set with 0.5dB step from +24dB to -103dB.
There is no smooth transition function in the sub output post scaler.
Default = 30h
Select Address Operating explanation
&h2E [ 70 ]
Command Gain
00 01 +23.5dB
30 31 32
FE FF
+24dB
0dB
-0.5dB
-1dB
-103dB
-∞
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2012.03 - Rev.
BU9414FV
A
4-26. Sub output clipper
The case when rated output (practical maximum output) of the television is measured, total harmonic distortion + noise (THD+N) measures at the place of 10%. It can obtain the rated output of 10W and 5W for example making use of the amplifier of 15W output, because it is possible to clip with optional output amplitude by using the clipper function.
Please designate &h30 [7] as” H when using sub output clipper function.
Default = 0
Select Address Value Operating explanation
&h30 [ 7 ]
As for clip level, it sets with superior 8 bits &h31 [7: 0] and subordinate 8 bits &h32 [7: 0].
0 Clipper function is not used
1 Clipper function is used
Clip Level
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10111 1111111111111111111
01000 0000000000000000000 0 1
g value is made small, clip level becomes narrow.
As for negative clip level, the reversal data of positive clip level is set.
clip_level[15:0]
~clip_level[15:0]
0000000 1111111
Maximum value
Minimum value
A positive clip level A negative clip level
Technical Note
When
settin
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2012.03 - Rev.
BU9414FV
A
Technical Note
4-27. Direct setting five coefficient of b0, b1, b2, a1 and a2 of Bi-quad Filter
7 bands Parametric Equalizer of main output and of 3 bands Parametric Equalizer of sub output have used the secondary
IIR type digital filter (Bi-quad Filter).
It is possible to set five coefficient 24 bit of b0, b1, b2, a1 and a2 of Bi-quad Filter (-4+4) directly from an external.
When this function is used, it can do the filter type and frequency setting, Q value (quality factor) setting and gain setting
other than Peaking, Low-Shelf and High-Shelf unrestrictedly.
(Note) five coefficient have the necessity to make below the ±4, there is no read-out function of setting value and an
automatic renewal function of coefficient RAM.
Register for the coefficient transfer of 24bit
Before transferring into coefficient RAM in a lumping, the data is housed in the register for coefficient transfer from the
micro-computer.
Default = 00h
Select Address Operating explanation
&h8D [ 7:0] bit[23:16] which transfers 24 bit coefficient
&h8E [ 7:0] bit[15:8] which transfers 24 bit coefficient
&h8F [ 7:0] bit[7:0] which transfers 24 bit coefficient
It starts to transmit the coefficient of 24bit into coefficient RAM
Default = 0
Select Address Value Operating explanation
&h8C [ 7 ]
0 Coefficient transmission stop
1 Coefficient transmission start
Coefficient number appointment of coefficient RAM
Default = 00h
Select Address Operating explanation
&h8C [ 6:0] Coefficient number appointment of coefficient RAM
Appointment of coefficient number other than 14H45H is prohibition
Main output 7Band Parametric EQ
-1
Z
-1
Z
Coefficient
number
14
H.
b0
+
+ +
15
16
H.
17
H.
BAND1 (Main)
H
a1b1
+ +
18
H
a2b2
Sub output 3Band Parametric EQ
Coefficient
37
H.
b0
-1
Z
38
H.
-1
Z
39
H.
Coefficient
19
b0
-1
-1
Z
Z
1A
-1
-1
Z
Z
1B
number
+
+ +
+ +
BAND1 (Sub) BAND2 (Sub) BAND3 (Sub)
Coefficient
number
H.
+ +
-1
Z
1C
+ +
-1
Z
-1
Z
1D
Z
Z
H
a1b1
Z
H
a2b2
Coefficient
3C
b0
-1
3D
-1
3E
-1
H.
H.
BAND2 (Main) BAND3 (Main) BAND4 (Main) BAND5 (Main) BAND6 (Main) BAND7 (Main)
3A
H
a1b1
3B
H
a2b2
number
1E
H.
b0
+ +
-1
Z
1F
H.
+ +
-1
Z
20
H.
number
H.
+ +
H.
H.
+ +
3F
a1b1
40
a2b2
21
a1b1
22
H
a2b2
-1
Z
H
-1
Z
H
Coefficient
number
23
H.
b0
+ +
-1
-1
Z
Z
Z
-1
Z
Z
-1
Z
Coefficient
41
b0
-1
42
-1
43
24
H.
25
H.
number
H.
H.
H.
H
26
+ +
27
+
44
+ +
45
Coefficient
number
28
H.
b0
-1
-1
Z
Z
H
a1b1
H
a2b2
29
-1
-1
Z
Z
2A
-1
Z
H
a1b1
-1
Z
H
a2b2
+ +
H.
H.
2B
+ +
2C
Coefficient
number
2D
H.
b0
+ +
-1
-1
Z
Z
H
a1b1
H
a2b2
2E
H.
-1
-1
Z
Z
2F
H.
+ +
30
a1b1
31
a2b2
Coefficient
number
32
H.
b0
-1
-1
Z
Z
H
H
33
H.
+ +
-1
-1
Z
Z
34
H.
+
-1
Z
35
H
a1b1
-1
Z
36
H
a2b2
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© 2012 ROHM Co., Ltd. All rights reserved.
2012.03 - Rev.
BU9414FV
A
Technical Note
4-28. About the automatic renewal of five coefficients of b0, b1, b2, a1 and a2 of Bi-quad Filter
BASS, MIDDLE, TREBLE, main output 7 bands Parametric Equalizer and sub output 3 band Parametric Equalizer have
used coefficient RAM. As for this coefficient RAM, because direct access is not possible from the micro-computer, it cannot
refresh the register efficiently.
There is an automatic renewal function of coefficient RAM in this DSP, the automatic write-in renewal of coefficient RAM is
possible by using this function. However when 4-26 the function of direct setting a coefficient RAM is utilized, it is not
possible to utilize automatic write-in renewal.
Selection of using the automatic write-in renewal function
Default = 0
Select Address Value Operating explanation
&h6D [ 0 ]
0 Automatic write-in renewal function is used
1 Automatic write-in renewal function is not used
The separate setting of Filter of automatic write-in renewal function
Default = 00h
Select Address Filter Operating explanation
&h6E [ 0 ] BASS 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6E [ 1 ] MIDDLE 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6E [ 2 ] TREBLE 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 0 ] Main MAND1 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 1 ] Main MAND2 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 2 ] Main MAND3 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 3 ] Main MAND4 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 4 ] Main MAND5 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 5 ] Main MAND6 0:Automatic renewal function OFF
1Automatic renewal function ON
&h6F [ 6 ] Main MAND7 0:Automatic renewal function OFF
1Automatic renewal function ON
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2012.03 - Rev.
BU9414FV
A
Technical Note
5. P-S conversion 1 ,P-S conversion 2
Two parallel serial conversion circuits are built in BU9414FV. (P-S conversion 1, P-S conversion 2)
P-S conversion 1 convert the Main output of DSP from SDATAO1, LRCKO, and BCKO (34,35,36pin) into three line serial
data and output the data.
P-S conversion 2 convert the sub output of DSP from SDATAO1, LRCKO, and BCKO (33,35,36pin) into three line serial data
and output the data.
Output format has the IIS mode, left-align mode, and right-align mode. 16 each bit, 20bit, and 24bit output can also be
selected. The figure below shows the timing chart of each transmission mode.
IIS mode
IIS方
LRCKO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKO
MSB LSB
S
DATAO
16bit
MSB LSB
S
16bit
20bit
24bit
20bit
24bit
left-align mode
詰方式
LRCKO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKO
MSB LSB
S
DATAO
16bit
20bit
24bit
MSB LSB
S
16bit
20bit
24bit
right-align mode
詰方式
LRCKO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCKO
DATAO
MSB LSB
S
16bit
20bit
24bit
MSB LSB
S
16bit
20bit
24bit
5-1. Format setting of three line serial output
Default = 0
Select Address Value Operating Description
P-S conversion 1 &h0D [ 3:2 ]
P-S conversion 2
& h0E [ 3:2 ]
0 IIS mode
1 left-align mode
2 right-align mode
5-2. Setting data bit width of three line serial output
Default = 0
Select Address Value Operating Description
P-S conversion 1 &h0D [ 1:0 ]
P-S conversion 2
& h0E [ 1:0 ]
0 16 bit
1 20 bit
2 24 bit
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2012.03 - Rev.
BU9414FV
A
Technical Note
6. Mute function by command
Mute function by command is provided in BU9414FV.
It's possible to mute DSP's main and sub digital output by setting to &hF4 [ 4 ] = 1h and MUTEX_DAC terminal and a
MUTEX_SP terminal both to L.
Setting the transition time of smooth mute
Mute the Main and Sub output of DSP.
Select the transition time of entering from 0dB to mute state.
Smooth transition time when releasing mute is about 22ms(fixed) .
Default = 0
Select Address Value Operating Description
&h10 [ 10 ]
0 Don’t use mute function.
1 10.8ms
2 5.4ms
3 2.7ms
Soft mute release time setup
Setting of soft mute release start time from detect soft mute release state
Default = 0
Select Address Value Operating Description
&h10 [ 76 ]
0 0ms
1 100ms
2 200ms
3 300ms
7. Clock halt function of DSP part
Clock halt function of DSP part with terminal MUTEX_DAC and MUTEX_SP is provided in BU9414FV.
Clock halt function’s setting
Default = 0
Select Address Value Operating Description
&hA9 [ 7 ]
0 Don’t use the clock halt function
1 Use the clock halt function
When setting on using the clock halt function, then set the MUTEX_DAC and MUTEX_SP terminal on L ,the clock of DSP
part will be halted. If clock is halted, command can’t be sent and received in a part of the block. If &hA9 [ 7 ] is input from
MCLK into clock, command can be sent and received even on the clock halt condition.
When MUTEX_DAC or MUTEX_SP terminal is on H, the clock halt will be released.
Power consumption decreases in the clock halt condition.
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2012.03 - Rev.
BU9414FV
A
Technical Note
8. Command sent after releasing reset
Please send the following command after releasing reset including power supply on.
0. Power supply turning on
Please input the clock from the outside. When the clock is not input, reset can't normally be done.
1. Reset release (RESETB="H")
2. &hA0[7:0] = C2h :Set PLLA.
3. &hF3[5:0] = 08h :Set the dividing frequency ratio of MCLK. Please do as follows to set a value by fs of
MCLK.
MCLK:512fs=08h256fs=04h128fs=02h
4. &hF5[3:0] = 01hSet the dividing frequency ratio of PLL.
5. &hF6[7:0] = 00hSet the phase adjust command of PLL.
6. &hF1[4] = 0Enable analog input.
7. &h08[5:4] = 1h :Select system clock is PLL.
8. &hA7[7:0] = F4hSynchronous detection condition setting 1 for PLLA is initialized.
9. &hA8[7:0] = 33hSynchronous detection condition setting 2 for PLLA is initialized.
10. &hA9[3:0] = 3hSynchronous detection condition setting 3 for PLLA is initialized.
11. &hA9[5:4] = 2h or 1h or 0h :Set MCLK.
(Set in “2h”While MCLK is 512fs, set in “1h”While MCLK is 256fs, set in “0h”While MCLK is 128fs.)
It is about 10ms wait until PLL is steady.
12. &hAA[7:0] = 80h :A data taking-in position is adjusted.
13. Read back &hAA[7] address data and check read result is 0.
It is about 5ms wait until RAM all address clear.
14.&h01 = 00h : Set ram clear off.
15. Other register setting
&h26[7:0] = **h :Release the mute of the Main output volume(30h=0dB
&h2C[7:0] = **h :Rel
ease the mute of the Sub output volume(30h=0dB).
.
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2012.03 - Rev.
BU9414FV
A
Technical Note
9. About frequency setting such as tone control and parametric equalizer
Because the sampling rate converter is not built into BU9414FV, the calculation clock of DSP is changed according to the
input sampling rate of I2S.
Because sampling rate describes the frequency on the assumption of 48kHz in this function specification, conversion is
needed in case of sampling frequency of 44.1kHz and 32kHz.
Please refer to the table below for F0 setting of tone control (Bass, Middle, Treble) and parametric equalizer.
F0 (fs=48kHz)
Command
00 01 02 03 04 05 06 07
Frequency
20Hz 22Hz 25Hz 28Hz 32Hz 35Hz 40Hz 45Hz
Command
0C
08 09 0A 0B
0D 0E 0F
Frequency
50Hz 56Hz 63Hz 70Hz 80Hz
90Hz 100Hz 110Hz
Command
10 11 12 13 14 15 16 17
Frequency
125Hz 140Hz 160Hz 180Hz 200Hz 220Hz 250Hz 280Hz
Command
18 19 1A 1B 1C 1D 1E 1F
Frequency
315Hz 350Hz 400Hz 450Hz 500Hz 560Hz 630Hz 700Hz
Command
20 21 22 23 24 25 26 27
Frequency
800Hz 900Hz
1kHz
1.1kHz
1.25kHz
1.4kHz
1.6kHz
1.8kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
2kHz
2.2kHz
2.5kHz
2.8kHz
3.15kHz
3.5kHz 4kHz
4.5kHz
Command
30 31 32 33 34 35 36 37
Frequency
5kHz
5.6kHz
6.3kHz 7kHz 8kHz 9kHz
10kHz 11kHz
Command
38 39 3A 3B 3C 3D 3E 3F
Frequency
12.5kHz 14kHz 16kHz 18kHz 20kHz
-
-
-
F0 (fs=44.1kHz)
Command
00 01 02 03 04 05 06 07
Frequency
18Hz 20Hz 23Hz 26Hz 29Hz 32Hz 37Hz 41Hz
Command
08
09 0A 0B 0C 0D
0E
0F
Frequency
46Hz 51Hz 58Hz 64Hz 74Hz 83Hz 92Hz
101Hz
Command
10 11 12 13 14 15 16 17
Frequency
115Hz 129Hz 147Hz 165Hz 184Hz 202Hz 230Hz 257Hz
Command
18
19 1A 1B 1C 1D
1E
1F
Frequency
289Hz 322Hz 368Hz 413Hz 459Hz 515Hz 579Hz 643Hz
Command
20 21 22 23 24 25 26 27
Frequency
735Hz 827Hz 919Hz
1.01kHz
1.15kHz
1.29kHz
1.47kHz
1.65kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
1.84kHz
2.02kHz
2.3kHz
2.57kHz
2.89kHz
3.22kHz
3.68kHz
4.13kHz
Command
30 31 32 33 34 35 36 37
Frequency
4.59kHz
5.15kHz
5.79kHz
6.43kHz
7.35kHz
8.27kHz
9.19kHz
10.1kHz
Command
38
39 3A 3B 3C 3D
3E
3F
Frequency
11.5kHz
12.9kHz
14.7kHz
16.5kHz
18.4kHz
-
-
-
F0 (fs=32kHz)
Command
00 01 02 03 04 05 06 07
Frequency
13Hz 15Hz 17Hz 19Hz 21Hz 23Hz 27Hz 30Hz
Command
08 09 0A 0B
0C
0D 0E 0F
Frequency
33Hz 37Hz 42Hz 47Hz 53Hz 60Hz 67Hz 73Hz
Command
10 11 12 13 14 15 16 17
Frequency
83Hz
93Hz 107Hz 120Hz 133Hz 147Hz 167Hz 187Hz
Command
18 19 1A 1B 1C 1D 1E 1F
Frequency
210Hz 233Hz 267Hz 300Hz 333Hz 373Hz 420Hz 467Hz
Command
20 21 22 23 24 25 26 27
Frequency
533Hz 600Hz 667Hz 733Hz 833Hz 933Hz
1.07kHz
1.2kHz
Command
28 29 2A 2B 2C 2D 2E 2F
Frequency
1.33kHz
1.47kHz
1.67kHz
1.87kHz
2.1kHz
2.33kHz
2.67kHz 3kHz
Command
30 31 32 33 34 35 36 37
Frequency
3.33kHz
3.73kHz
4.2kHz
4.67kHz
5.33kHz 6kHz
6.67kHz
7.33kHz
Command
38 39 3A 3B 3C 3D 3E 3F
Frequency
8.33kHz
9.33kHz
10.7kHz 12kHz
13.3kHz
-
-
-
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2012.03 - Rev.
BU9414FV
A
Technical Note
10. About a setup of a clock, and the input of a command
The input of MCLK is decided by combination of three kinds of sampling rates (fs=32kHz, 44.1kHz, 48kHz), and three kinds
of magnifications (128 times, 256 times, 512 times).
Sampling rate(fs)
MCLK clock 32kHz 44.1kHz 48kHz
128fs 4.096MHz 5.6448MHz 6.144MHz
256fs 8.192MHz 11.2896MHz 12.288MHz
512fs 16.384MHz 22.5792MHz 24.576MHz
In order that PLL may multiple the dividing output of MCLK, the dividing ratio of MCLK is not concerned with a sampling rate
like explanation in Chapter 8, but is decided by the magnification of MCLK.
MCLK clock &hF3[5:0]
128fs 04h
256fs 08h
512fs 10h
Therefore, as for the case of the input of 4.096MHz-6.144NHz, and a 256fs setup, in the input frequency of MCLK, in a 128fs setup, a 16.384MHz - 24.576MHz input serves as a range which can be operated in a 8.192MHz - 12.288MHz input and a 512fs setup.
MCLK
I2C
CONTROL LOGIC
&hF3[5:0]
DIV
PLLA PLL_DIV
DSP
S E L 1
AUDIO IF
ERROR_DET
BU9414FV Clock line
&h08[5:4]
S E L 2
SYSCLKO
The clock system figure of BU9414FV is as mentioned above. (1) In the case of &h08 [5:4] =1, the block of an above figure light blue operates with a PLL clock. (2) In the case of &h08 [5:4] =0, the block of an above figure light blue operates by MCLK.
Be careful of the following points at the time of a command input. In (1), a part of blocks containing DSP are operating with the clock of PLL. Therefore, even if MCLK is the range which is 4.096MHz - 24.576MHz, when a setup of PLL and the setup of &hF3 are not performed correctly, a command may not be received other than command &h08 of a system control system, &hA0-&hA9, &hB0-&hBA, &hD0, &hF0 - &hFA. In (2), the whole operates with the clock of MCLK. If MCLK is the range which is 4.096MHz - 24.576MHz, all blocks will receive an I2C command.
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2012.03 - Rev.
BU9414FV
A
Technical Note
11. About the change of a sampling rate
11- 1. When a sampling rate change can predict beforehand
When the change of a sampling rate can predict beforehand, please switch a sampling rate in the following procedures.
1The mute of the DAC is carried out (MUTEX_SP and MUTEX_DAC are set to L and it is a mute about BD5446.).
2. EVR is set as -infinity.
3. Set prescaler as -infinity.
4. A RAM clearance is carried out by setting it as &h01= C0h.
5. &h08[5:4] = by setting it as 0, the whole clock is switched to MCLK.
6. Switch a sampling rate.
7. Switch to a PLL clock after stabilizing the input of MCLK by setting it as more 10 msec WAIT and &h08 [5:4] =1h, since it is PLL stability.
8. &hAA[7:0] = 80h :A data taking-in position is adjusted.
9. Read back &hAA[7] address data and check read result is 0.
It is about 5ms wait until RAM all address clear.
10.&h01 = 00h : Set ram clear off.
↓↓
11. Since the coefficient is cleared, please set up DSP.
12. Please cancel a DAC mute.
11- 2. When a sampling rate change cannot predict beforehand
Please do the following work, when the change of a sampling rate cannot predict beforehand, and having switched is detected.
1The mute of the DAC is carried out (MUTEX_SP and MUTEX_DAC are set to L and it is a mute about BD5446.).
When the input of MCLK has stopped, please do not input a command until MCLK is inputted again.
Please perform the following setup, after MCLK is inputted on the frequency of specification within the limits.
2 It is set as &h08[5:4] = 0 and the whole clock is switched to MCLK.
3Switch to a PLL clock after stabilizing the input of MCLK by setting it as more 10 msec WAIT and &h08 [5:4] =1h,
since it is PLL stability.
4A RAM clearance is carried out by setting it as &h01= C0h.
EVR is set as -infinit
5
y.
6Prescaler is set as -infinity.
7. &hAA[7:0] = 80h :A data taking-in position is adjusted.
8. Read back &hAA[7] address data and check read result is 0.
It is about 5ms wait until RAM all address clear.
9.&h01 = 00h : Set ram clear off.
10Since the coefficient is cleared, please set up DSP.
11Please cancel a DAC mute.
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2012.03 - Rev.
BU9414FV
A
Technical Note
11- 3. When the frequency more than a stop or the specification range does not enter [ MCLK ] at the time of a sampling rate change
When switching a sampling rate, the clock of the frequency more than the specification range does not go into MCLK,
but when input data is 0, it can return with the following procedures.
1. Carry out the mute of the DAC (MUTEX_SP and MUTEX_DAC are set to L and it is a mute about BD5446.)
When the input of MCLK has stopped, please do not input a command until MCLK is inputted again.
Please perform the following setup, after MCLK is inputted on the frequency of specification within the limits.
2. It is 10ms or more WAIT because of PLL stability.
When the section where MCLK stopped or the relation with I2S input had collapsed in the midst of the midst of soft
transition and transmission of a coefficient exists, the coefficient may not be able to be transmitted well. When soft transition and a coefficient are transmitting, please perform a setup from 11-2 4. Please perform the following setup, when you are not the midst of soft transition or transmission of a coefficient.
3. &hAA[7:0] = 80h :A data taking-in position is adjusted.
4. Read back &hAA[7] address data and check read result is 0.
5. Please cancel a DAC mute.
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2012.03 - Rev.
BU9414FV
A
Technical Note
12. When the clock which exceeded the specification range from MCLK is inputted
When the frequency beyond fs=48kHz is inputted from
Frequency
MCLK in the state where it was set as &h08 [5:4] =1, since
PLL follows inputted MCLK, as shown in the right figure,
when it exceeds Time Ter, it will exceed the frequency in
which DSP can operate.
In this case, an allophone may carry out irrespective of the
existence of data.
PLL output frequency
The frequency limit that DSP can operate
When you change into such a state, please carry out the
mute of the DAC immediately, apply reset (RESETB=L), and
do the work after reset release of Chapter 8.
48kHz
MCLK inputted frequency
The time of Ter serves as about 70 usec.
Ter
Time
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2012.03 - Rev.
BU9414FV
A
Technical Note
13. Audio Interface Signal Specification
Electric specification and timing of MCK, BCK, LRCK, and SDATA1 and SDATA2
MCLK
1/fMCLK
LRCK
1/fLRCK
BCK
LRCK
BCK
SDATA1,SDATA2
tBLRDG
tBCK
tBCK H tBCKL
Fig 1-2 Clock timing
tLBRD G
tSU;SD
Fig 1-3 Audio interface timing
tHD;SD
Parameter Sign Unit
1
MCK
2 DUTY dSCLK 40 60 %
3
LRCK
4 DUTY dLRCK 40 60 %
5
BCK
6 H width tBCKH 130 - ns
Frequency fSCLK 4.096 24.576 MHz
Frequency fLRCK 32 48 kHz
Cycle tBCK 325 - ns
Min. Max.
7 L width tBCKL 130 - ns
8 It is time to the edge of LRCK from a BCK rising edge.*1 tBLRDG 20 ns
9 It is time to a BCK rising edge from the edge of LRCK.*1 tLBRDG 20 - ns
10 Setup time of SDATA tSU;SD 20 - ns
11 Hold time of SDATA tHD;SD 20 ns
*1 This standard value has specified that the edge of LRCK and the rising edge of BCK do not overlap.
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2012.03 - Rev.
BU9414FV
A
Technical Note
14. Notes at the Time of Res et
Since the state of IC is not decided, please make it into RESETX=L at the time of a power supply injection, and surely apply
reset.
Reset of BU9414FV is performing noise removal by MCLK.
Therefore, in order to apply reset, a MCLK clock pulse is required of the state of RESETX=L more than 10 times.
The power-on reset after a power supply injection, and when you usually apply reset at the time of operation, please be sure
to carry out in the state where the clock is inputted, from MCLK.
15. Read-out of Soft Transition Flag
It is set to &hF4[0] =H, &hFD[0]=H when BASS, MIDDLE, TREBLE or P2Bass, and P2Treble are soft transiting.
It is possible to check whether soft transition is completed by reading &hF4 [0]or &hFD[0]
Soft transition will be completed if the read-out result of &hF4 [0] or &hFD [0] is L.
16. Data taking-in position adjustment circuit
There is a circuit which adjusts the position of data taking in so that data can be received, even when the incoming signal is
shaking by jitter.
DSP clock use multiplied input clock by PLL.
Even when I2S signal inputted is shaking by jitter, the taking-in position of data is adjusted to the position which has a margin most so that take data and they may not be spilt. Adjust a data taking-in position by making it &hAA[7] =H. The read-out value of &hAA[7] is set to H during adjustment of a data taking-in position. It reads, after adjustment of a data taking-in position finishes, and a value is set to L. The reset release back, the time of an input sampling rate change, etc. adjust, when the lock state of PLL changes. Please refer to the recommendation procedure of Chapter 8 and Chapter 11 for details. When there is no margin in the data taking-in position of DSP, the read-out value of &hAA[3] is set to H. & Once hAA [3] is set to H, it will read until it adjusts a data taking-in position or writes 0 in &hAA[3], and a value will not be set to L.
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2012.03 - Rev.
BU9414FV
A
Technical Note
Operational Notes
(1) ABSOLUTE MAXIMUM RATINGS
Permanent device damage may occur and break mode (open or short) can not be specified if power supply, operating temperature, and those of ABSOLUTE MAXIMUM RATINGS are exceeded. If such a special condition is expected, components for safety such as fuse must be used.
(2)Regarding of SCLI and SDAI terminals
SCLI and the SDAI terminal do not support 5 V-tolerant. Please use it within absolute maximum rating (4.5V).
(3) Power Supply
Power and Ground line must be designed as low impedance in the PCB. Print patterns if digital power supply and analog power supply must be separated even if these have same voltage level. Print patterns for ground must be designed as same as power supply. These considerations avoid analog circuits from the digital circuit noise. All pair of power supply and ground must have their own de-coupling capacitor. Those capacitor should be checked about their specification, etc. (nominal electrolytic capacitor degrades its capacity at low temperature) and choose the constant of an electrolytic capacitor.
(4) Functionality in the strong electro-magnetic field
Malfunction may occur if in the strong electro-magnetic field.
(5) Input terminals
All LSI contain parasitic components. Some are junctions which normally reverse bias. When these junctions forward bias, currents flows on unwanted path, malfunction or device damage may occur. To prevent this, all input terminal voltage must be between ground and power supply, or in the range of guaranteed value in the Electrical characteristics. And no voltage should be supplied to all input terminal when power is not supplied.
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2012.03 - Rev.
BU9414FV
A
Technical Note
Ordering Information
B U 9 4 1 4 F
Part Number
Package FV: SSO-B40
Physical Dimension Tape and Reel Information
SSOP-B40
13.6 ± 0.2
(MAX 13.95 include BURR)
40
21
1.8 ± 0.1
7.8 ± 0.3
5.4 ± 0.2
1
0.1
0.65
0.22 ± 0.1
0.08
20
M
0.5 ± 0.2
0.15 ± 0.1
0.1 S
(Unit : mm)
Marking Diagram(s)(TOP VIEW)
V
Packaging and forming specification E2: Embossed tape and reel
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction of feed
2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
E2
1pin
Order quantity needs to be multiple of the minimum quantity.
Direction of feed
BU9414F
Lot No.
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2012.03 - Rev.
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specications, which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.
The Products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu­nication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel­controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specied herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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