●Description
These devices control are simple. It requires only 3.3V source and a few GPIO controls.
Termination resistors (50Ω) are integrated at all TMDS input port. When channel is not selected, TMDS input termination
resistors are turned off and TMDS inputs are high impedance. These devices are also integrated equalizer circuit to adapt
long cable and DDC active buffer function to isolate capacitance.
●Features
1) Supports 2.25 Gbps signaling rate for 480i/p, 720p, and 1080i/p resolution to 12-bit color depth
●Absolute Maximum Rating
Over operating free-air temperature range (unless otherwise noted)
Item Limits
BU16006KVBU16018KVBU16024KVBU16027KV
Unit
Power supply voltage(Vcc) -0.3~+4.5 -0.3~+4.5 -0.3~+4.5 -0.3~+4.5 V
DDC, HPD_SINK input voltage -0.3~+5.6 -0.3~+5.6 -0.3~+5.6 -0.3~+5.6 V
Differential input voltage +2.5~+4.0 +2.5~+4.0 +2.5~+4.0 +2.5~+4.0 V
Control pin input voltage -0.3~+4.0 -0.3~+4.0 -0.3~+4.0 -0.3~+4.0 V
Power dissipation 1000(*1) 1200(*2) 950(*3) 1000(*1) mW
Strage temperture range -55~+125 -55~+125 -55~+125 -55~+125 ℃
(*1-3) 70mm×70mm×1.6mm glass epoxy board mount.(Reverse Cu occupation rate:15mm×15mm)
(*1) When it’s used by than Ta=25℃, it’s reduced by 10.0mW/℃.
(*2) When it’s used by than Ta=25℃, it’s reduced by 12.5mW/℃.
(*3) When it’s used by than Ta=25℃, it’s reduced by 9.5mW/℃.
●Recommended Operating Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage 3 3.3 3.6 V
TA Free-air temperature 0 - 70 ℃
TMDS Differential Pins
VIC Input common mode voltage, see Figure 2. VCC–0.6- VCC+0.01V
V
Resistor for TMDS compliant voltage swing range 4.60 4.64 4.68 k Ω
VSADJ
AVCC TMDS Output termination voltage, see Figure 1. 3 3.3 3.6 V
RT Termination resistance, see Figure 1. 45 50 55 Ω
Signaling rate - - 2.25 Gbps
Control Pins
VIH LVTTL High-level input voltage 2 - VCC V
VIL LVTTL Low-level input voltage GND - 0.8 V
HPD_SINK
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage GND - 0.8 V
RX (SDA[n],SCL[n])
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage GND - 0.8 V
TX (SCL_SINK, SDA_SINK)
VIH High-level input voltage 1.5 - 5.5 V
VIL Low-level input voltage GND - 0.35 V
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) See Figure 4
Technical Note
Limits Unit
Max.
ps
ps
ps
ps
ps
ps
t
pdLHTR(DDC)
Propagation delay time, low to high level
output Tx to Rx
= 4.7kΩ, CL = 100pF,
R
L
- 650 - ns
see Figure 5
t
pdHLTR(DDC)
t
pdLHRT(DDC)
t
pdHLRT(DDC)
tr Tx
DDC
tf Tx
DDC
tr Rx
DDC
tf Rx
DDC
Propagation delay time, high to low level
output Tx to Rx
Propagation delay time, low to high level
output Rx to Tx
Propagation delay time, high to low level
output Rx to Tx
Tx output Rise time
Tx output Fall time - 150 - ns
Rx output Rise time
Rx output Fall time - 50 - ns
R
= 1.67kΩ, CL = 400pF,
L
see Figure 5
R
= 4.7kΩ, CL = 100pF,
L
see Figure 5
R
= 1.67kΩ
L
C
= 400pF
L
- 200 - ns
- 500 - ns
- 350 - ns
- 800 - ns
- 950 - ns
tsx Select to switch output see Figure 4 - 8 - ns
t
Disable time see Figure 4 - 5 - ns
dis
ten Enable time see Figure 4 - 7 - ns
t
Switch time from SCLn to SCL_SINK CL=10pF - 800 - ns
sx(DDC
CIO Input/output capacitance VI=0V - 15 - pF
Hot Plug Detect Pins
t
pdLH(HPD)
t
pdHL(HPD)
t
sx(HPD)
Propagation delay time, low to high level
output from HPD_SINK to HPDn(n=1,2,3)
Propagation delay time, high to low level
output from HPD_SINK to HPDn(n=1,2,3)
Switch time from port select to the latest
valid status of HPD
CL=10pF - 5 - ns
CL=10pF - 5 - ns
=10pF - 8 - ns
C
L
Note: (1). All typical values are at 25℃ and with a 3.3V supply.
A1 1, A12, A13, A14 6, 9, 12, 15 I Port 1 TMDS positive inputs
A21, A22, A23, A24 68, 71, 74, 77 I Port 2 TMDS positive inputs
A31, A32, A33, A34 49, 52, 55, 58 I Port 3 TMDS positive inputs
B11, B12, B13, B14 5, 8, 11, 14 I Port 1 TMDS negative inputs
B21, B22, B23, B24 67, 70, 73, 76 I Port 2 TMDS negative inputs
B31, B32, B33, B34 48, 51, 54, 57 I Port 3 TMDS negative inputs
GND
4, 10, 16, 24, 30, 36, 37, 47,
53, 59, 65, 66, 72, 78
- Ground
HPD1 80 O Port 1 hot plug detector output
HPD2 62 O Port 2 hot plug detector output
HPD3 44 O Port 3 hot plug detector output
HPD_SINK 40 I Sink side hot plug detector input
TEST0,1,2,3
______
OE
42 I Output enable, active low
PRE 19 I
1, 20, 41, 60 Open or GND connect (recommend)
TMDS high speed mode SW High : ON, Low : OFF
(above 165MHz recommend to High)
SCL1 3 I/OSource port 1 DDC I2C clock line
SCL2 64 I/OSource port 2 DDC I2C clock line
SCL3 46 I/OSource port 3 DDC I2C clock line
SCL_SINK 38 I/O
Sink port DDC I2C clock line
SDA1 2 I/OSource port 1 DDC I2C data line
SDA2 63 I/OSource port 2 DDC I2C data line
SDA3 45 I/OSource port 3 DDC I2C data line
SDA_SINK 39 I/OSink port DDC I2C data line
S1, S2, S3 21, 22, 23 I Source selector input
VCC
7, 13, 17, 27, 33, 43, 50, 56,
61, 69, 75, 79
- Power supply
VSADJ 18 I TMDS voltage swing control. Connect to GND 4.64KΩ
Y1, Y2, Y3, Y4 34, 31, 28, 25 O TMDS positive outputs
Z1, Z2, Z3, Z4 35, 32, 29, 26 O TMDS negative outputs
A11, A12, A13, A14 39, 42, 45, 48 I Source port 1 TMDS positive inputs
A21, A22, A23, A24 54, 57, 60, 63 I Source port 2 TMDS positive inputs
A31, A32, A33, A34 5, 8, 11, 14 I Source port 3 TMDS positive inputs
B11, B12, B13, B14 38, 41, 44, 47 I Source port 1 TMDS negative inputs
B21, B22, B23, B24 53, 56, 59, 62 I Source port 2 TMDS negative inputs
B31, B32, B33, B34 4, 7, 10, 13 I Source port 3 TMDS negative inputs
GND 3, 9, 15, 22, 28, 43, 58 - Ground
HPD1 35 O Source port 1 hot plug detect or output (statu s pin)
HPD2 50 O Source port 2 hot plug detect or output (statu s pin)
HPD3 64 O Source port 3 hot plug detect or output (statu s pin)
HPD_SINK 31 I Sink port hot plug detector input (status pin)
Reserve1 34 I/OIn High, Low, and Open, any setting is OK.
Reserve2 49 I/ONon Connect Pin
SCL1 37 I/OSource port 1 DDC I2C clock line
SCL2 52 I/OSource port 2 DDC I2C clock line
SCL3 2 I/OSource port 3 DDC I2C clock line
SCL_SINK 29 I/OSink port DDC I2C clock line
SDA1 36 I/OSource port 1 DDC I2C data line
SDA2 51 I/OSource port 2 DDC I2C data line
SDA3 1 I/OSource port 3 DDC I2C data line
SDA_SINK 30 I/OSink port DDC I2C data line
S1, S2 32, 33 I Source selector
Vcc
6, 12, 19, 25, 40, 46, 55,
61
- Power supply
VSADJ 16 I TMDS voltage swing control (via 4.64kΩ to GND)
Y1, Y2, Y3, Y4 26, 23, 20, 17 O Sink port TMDS positive outputs
Z1, Z2, Z3, Z4 27, 24, 21, 18 O Sink port TMDS negative outputs
1). Attention on use as “repeater” or “source” equipment.
Y and Z terminals are connected to Vcc through ESD diode as Figure 7. When Vcc+0.4 < AVcc, leak current flows from
AVcc to Vcc. For this current, BU16006KV/BU16027KV can’t pass the compliance test as “Repeater” and “Source”
equipment (Test ID 7-3 VOFF). BU16018KV/BU16024KV is able to pass the compliance test using external element lik e
Figure 8
Vcc=0V
Vcc=0V
Ym
Voff
50
AVcc=3.3V
Technical Note
Ioff
50
Ioff
Zm
AVcc=3.3V
Voff
Figure 7 TMDS Equivalent output schematic
Figure 8 Leak current control in BU16018KV an d BU16024KV
2). HPD_SINK Pull down resistance.
HPD_SINK have a 5V tolerant structure shown in Figure 9.It needs some drive current to pull down HPD_SINK "H" to "L".
So to pull down HPD_SINK, please use 10kΩ(or under 10kΩ) resistor.
Figure 9 HPD_SINK I/O schematic
3). About don’t use terminal.
3-1. Unused TMDS input channel recommend open.
Vcc
R
INT
A
B
R
INT
TMDS
Receiver
TMDS
Driver
Figure 10 TMDS Input Recommendation
3-2. Unused DDC Buffers of R side recommend to pull up to Vcc.
3-3. Unused DDC Buffers of R side recommend pull up to Vcc.
Vcc
Technical Note
4.7k
RSCL
RSD
T
TSCL
TSD
R
Figure 12 Unused DDC of T side
3-4. Unused HPDn recommend open.
Figure 13 Open unused HPDn
4). About serial connection notice.
When BU160xxKV output connect to other HDMI sw input like following application the specification of Jitter toleranc e is
downed. Especially when system needs 1080p (12bit) data rate and cable or PCB trace lengths bet ween BU160xxKV i nput
and output is small, Deteriorations of Jitter tolerance is outstanding. This problem also depends on receiver IC
characteristic. When system is required 1080p (12bit), Rohm doesn’t recommend serial connect application.
5). AC Coupling notice
BU160xxKV can also communicate using AC coupling capacitor with TMDS line. But even connecting AC coupling
capacitor, AC current may flow if input common mode voltage between two devices is different. For this current, the lower
common mode voltage devices like PCIe or DP may be damaged by AC current.
Technical Note
Figure 15 AC Coupling connection notice
6). TMDS output offset voltage notice.
Offset voltage may appear to TMDS output when there is no signal to TMDS input differential line. OE should set to “H” to
avoid it.
7). Limitation of Master and slave direction as shown Figure 16.
Figure 16 Limitation of Master and slave direction
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
1pin
Reel
Direction of feed
Order quantity needs to be multiple of the minimum quantity.
∗
2010.05 - Rev.E
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