Richtek RT8015AGQW Schematic [ru]

3A, 2MHz, Synchronous Step-Down Converter

RT8015A

General Description

The RT8015A is a high efficiency synchronous, step-down
DC/DC converter. Its input voltage range is from 2.6V to

5.5V and provides a n adjustable regulated output voltage
from 0.8V to 5V while delivering up to 3A of output current.

The internal synchronous low on-resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The switching frequency is
set by an external resistor or can be synchronized to an
external clock. The 100% duty cycle provides low dropout
operation extending battery life in portable systems.
Current mode operation with external compensation
allows the transient response to be opti mized over a wide
range of loads a nd output ca pacitors.

The RT8015A is operated in forced continuous PWM Mode
which minimizes ripple voltage a nd reduces the noise and
RF interference.

The 100% duty cycle in Low Dropout Operation further
maximize battery life.

Features

zz

High Efficiency : Up to 95%

z

zz

zz

z Low R

zz

zz

z Programmable Frequency : 300kHz to 2MHz

zz

zz

z No Schottky Diode Required

zz

zz

z 0.8V Reference Allows for Low Output Voltage

zz

zz

z Forced Continuous Mode Operation

zz

zz

z Low Dropout Operation : 100% Duty Cycle

zz

zz

z RoHS Compliant and 100% Lead (Pb)-Free

zz

Internal Switches : 110m

DS(ON)

ΩΩ

Ω

ΩΩ

Applications

z Portable Instruments
z Battery-Powered Equipment
z Notebook Computers
z Distributed Power Systems
z IP Phones
z Digital Camera s

Pin Configurations

(TOP VIEW)

The RT8015A is availa ble in the W DF N-10L 3x3 pa ckage.

Ordering Information

RT8015A

Package Type
QW : WDFN-10L 3x3

Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)

Note :
Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

SHDN/RT

GND

LX
LX

PGND

1
2
3
4
5

10

COMP

9

FB

8

VDD

7

PVDD

9

11

PVDD

WDFN-10L 3x3

Marking Information

For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.

DS8015A-04 March 2011 www.richtek.com

1

RT8015A

Typical Application Circuit

V

IN

5V

R

OSC

332k

Note : Using all Ceramic Capacitors

Functional Pin Description

1
2

3, 4

5

SHDN/RT
GND

LX

PGND

RT8015A

L1

2µH

COMP

FB

VDD

PVDD

10

9
8

6, 7

C

IN

22µF

R

COMP

30k

22pF

C

COMP

1000pF

240k

R2

C

1

R1
510k

C

OUT

22µFx2

V

OUT

2.5V/3A

P in No. Pin Name Pin F unction

1 SHDN/RT

Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the
switching frequency. Forcing this pin to V

2 GND

Signal Ground. All small-signal components and compensation components should
connect to this ground, which in turn connects to PGND at one point.

3, 4 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor.

5 PGND Power Ground. Connect this pin close to the negative terminal of CIN and C

6, 7 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor.

Signal Input Supply. Decouple this pin to GND with a capacitor. Normally V

8 VDD

9 FB

equal to PVDD.
Feedback Pin. This pin Receives the feedback voltage from a resistive divider
connected across the output.
Error Amplifier Compensation Point. The current comparator threshold increases

10 COMP

with this control voltage. Connect external compensation elements to this pin to
stabilize the control loop.
No Internal Connection. The exposed pad must be soldered to a large PCB and

11 (Exposed Pad) NC

connected to GND for maximum power dissipation.

causes the device to be shut down.

DD

OUT

DD

.

is

DS8015A-04 March 2011www.richtek.com

2

Function Block Diagram

RT8015A

SHDN/RT

COMP

FB

0.8V

POR

VDD

EA

Int-SS

SD

Output
Clamp

0.9V

0.7V

0.4V

OSC

Slope

Com

ISEN

OC

Limit

PVDD

Driver

LX

Control

Logic

NISEN

PGND

NMOS I Limit

REF

OTP

GND

V

Layout Guide

CIN must be placed between VDD
and GND as closer as possible

V

IN

PVDD
PVDD

COMP

R1

C

F

V

OUT

R2

R

COMP

C

COMP

VDD

FB

C

6
7
8
9

10

Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between V

GND

IN

RT8015A

GND

Output capacitor must be
near RT8015A

V

and GND.

OUT

OUT

5

PGND

4

LX

3

LX

2

GND

1

SHDN/RT

C

OUT

LX should be
connected to Inductor
by wide and short
trace, keep sensitive
components away

L1

from this trace

R

OSC

DS8015A-04 March 2011 www.richtek.com

3

RT8015A

Operation

Main Control Loop

The RT8015A is a monolithic, constant-frequency , current
mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-Channel
MOSFET) is turned on at the beginning of each clock
cycle. Current in the inductor increases until the peak
inductor current reach the value defined by the voltage on
the COMP pin. The error a mplifier adjusts the voltage on
the COMP pin by comparing the feedback signal from a
resistor divider on the FB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the COMP voltage until the
average inductor current matches the new load current.
When the top power MOSFET shuts off, the synchronous
power switch (N-MOSFET) turns on until either the bottom
current limit is rea ched or the beginning of the next clock
cycle.

The operating frequency is set by an external resistor
connected between the RT pin a nd ground. The practical
switching frequency can ra nge from 300kHz to 2MHz. In
an over-voltage condition, the top power MOSFET is turned
off and the bottom power MOSFET is switched on until
either the over voltage condition clears or the bottom
MOSFET's current limit is rea ched.

RT8015A is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by a dding a compensating ra mp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. In the RT8015A, however, separated inductor
current signals are used to monitor over current condition.
This keeps the maximum output current relatively constant
regardless of duty cycle.

Short Circuit Protection

When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. A
current runaway detector is used to monitor inductor
current. As current increa sing beyond the control of current
loop, switching cycles will be skipped to prevent current
runaway from occurring.

Dropout Operation

When the input supply voltage decrea ses toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually reaching 100% duty cycle.

The output voltage will then be determined by the input
voltage minus the voltage drop across the internal
P-Channel MOSFET a nd the inductor.

Low Supply Operation

The RT8015A is designed to operate down to an input
supply voltage of 2.6V. One important consideration at
low input supply voltages is that the R
P-Channel a nd N-Cha nnel power switches increase s. The
user should calculate the power dissipation when the

4

DS(ON)

of the

DS8015A-04 March 2011www.richtek.com

RT8015A

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, VDD, PVDD ---------------------------------------------------------------------------- −0.3V to 6V
z LX Pin Switch Voltage--------------------------------------------------------------------------------------------−0.3V to (PVDD + 0.3V)

<200ns ---------------------------------------------------------------------------------------------------------------−5V to 7.5V

z Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V)
z LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A
z Power Dissipation, P

W D FN-10L 3x3 -----------------------------------------------------------------------------------------------------909mW

z Package Thermal Resistance (Note 2)

W DFN-10L 3x3, θJA-----------------------------------------------------------------------------------------------11 0°C/W

z Junction T emperature--------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------260°C
z Storage T emperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
z ESD Susceptibility (Note 3)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode)----------------------------------------------------------------------------------------------200V

Recommended Operating Conditions (Note 4)

z Supply Input V oltage----------------------------------------------------------------------------------------------2.6V to 5.5V
z Junction T emperature Range------------------------------------------------------------------------------------
z Ambient T emperature Range------------------------------------------------------------------------------------

@ TA = 25°C

D

−40°C to 125°C

−40°C to 85°C

Electrical Characteristics

(V

= 3.3V, T

DD

Input Voltage Ra nge VDD 2.6 -- 5.5 V
Feedback Reference Voltage V
Feedback Leakage Current IFB -- 0.1 0.4 μA

DC Bias Cu rre nt

Out put Voltage Line Regul at ion VIN = 2.7V to 5.5V -- 0.04 -- %/V

Out put Voltage Load R egulation

Er ror A mp lifier
Transconductance

Current Sense Transresistance RT -- 0.4 -- Ω
Switching Leakage Current SHDN/RT = VIN = 5. 5V -- -- 1 μA

Switching Fr equenc y

= 25°C, unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Unit

0.784 0.8 0.816 V

REF

Active , VFB = 0.78V, Not Switching -- 460 -- μA
Shutdown -- -- 1 μA

Me as ured in Se rv o Loop,
V

g

-- 800 -- μs

m

R

= 0.2V to 0.7V (Note 5)

COMP

= 332k 0.8 1 1.2 MHz

OSC

−0.2

±0.02 0.2 %

Switching Fr equency 0.3 -- 2 MHz
Sw itch On Resistan ce, High
Sw itch On Resistan ce, Low R

R

ISW = 0.5A -- 110 160 mΩ

PMOS

ISW = 0.5A -- 110 170 mΩ

NMOS

To be continued

DS8015A-04 March 2011 www.richtek.com

5

RT8015A

Parameter Symbol Test Conditions Min Typ Max Unit

Peak Current Limit I
Under Vol tage Lockout

Threshold

3.2 3.8 -- A

LIM

V
V

Ris ing -- 2. 4 -- V

DD

Fa lling -- 2. 3 -- V

DD

Shutdown Threshold -- VIN − 0.7 VIN − 0. 4 V

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization

is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of

JA

JEDEC thermal measurement standard.

and correlation with statistical process controls.

DS8015A-04 March 2011www.richtek.com

6

Typical Operating Characteristics

RT8015A

Efficiency vs . Loa d Current

100

90
80
70
60
50

Eff iciency (%)

40
30
20

0.01 0.1 1 10

VIN = 4.5V

VIN = 5.5V

VIN = 5V

V

Load Current (A)

Frequency vs. Temperature

1.08

1.06

1.04

1.02

Frequency (MHz)

1.00

0.98

VIN = 5V, V

-50 -25 0 25 50 75 100 125

Temperature

= 2.5V, I

OUT

(°C)

OUT

= 2.5V

= 0A

OUT

Output Voltage vs. Load Current

2.492

2.488

2.484

2.480

2.476

2.472

2.468

Output Voltage ( V)

2.464

2.460

2.456

0.00.51.01.52.02.53.0

Load Current (A)

Peak Current Limit vs. Input Voltage

5.0

4.5

4.0

3.5

3.0

Current Limit (A)

2.5

V

2.0

3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

Input Voltage (V)

OUT

VIN = 5V

= 2.5V

Quiescent Current vs. Input Voltage

450
440
430
420
410
400
390
380

Quiescent Current (uA)

370
360

2.5 3 3.5 4 4.5 5 5.5

Input Vol tage (V)

450

440

430

420

410

400

Quiescent Current (uA)

390

380

Quiescent Current vs. Temperature

VIN = 5V

-50-25 0 25 50 75100125

Temperature

(°C)

DS8015A-04 March 2011 www.richtek.com

7

RT8015A

Output Voltage v s . Te m perature

3.34

0.84

V

vs. Input Voltage

REF

3.32

3.30

3.28

3.26

Output V oltage ( V)

3.24

3.22

V

OUT_ac

(100mV/Div)

VIN = 5V

-50 -25 0 25 50 75 100 125

Temperature

(°C)

Load Transient Response

VIN = 5V, V
I

= 0A to 3A

OUT

OUT

= 2.5V

0.83

0.82

(V)

0.81

REF

V

0.80

0.79

0.78

V

LX

(5V/Div)

V

OUT_ac

(10mV/Div)

2.5 3 3.5 4 4.5 5 5.5

Inpu t Volt age (V)

Output Ripple

I

LOAD

(1A/Div)

V

IN

(2V/Div)

V

LX

(2V/Div)

V

OUT

(2V/Div)

I

IN

(1A/Div)

VIN = 5V, V
I

= 0A

OUT

Time (100us/Div)

Start-up with No Load

= 2.5V

OUT

Time (1ms/Div)

I

LX

(2A/Div)

V

IN

(2V/Div)

V

LX

(2V/Div)

V

OUT

(2V/Div)

I

IN

(2A/Div)

Time (400ns/Div)

Start-up with Heavy Load

VIN = 5V, V
I

= 3A

OUT

= 2.5V

OUT

Time (1ms/Div)

VIN = 5V, V
I

= 3A

OUT

OUT

= 2.5V

DS8015A-04 March 2011www.richtek.com

8

Application Information

The basic R T8015A a pplication circuit is shown in T ypical
Application Circuit. External component selection is
determined by the maximum load current a nd begins with
the selection of the inductor value and operating frequency
followed by CIN and C

Output Voltage Programming

The output voltage is set by an external resistive divider
according to the f ollowing equation :

⎛

1VV

⎜

REFOUT

⎝

where V

equals to 0.8V typical.

REF

The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.

Figure 1. Setting the Output Voltage

OUT

R1

+×=

R2

RT8015A

⎞
⎟

⎠

.

GND

FB

V

OUT

R1

R2

RT8015A

Operating Frequency

Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance a nd/or capa cita nce to maintain
low output ripple voltage.

The operating frequency of the RT8015A is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing ca pacitor within the oscillator . The RT resistor value
can be determined by examining the frequency vs. RT
curve. Although frequencies a s high a s 2MHz are possible,
the minimum on-time of the RT8015A imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns. Therefore, the minimum duty cycle is
equal to 100 x 1 10ns x f(Hz).

2.5

RT = 152k for 2MHz

Soft-Start

The RT8015A contains an internal soft-start clamp that
gradually raises the clamp on the COMP pin. The full
current range becomes available on COMP after 1024
switching cycles as shown in Figure 2.

VIN = 5V

= 2.5V

V

OUT

I

= 2A

OUT

V

IN

(2V/Div)

V

OUT

(1V/Div)

I

L

(1A/Div)

Time (400us/Div)

Figure 2. Soft-Start

2

1.5

RT = 330k for 1MHz

1

Frequency ( M H z)

0.5

0

0 200 400 600 800 1000

R

(kٛ)

R

(kΩ)

OSC

OSC

Figure 3

Inductor Selection

For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increa ses with higher VIN and decrea ses
with higher inductance.

V

⎡

I

=Δ

L

⎢

Lf

×

⎣

V

⎡

⎤

1

−

⎢

⎥

⎣

⎦

⎤

OUTOUT

⎥

V

IN

⎦

DS8015A-04 March 2011 www.richtek.com

9

RT8015A

Having a lower ripple current reduces the ESR losses in
the output capa citors and the output voltage ri pple. Highest
efficiency operation is a chieved at low frequency with small
ripple current. This, however , requires a large inductor . A
reasonable starting point for selecting the ripple current
is ΔI = 0.4(I

). The largest ripple current occurs at the

MAX

highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :

⎡

L(MAX)

⎤

V

1

−

⎢

⎥

V

IN(MAX)

⎣

⎦

⎡

V

L

=

OUT

⎢

If

Δ×

⎣

OUT

⎤
⎥

⎦

Inductor Core Selection

Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and theref ore copper losses
will increa se.

CIN and C

Selection

OUT

The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :

V

II

OUT(MAX)RMS

OUT

V

This formula has a maximum at VIN = 2V
I

RMS

= I

/2. This simple worst-case condition is

OUT

IN

V

V

IN

OUT

1

−=

, where

OUT

commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required.

Several cap acitors may also be paralleled to meet size or
height requirements in the design.

The selection of C

is determined by the effective series

OUT

resistance (ESR) that is required to mini mize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient re sponse as described in a later section.
The output ripple, ΔV

, is determined by :

OUT

Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which mean s that
inductance collapses abruptly when the peak design
current is exceeded.

This result in an abrupt increa se in inductor ri pple current
and consequent output voltage ri pple.

Do not allow the core to saturate!
Different core materials a nd sha pes will change the size/

current and price/current relationship of a n inductor. T oroid
or shielded pot cores in ferrite or permalloy materials are
small and don't radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs. size requirements and
any radi ated field/EMI requirements.

⎡

ESRIV

LOUT

+Δ≤Δ

⎢

⎣

8fC

1

OUT

⎤
⎥

⎦

The output ripple is highest at maximum input voltage
since ΔIL increa ses with input voltage. Multiple ca pacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic a nd cera mic capa citors are
all available in surface mount pa ckages. Speci al polymer
ca pacitors offer very low ESR but have lower ca pa citance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but ca n be used in cost-sensitive
application s provided that consideration is given to ripple
current ratings and long term relia bility. Cera mic ca pacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric ef fects.
The high Q of ceramic capacitors with trace inductance
can also lead to signif ica nt ringing.

10

DS8015A-04 March 2011www.richtek.com

RT8015A

Using Ceramic In put and Output Capacitors

Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR ma ke them ideal
for switching regulator a pplications. However , care must
be taken when these ca pacitors are used at the in put and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall ad a pter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.

Checking Tra n sient Re spon se

The regulator loop response can be checked by looking
at the load transient respon se. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ΔI
resistance of C
discharge C

LOAD(ESR)

OUT

generating a feedback error signal used

OUT

by the regulator to return V
During this recovery time, V

immediately shifts by a n amount

OUT

, where ESR is the effective series

. ΔI

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability problem.
The COMP pin external components and output ca pa citor
shown in T ypical Application Circuit will provide adequate
compensation for most a pplication s.

Efficiency Considerations

The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency ca n be expressed as :

Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc.
are the individual losses as a percentage of in put power .
Although all dissipative elements in the circuit produce
losses, two main sources usually account f or most of the
losses: VDD quiescent current and I2R losses.

The VDD quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
actual power lost is of no consequence.

1. The VDD quiescent current is due to two components :
the DC bi as current a s given in the electrical characteristics
and the internal main switch a nd synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each ti me the gate is switched from
high to low to high again, a packet of charge ΔQ moves
from VDD to ground. The resulting ΔQ/Δt is the current out
of VDD that is typically larger than the DC bi as current. In
continuous mode, I

GATECHG

= f(QT+QB) where QT and QB
are the gate charges of the internal top and bottom
switches.

Both the DC bi as a nd gate charge losses are proportional
to VDD and thus their effects will be more pronounced at
higher supply voltages.

2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series re sistance
looking into the LX pin is a function of both top and bottom
MOSFET R

RSW = R

DS(ON)

and the duty cycle (D) as follows :

DS(ON)

TOP x D + R

BOT x (1"D) The R

DS(ON)

DS(ON)

for both the top and bottom MOSFETs can be obtained
from the Typical Perf ormance Characteristics curves. Thus,
to obtain I2R losses, simply add RSW to RL a nd multi ply
the result by the square of the average output current.
Other losses including CIN and C

ESR dissipative

OUT

losses and inductor core losses generally a ccount for less
than 2% of the total loss.

Thermal Considerations

In most applications, the RT8015A does not dissipate
much heat due to its high efficiency. But, in applications
where the RT8015A is running at high a mbient temperature
with low supply voltage and high duty cycles, such as in
dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction temperature
reaches approximately 150°C, both power switches will
be turned off and the SW node will become high

DS8015A-04 March 2011 www.richtek.com

11

RT8015A

impedance. To avoid the RT8015A from exceeding the
maximum junction temperature, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds
the maximum junction temperature of the part. The
temperature rise is given by : TR = PD x θJA Where PD is
the power dissipated by the regulator and θJA is the thermal
resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by :
TJ = TA + TR Where TA is the ambient temperature.

As an example, consider the RT8015A in dropout at an
input voltage of 3.3V , a load current of 2A a nd an a mbient
temperature of 70°C. From the typical performance gra ph
of switch resistance, the R

of the P-Channel switch

DS(ON)

at 70°C is approximately 121mΩ. Therefore, power
dissipated by the part is :

PD = (I

LOAD

)2 (R

) = (2A)2 (121mΩ) = 0.484W

DS(ON)

For the DFN3x3 package, the θJA is 110°C/W. Thus the
junction temperature of the regulator is : TJ = 70°C +
(0.484W) (110°C/W) = 123.24°C Which is below the
maximum junction temperature of 125°C. Note that at
higher supply voltages, the junction temperature is lower
due to reduced switch resistance (R

DS(ON)

).

` Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise
of powercomponents.

Y ou can connect the copper area s to a ny DC net (PV DD,
V DD, VOUT, PGND, GND, or any other DC rail in your
system).

` Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between V

OUT

and GND.

Figure 4

Layout Considerations

Follow the PCB layout guidelines for optimal performa nce
of RT8015A.

` A ground pla ne is recommended. If a ground plane layer

is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.

` Connect the terminal of the input capacitor(s), C

IN

, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.

` LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray cap acitive
noise pick-up.

Figure 5

12

DS8015A-04 March 2011www.richtek.com

RT8015A

Recommended component selection for T ypical Application

Table 1. Inductors

Com ponent Suppl ie r Ser ie s Induct ance (μH) DCR (mΩ) Cur re n t Ra ting ( mA) Dimensio ns (mm)

TAIY O YUDE N NR 8040 2 9 7800 8x 8x4

Table 2. Capacitors for CIN and C

Compon ent Sup pl ie r Par t No. Capacit ance (μF) Case Size

TDK C3225X5R0J226M 22 1210

TDK C2012X5R0J106M 10 0805
Panasonic ECJ4YB0J226M 22 1210
Panasonic ECJ4YB1A106M 10 1210

TA IYO YUDEN LMK325BJ226ML 22 1210
TA IYO YUDEN JMK316BJ226ML 22 1206
TA IYO YUDEN JMK212BJ106ML 10 0805

OUT

DS8015A-04 March 2011 www.richtek.com

13

RT8015A

Outline Dimension

D

E

A

A3

A1

D2

L

E2

SEE DETAIL A

1

e

b

2

1

1

2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 2.300 2.650 0.091 0.104

E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069

e 0.500 0.020

L 0.350 0.450

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

0.014 0.018

W-Type 10L DFN 3x3 Package

Richtek Technology Corporation

Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8015A-04 March 2011www.richtek.com

14