Richtek RT8010-10GQW, RT8010-10PQV, RT8010-10PQW, RT8010-12GQW, RT8010-12PQV Schematic [ru]

...

RT8010/A

1.5MHz, 1A, High Efficiency PWM Step-Down DC/DC Converter

General Description

The RT8010/A is a high efficiency Pulse-Width-Modulated (PWM) step-down DC/DC converter . Ca pable of delivering 1A output current over a wide input voltage range from

2.5V to 5.5V, the RT8010/A is ideally suited for portable electronic devices that are powered from 1-cell Li-ion battery or from other power sources such as cellular phones, PDAs and hand-held devices.

Two operating modes are availa ble including : PWM/LowDropout autoswitch and shutdown modes. The Internal synchronous rectifier with low R conduction loss at PWM mode. No external Schottky diode is required in practical a pplication.

The RT8010/A enters Low Dropout mode when normal PWM cannot provide regulated output voltage by continuously turning on the upper P-MOSFET . RT8010/A enter shut-down mode and consumes less than 0.1 μA when EN pin is pulled low.

dramatically reduces

DS(ON)

Features



2.5V to 5.5V Input Range





 Output V oltage (Adjustable Output From 0.6V to V



` RT8010 : 1V, 1.2V, 1.5V, 1.6V, 1.8V, 2.5V and 3.3V

Fixed/Adjustable Output Voltage

` RT8010A Adjustable Output Voltage Only



 1A Output Current



 95% Efficiency



 No Schottky Diode Required



 1.5MHz Fixed-Frequency PWM Operation



 Small 6-Lead WDFN and 16-Lead WQFN Package



 RoHS Compliant and 100% Lead (Pb)-Free



Applications

 Mobile Phones  Personal Information Appliances  Wireless and DSL Modems  MP3 Players  Portable Instruments

The switching ripple is easily smoothed-out by small package filtering elements due to a fixed operating frequency of 1.5MHz. This along with small W DF N-6L 2x2 and WQFN-16L 3x3 package provides small PCB area a pplication. Other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection.

Ordering Information

RT8010/A(- )

Package Type QW : WDFN/WQFN (W-Type)

Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free)

Output Voltage

Pin Configurations

(TOP VIEW)

GND

VIN

1 2 3

FB/VOUT

GND

WDFN-6L 2x2 (RT8010)

GND GND

FB/VOUT

WQFN-16L 3x3 (RT8010A)

Marking Information

For marking information, contact our sales re presentative directly or through a Richtek distributor located in your area.

DS8010/A-09 September 2012 www.richtek.com

LXLXLX

13141516

VIN

12 11

VIN

VIN VIN

8765

1 2 3 4

GND

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Default : Adjustable (RT8010/A) Fixed (RT8010) 10 : 1.0V 12 : 1.2V 15 : 1.5V 16 : 1.6V 18 : 1.8V 25 : 2.5V 33 : 3.3V

WQFN-16L 3x3 WDFN-6L 2x2

)

RT8010/A

Typical Application Circuit

2.5V to 5.5V

⎛

⎜

REFOUT

⎝

⎞

1 x VV

⎟

⎠

4.7µF

VIN

RT8010/A

EN VOUT

GND

2.2µH

Figure 1. Fixed V oltage Regulator

4.7µF

VIN

RT8010/A

EN FB

GND

2.2µH

OUT

10µF

OUT

10µF

OUT

with R2 = 300kΩ to 60kΩ so the IR2 = 2μA to 10μA, and (R1 x C1) should be in the range between 3x10

Figure 2. Adjustable V oltage Regulator

Layout Guide

RT8010/A_FIX

VIN

CIN must be placed to the VIN as close as possible.

Layout note :

1. The distance that C

2. C

should be placed near RT8010/A.

OUT

VOUT

GND

LX should be connected to Inductor by wide and short trace, keep sensitive components away from this trace.

connects to VIN is as close as possible (Under 2mm).

Output capacitor must be near RT8010

OUT

-6

and 6x10

Figure 3

-6

for component selection.

RT8010/A_ADJ

VIN

CIN must be placed to the VIN as close as possible.

GND

LX should be connected to Inductor by wide and short trace, keep sensitive components away from this trace.

Output capacitor must be near RT8010/A

OUT

DS8010/A-09 September 2012www.richtek.com

Functional Pin Description

Pin No.

RT8010 RT8010A

1 6, 8, 16 IC 2 7 EN

3 9, 10, 11, 12 VIN Power Input. (Pin 9 and Pin 10 must be c onnected with Pin 11). 4 13, 14, 15 LX Pin for Switching. (Pin 13 m ust be c onnected with Pin 14). 5 1, 2, 3, 5 GND Ground. 6 4 FB/VOUT Feedback/Output Voltage.

Pin Name Pin Function

RT8010/A

Internal Connection. Leave floating and do not make connection to this pin. Chip Enable ( Active High).

7 (Expo sed Pad) 17 (Exposed Pad) GND

Function Block Diagram

Slope

Compensation

FB/VOUT

Error

Amplifier

COMP

Ground. The exposed pad must be soldered to a large PCB and connec ted to GND for maximum thermal dissipation.

EN VIN

OSC &

Shutdown

Control

Current

Sense

PWM

Comparator

UVLO &

Power Good

Detector

REF

Current

Limit

Detector

Control

Logic

Driver

RS1

RS2

GND

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

Absolute Maximum Ratings (Note 1)

 Supply Input V oltage------------------------------------------------------------------------------------------------- 6.5V  EN, FB Pin Voltage -------------------------------------------------------------------------------------------------- −0.3V to V  LX Pin Switch Voltage ----------------------------------------------------------------------------------------------- −0.3V to (V

<20ns ------------------------------------------------------------------------------------------------------------------- −4.5V to 7.5V

 LX Pin Switch Current ----------------------------------------------------------------------------------------------- 2A  Power Dissipation, P

@ TA = 25°C

WDFN-6L 2x2 --------------------------------------------------------------------------------------------------------- 0.833W WQFN-16L 3x3 ------------------------------------------------------------------------------------------------------- 1.47W

 Package Thermal Re sistance (Note 2)

W DFN-6L 2x2, θJA---------------------------------------------------------------------------------------------------- 120°C/W WDFN-6L 2x2, θJC--------------------------------------------------------------------------------------------------- 20°C/W WQF N-16L 3x3, θJA-------------------------------------------------------------------------------------------------- 68°C/W WQFN-16L 3x3, θJC------------------------------------------------------------------------------------------------- 7.5°C/W

 Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------- 260°C  Storage T emperature Range --------------------------------------------------------------------------------------- −65°C to 150°C  Junction T emperature------------------------------------------------------------------------------------------------ 150°C  ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------- 2kV

+ 0.3V)

Recommended Operating Conditions (Note 4)

 Supply Input V oltage------------------------------------------------------------------------------------------------- 2.5V to 5.5V  Junction T emperature Range---------------------------------------------------------------------------------------  Ambient T emperature Range---------------------------------------------------------------------------------------

−40°C to 125°C

−40°C to 85°C

Electrical Characteristics

= 3.6V, V

Input Volt age Ra nge VIN 2.5 -- 5.5 V Qui escent Cu rrent IQ I Shutdown Current I Re f erenc e Volt a ge V Adjustable Output Range V

Output Voltage

Accuracy

= 2.5V, L = 2.2μH, C

OUT

= 4.7μF, C

OUT

= 10μF, T

= 25°C, I

= 1A unless otherwise specified)

MAX

Parameter Symbol Test Conditions Min Typ Max Unit

Fix

= 0mA, VFB = V

OUT

EN = G ND -- 0.1 1 μA

SHDN

For Adjustable Output Voltage 0.588 0.6 0.612 V

REF

(Note 5) V

OUT

= 2.5V to 5.5V, V

0A < I V

0A < I

< 1A

OUT

= 2.5V to 5.5V, V

< 1A

OUT

= 2.5V to 5.5V, V

< 1A

OUT

= 2.5V to 5.5V, V

< 1A

OUT

= 2.5V to 5.5V, V

< 1A

OUT

ΔV

ΔV ΔV

OUT

+ 5% -- 50 70 μA

REF

OUT

= 1V

= 1.2V

= 1.5V = 1.6V

= 1.8V

-- V

REF

−3 -- 3

− 0.2V V

DS8010/A-09 September 2012www.richtek.com

RT8010/A

Parameter Symbol Test Conditions Min Typ Max Unit

= V

ΔV

OUT

Fix

Outpu t Volt age

ΔV

Accuracy

Adjustable

FB I nput Curre nt

P-MOSF ET RON R

N-MOSFET RON R

P-Channel Current Limit EN High-Level Input Voltage EN Low-Level Input Voltage

OUT

ΔV

OUT

DS(ON)_P

DS(ON)_N

LIM_P

VIN = 2.5V to 5.5V

EN_H

VIN = 2.5V to 5.5V

EN_L

OUT

= V

OUT

= V

0A < I

= VIN

OUT

= 2.5V to 5.5 V

+ ΔV to 5.5V (Note 6)

OUT

= 2.5V, 0A < I

+ ΔV to 5.5V (Note 6)

OUT

= 3.3V, 0A < I

+ ΔV to 5.5V (Note 6)

OUT

< 1A

OUT

= 200 mA

OUT

V V V V

IN IN IN IN

< 1A

= 3.6V = 2.5V = 3.6V = 2.5V

−3

-- 3 %

−3

-- 3

-- 3 %

−50 -- 50 nA

-- 0.28 -Ω

-- 0.38 --

-- 0.25 -Ω

-- 0.35 --

1.4 1.5 -- A

1.5 -- -V

-- -- 0.4 Under Voltage Loc k Ou t thr es hold UVLO -- 1.8 -- V Hysteresis -- 0.1 -- V

Oscillator Frequency

Ther m al S hutd own Temper atu re

OSC

= 3.6V, I

OUT

= 100mA

-- 160 --

1.2 1.5 1.8 MHz °C

Ma x . Duty Cy cle 100 -- -- % LX Leakage Curr ent

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. Note 6. ΔV = I

is measured at T

measured at the exposed pad of the package.

x P

OUT

RDS(ON)

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

= 3.6V, V

= 0V or V

= 3.6V −1

-- 1

μA

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

)

Typical Operating Characteristics

Efficiency vs. Output Current

100

VIN = 3.6V

= 4.2V

80 70 60 50 40

Efficiency (%)

30 20 10

VIN = 5V

= 3.3V, C

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

OUT

= 4.7μF, L = 4.7μH

OUT

Output Current (A)

Efficiency vs. Output Current

100

90 80 70 60 50 40

Efficiency (%)

30 20 10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

= 1.2V, C

OUT

Output Current (A)

= 10μF, L = 2.2μH

VIN = 5V

= 3.3V

VIN = 2.5V

100

90 80 70 60 50 40

Eff iciency (%)

30 20 10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

OUT

= 1.2V, C

= 4.7μF, L = 4.7μH

OUT

Output Current (A)

UVLO Voltage vs. Temperature

2.0

Efficiency vs. Output Current

1.9

1.8

1.7

1.6

1.5

Input Voltage (V)

1.4

1.3

1.2

-40 -25 -10 5 20 35 50 65 80 95 110 125

Rising

Falling

= 1.2V, I

OUT

Temperature (°C)

VIN = 5V

= 3.3V

VIN = 2.5V

= 0A

OUT

EN Pin Threshold vs. Input Voltage

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

EN Pin Threshol d (V)

0.70

0.65

0.60

2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

Rising

Falling

OUT

= 1.2V, I

OUT

= 0A

Inpu t Voltage (V)

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

EN Pin Threshold (V

0.6

0.5

0.4

EN Pin Threshold vs. Temperature

Rising

Falling

VIN = 3.6V, V

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperatur e (°C)

= 1.2V, I

OUT

= 0A

DS8010/A-09 September 2012www.richtek.com

RT8010/A

)

Output Voltage (V)

Output Voltage vs. Load Current

1.230

1.225

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

VIN = 5V

VIN = 3.6V

Load Current (A)

Frequency vs. Input Voltage

1.60

1.55

1.50

1.45

Output Voltage vs. Temperature

1.25

1.24

1.23

1.22

1.21

1.20

1.19

1.18

Output Voltage (V)

1.17

1.16

1.15

-40 -25 -10 5 20 35 50 65 80 95 110 125

VIN = 3.6V, I

Temperature (°C)

Frequency vs. Temperature

1.60

1.55

1.50

1.45

OUT

= 0A

1.40

1.35

Frequency ( kH z)

1.30

1.25

1.20

VIN = 3.6V, V

2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

= 1.2V, I

OUT

Input Voltage (V)

Output Current Limit vs. Input Voltage

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

Output Current Limit (A)

1.6

1.5

2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

Inpu t Voltage (V)

= 1.2V @ T

OUT

= 300mA

OUT

= 20°C

1.40

1.35

Frequency ( kH z) 1

1.30

1.25

1.20

-40 -25 -10 5 20 35 50 65 80 95 110 125

VIN = 3.6V, V

= 1.2V, I

OUT

Temperatur e (°C)

Output Curre nt Limit vs. Temperature

2.6

2.5

2.4

VIN = 3.6V

VIN = 3.3V

-40 -25 -10 5 20 35 50 65 80 95 110 125

Output Current Limit (A

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

VIN = 5V

Temperatur e (°C)

= 300mA

= 1.2V

OUT

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

(2V/Div)

OUT

(1V/Div)

(500mA/Div)

(2V/Div)

VIN = 3.6V, V

VEN = 3V, V

Power On from EN

= 1.2V, I

OUT

Time (100μs/Div)

OUT

= 10mA

Power On from VIN

= 1.2V, ILX = 1A

OUT

(2V/Div)

OUT

(1V/Div)

(500mA/Div)

(2V/Div)

VIN = 3.6V, V

Power On from EN

= 1.2V, I

OUT

Time (100μs/Div)

OUT

= 1A

Power Off from EN

= 1.2V, ILX = 1A

OUT

(1V/Div)

(1A/Div)

OUT

(50mV/Div)

OUT

(500mA/Div)

Time (250μs/Div)

Load Transient Response

VIN = 3.6V, V I

= 50mA to 1A

OUT

= 1.2V

OUT

Time (50μs/Div)

OUT

(1V/Div)

(1A/Div)

OUT

(50mV/Div)

OUT

(500mA/Div)

Time (100μs/Div)

Load Transient Response

VIN = 3.6V, V I

= 50mA to 0.5A

OUT

= 1.2V

OUT

Time (50μs/Div)

DS8010/A-09 September 2012www.richtek.com

RT8010/A

OUT

(50mV/Div)

OUT

(500mA/Div)

OUT

(10mV/Div)

Load Transient Response

VIN = 5V, V I

= 50mA to 1A

OUT

= 1.2V

OUT

Time (50μs/Div)

Output Ripple Voltage

VIN = 3.6V, V I

= 1A

OUT

= 1.2V

OUT

(50mV/Div)

OUT

(500mA/Div)

OUT

(10mV/Div)

Load Transient Response

VIN = 5V, V I

= 50mA to 0.5A

OUT

= 1.2V

OUT

Time (50μs/Div)

Output Ripple Voltage

VIN = 5V, V

= 1A

OUT

= 1.2V

(2V/Div)

Time (500ns/Div)

(2V/Div)

Time (500ns/Div)

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

Applications Information

The basic R T8010/A a pplication circuit is shown in T ypical Application Circuit. External component selection is determined by the maximum load current and begin s with the selection of the inductor value and operating frequency followed by CIN and C

OUT

Inductor Selection

For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increas es with higher VIN and decrea ses with higher inductance.

⎡⎤⎡ ⎤

Δ×−

I = 1

OUT OUT

⎢⎥⎢ ⎥

fL V

⎣⎦⎣ ⎦

Having a lower ripple current reduces the ESR losses in the output capa citors and the output voltage ri pple. Highest efficiency operation is a chieved at low frequency with small ripple current. This, however , requires a large inductor.

A rea son able starting point for selecting the ri pple current is ΔIL = 0.4(I

). The largest ripple current occurs at the

MAX

highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation :

⎡⎤⎡ ⎤

L = 1

OUT OUT

⎢⎥⎢ ⎥

fI V

×Δ

L(MAX) IN(MAX)

⎣⎦⎣ ⎦

×−

Inductor Core Selection

Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and theref ore copper losses will increa se.

Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design

current is exceeded. This results in an a brupt increa se in inductor ripple current and con sequent output voltage ripple. Do not allow the core to saturate!

Different core materials a nd sha pes will cha nge the size/ current and price/current relationship of a n inductor .

T oroid or shielded pot cores in ferrite or permalloy materials are small and don't radi ate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radi ated field/EMI requirements.

CIN and C

Selection

OUT

The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by :

I = I 1

RMS OUT(MAX)

OUT

This formula has a maximum at VIN = 2V I

RMS

= I

/2. This simple worst-case condition is

OUT

IN OUT

−

, where

OUT

commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capa citor ma nufa cturers are often based on only 2000 hours of life which makes it advisa ble to further derate the capa citor , or choose a capa citor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.

The selection of C

is determined by the Effective Series

OUT

Resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load tran sient response as described in a later section. The output ripple, ΔV

8fC

OUT

Δ≤Δ

V I ESR+

OUT L

⎡⎤ ⎢⎥

⎣⎦

, is determined by :

OUT

DS8010/A-09 September 2012www.richtek.com

RT8010/A

The output ripple is highest at maximum input voltage since ΔIL increa ses with input voltage. Multiple ca pacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic a nd cera mic capa citors are all available in surface mount pa ckages. Speci al polymer ca pacitors offer very low ESR but have lower ca pa citance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but ca n be used in cost-sensitive application s provided that consideration is given to ripple current ratings and long term relia bility. Cera mic ca pacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric ef fects. The high Q of ceramic capacitors with trace inductance can also lead to signif ica nt ringing.

Using Ceramic In put and Output Capacitors

Higher values, lower cost ceramic capacitors are now becoming available in smaller ca se sizes. Their high ripple current, high voltage rating and low ESR ma ke them ideal for switching regulator a pplications. However , care must be taken when these ca pacitors are used at the in put and output. When a ceramic capacitor is used at the input and the power is supplied by a wall ad a pter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part.

For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation :

VV1+

OUT REF

where V

⎛⎞ ⎜⎟

⎝⎠

is the internal reference voltage (0.6V typ.)

REF

Efficiency Considerations

The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency ca n be expressed as :

Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses a s a percentage

of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : VIN quiescent current and I2R losses.

The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence.

1. The VIN quiescent current appears due to two factors including : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate cap acita nce of the internal power MOSFET switches. Each ti me the gate is switched from high to low to high again, a packet of charge ΔQ moves from VIN to ground.

Output Voltage Programming

The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 4.

OUT

The resulting ΔQ/Δt is the current out of VIN that is typically larger than the DC bias current. In continuous mode,

GATECHG

= f (QT + QB)

where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias a nd gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages.

RT8010/A

GND

Figure 4. Setting the Output Voltage

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resista nce looking into the LX pin is a function of both top and bottom MOSFET R

RSW = R The R

DS(ON)TOP

DS(ON)

and the Duty Cycle (DC) as follows :

DS(ON)

x DC + R

DS(ON)BOT

x (1 − DC)

for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to R and multiply the result by the s quare of the average output current.

Other losses including CIN and C

ESR dissipative

OUT

losses and inductor core losses generally a ccount for less than 2% of the total loss.

Thermal Considerations

The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation ca n be calculated by following formula :

P Where T

temperature, T

D(MAX)

= (T

− TA) / θ

J(MAX)

is the maximum operation junction

J(MAX)

is the ambient temperature a nd the θ

the junction to ambient thermal resistance. For recommended operating conditions specification,

where T

is the maximum junction temperature of the

J(MAX)

die and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-6L 2x2 packages, the thermal resistance θJA is 120°C/W on the standard JEDEC 51-7 four layers thermal test board.

The Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.

1.6

1.4

1.2

1.0

0.8

WDFN-6L 2x2

0.6

0.4

0.2

Maximum Power Dissipation (W) 1

0.0 0 25 50 75 100 125

WQFN-16L 3x3

Four Layers PCB

Ambient Temperature (°C )

Figure 5. Derating Curve of Maxi mum Power Dissi pation

Checking Tra n sient Re spon se

The regulator loop response can be checked by looking at the load transient respon se. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V equal to ΔI resistance of C discharge C

(ESR), where ESR is the effective series

LOAD

OUT

generating a feedback error signal used

OUT

by the regulator to return V During this recovery time, V

immediately shifts by a n amount

OUT

. ΔI

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability problem.

Layout Considerations

Follow the PCB layout guidelines for optimal performa nce of RT8010/A.

` For the main current paths as indicated in bold lines in

Figure 6, keep their traces short a nd wide.

The maximum power dissipation at TA = 25°C can be calculated by following formula :

= (125°C − 25°C) / 120°C/W = 0.833W for

D(MAX)

W DF N-6L 2x2 pa ckages The maximum power dissipation depends on operating

ambient temperature for fixed T

and thermal

J(MAX)

` Put the input ca pa citor as close a s possible to the device

pins (VIN a nd GND).

` LX node is with high frequency voltage swing a nd should

be kept small area. Keep analog components away from LX node to prevent stray cap acitive noise pick-up.

resistance θJA.

DS8010/A-09 September 2012www.richtek.com

` Connect feedba ck network behind the output capa citors.

Keep the loop area small. Place the feedback components near the RT8010/A.

` An exa mple of 2-layer PCB layout is shown in Figure 7

to Figure 8 for reference.

RT8010/A

VIN

FB/VOUT

GND

6 5

OUT

Figure 7. T op Layer

Figure 8. Bottom Layer

Figure 6. EVB Schematic

Table 1. Recommended Inductors

Supplier

Inductance

(μH)

Current Rating (mA)

DCR (mΩ)

Dimensions

(mm)

Series

TAIYO YUDEN 2.2 1480 60 3.00 x 3.00 x 1.50 NR 3015

GOTREND 2.2 1500 58 3.85 x 3.85 x 1.80 G TSD32

Sumida 2.2 1500 75 4.50 x 3.20 x 1.55 CDRH2D14 Sumida 4.7 1000 135 4.50 x 3.20 x 1.55 CDRH2D14

TAIYO YUDEN 4.7 1020 120 3.00 x 3.00 x 1.50 NR 3015

GOTREND 4.7 1100 146 3.85 x 3.85 x 1.80 GTSD32

Table 2. Recommended Capacitors for CIN and C

Supplier

Capacitance

(μF)

OUT

Package Part Number

TDK 4.7 0603 C1608JB0J475M

MURATA 4.7 0603 GRM188R60J475KE19 TAIYO YUDEN 4.7 0603 JMK107BJ475RA TAIYO YUDEN 10 0603 JMK107BJ106MA

TDK 10 0805 C2012JB0J106M MURATA 10 0805 GRM219R60J106ME19 MURATA 10 0805 GRM219R60J106KE19

TAIYO YUDEN 10 0805 JMK212BJ106RD

DS8010/A-09 September 2012 www.richtek.com

RT8010/A

Outline Dimension

SEE DETAIL A

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inch es

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250

0.007 0.010

b 0.200 0.350 0.008 0.014

D 1.950 2.050 0.077 0.081

D2 1.000 1.450 0.039 0.057

E 1.950 2.050 0.077 0.081 E2 0.500 0.850 0.020 0.033

e 0.650 0.026

L 0.300 0.400

W-Type 6L DFN 2x2 Package

0.012 0.016

DS8010/A-09 September 2012www.richtek.com

RT8010/A

SEE DETAIL A

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inch es

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 1.300 1.750 0.051 0.069

E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 16L QFN 3x3 Package

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8010/A-09 September 2012 www.richtek.com

Richtek RT8010-10GQW, RT8010-10PQV, RT8010-10PQW, RT8010-12GQW, RT8010-12PQV Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual