R-IN32M4-CL2
Board design editio n
Userʼs Manual
Renesas Electronics
User’s Manual:
All information contained in these materials, including pr oduct s and product specifications,
represents informat ion o n t he pr oduct at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronic s Corp.
website (http://www.renesas. com).
Document number: R18UZ0046EJ0200
Issue date: Dec. 28, 2018
www.renesas.com
Notice
1. Descriptions of circuits, softw are and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation of these
circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for
any losses incurred by you or third parties arising from the use of these circuits, software, or information.
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Electronics does not warrant that such information is error free. Renesas Electronics assumes no liabili ty w hatsoever
for any damages incurred by you resulting from errors in or omissions from the information included herein.
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ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a
- Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.
Instructions for the use of product
In this section, the precautions are described for over whole of CMOS device.
Please refer to this manual about individual precaution.
When there i s a mention unlike the text of this manual, a mention of the text takes first priority.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
- The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in
the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through
current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
- The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are
undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are not
guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not
guaranteed from the moment when power is supplied until the power reaches the level at which resetting has
been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
- The reserved addresses are provided for the possible future expansion of functions. Do not access these
addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable. When
switching the clock signal during program execution, wait until the target clock signal has stabilized.
- When the clock signal is generated with an external resonator (or from an external oscillator) during a reset,
clock signal produced with an external resonator (or by an external oscillator) while program execution is in
progress, wait until the target clock signal is stable.
All rights reserved.
- Ethernet is a registered trademark of Fuji Xerox Co., Ltd.
- IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc.
- CC-Link and CC-Link IE Field are registered trademarks of CC-Link Partner Association (CLPA).
- TRON is an acronym for "The Real-time Operation system N ucle us".
- ITRON is an acronym for "Industrial TRON".
- μITRON is an acronym for "Micro Industrial TRON".
- TRON, ITRON, and μITRON do not refer to any specific product or products.
- Additionally all product names and service names in this document are a trademark or a registered trademark which
belongs to the respective owners.
within the body of the text, at the end of each section, and in the Usage Notes section.
point in this document.
refer to it.
Document Name
Document Number
R-IN32M4-CL2 User’s Manual
R18UZ0032EJ****
R-IN32M4-CL2 User’s Manual: Peripheral Modules
R18UZ0034EJ****
R-IN32M4-CL2 User’s Manual: Gigabit Ethernet PHY
R18UZ0044EJ****
R-IN32M4-CL2 Programming Manual: Driver
R18UZ0036EJ****
R-IN32M4-CL2 Programming Manual: OS
R18UZ0040EJ****
R-IN32M4-CL2 User’s Manual: Board des ign edi tion
This manual
How to Use This Manual
1. Purpose and Target Readers
This manual is intended for users who wish to understand the functions of an Ethernet communication LSI "R-IN32M4CL2" for designing app lic a tion of it. It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to
the text of the manual for details.
The mark "<R>" means the updated point in this revision. The mark "<R>" let users search for the updated
Related
Documents
The related documents indicated in this publication may include preliminary versions. However,
preliminary versions a re not marked as such. Please be understand ing of this beforehand. In addition,
because we make document at development, planning of each core, the related document may be the
document for individual customers. Last four digits of document number (described as ****) indicate
version information of each document. Please download the latest document from our web site and
The document related to R-IN32M4-CL2
2. Notation of Numbers and Symbols
Weight in data notation: Left is high-order column, right is low-order column
Active low notation:
xxxZ (capital letter Z after pin name or signal name)
or xxx_N (capital letter _N after pin name or signal name)
or xxnx (pin name or signal name contains small l etter n)
Note:
Explanatio n of (Note) i n the text
Caution:
Item deserving extra attention
Remark:
Supplementary explanation to the text
Numeric notation:
Binary … xxxx , xxxxB or n’bxxxx (n bits)
Decimal … xxxx
Hexadecimal … xxxxH or n’hxxxx (n bits)
Prefixes representing powers of 2 (address space, memory capacity):
K (kilo)… 2
M (mega)… 2
G (giga)… 2
Data Type:
Word … 32 bits
Halfword … 16 bits
Byte … 8 bits
10
= 1024
20
= 10242
30
= 10243
Contents
1.
Overview ........................................................................................................................................................ 1
1.1 Definitio n of Pin Hand ling and Symbols in This Manual ................................................................................... 1
2. Power/Reset Pins .......................................................................................................................................... 2
2.1 Power-O n/O ff Se q ue nc e ..................................................................................................................................... 2
2.2 Power Supply Pins .............................................................................................................................................. 4
2.3 Reset Pins ........................................................................................................................................................... 5
3. Clock Input Pins ............................................................................................................................................. 6
3.1 Pin Functions ...................................................................................................................................................... 6
3.2 Notes on Configuring the Oscillation Circuit ..................................................................................................... 7
3.3 Configuration Example of Oscillation Circuits................................................................................................... 9
4. PLL Power Supply Pins ............................................................................................................................... 10
4.1 Recommended Configuration of Filter ............................................................................................................. 10
4.2 Notes on Placement of Peripheral Components ................................................................................................ 11
5. GPIO Port Pins ............................................................................................................................................ 12
6. Gigabit Ethernet PHY Pins .......................................................................................................................... 13
6.1 Power Supply Peripheral Circ uit ...................................................................................................................... 13
6.1.1 Circuit Configuration ............................................................................................................................... 13
6.1.2 Recommended Components .................................................................................................................... 14
6.2 Peripheral Circuit of Pulse Transformer ........................................................................................................... 15
6.2.1 Example of Circuit Configurat ion ........................................................................................................... 15
6.2.2 Recommended Components .................................................................................................................... 16
6.3 REF_REXT and REF_FILT Pins ..................................................................................................................... 17
6.3.1 Example of Circuit Configurat ion ........................................................................................................... 17
6.3.2 Recommended Resistors .......................................................................................................................... 17
6.3.3 Recommended Ceramic Capacitors ......................................................................................................... 17
6.4 PHYADD Pin Handling .................................................................................................................................... 18
6.4.1 Example of P in Handling ......................................................................................................................... 18
6.4.2 Handling of Pins ...................................................................................................................................... 18
6.5 Notes on Board Wiring ..................................................................................................................................... 19
Contents-1
7. Thermal Design <R> ................................................................................................................................... 22
7.1 Deciding on whether Particular Measures for Heat Dissipation are Required .................................................. 22
7.1.1 Estimating Tj ........................................................................................................................................... 22
7.1.2 Estimating Power Consumption .............................................................................................................. 22
7.1.3 Thermal Resistances under the JEDEC Conditions (for θja and Ψjt) ...................................................... 23
7.1.4 Results of Estimating Po wer Consu mption of the 1-V Sub-Systems at Tj .............................................. 24
7.1.5 Relation between Temperature Increases (∆t) and Thermal Resistance (θja) at a Given Ambient
Temperature ............................................................................................................................................. 25
7.2 Examples of Measures for Heat Dissipation ..................................................................................................... 26
7.2.1 Measures for Heat Release in Designing the Board ................................................................................. 27
7.2.2 Heat Dissipation from the Periphery (Including the Casin g) ................................................................... 29
7.3 Caution <R> ..................................................................................................................................................... 30
7.3.1 Handling of Unused Pins ......................................................................................................................... 30
8. CC-Link Pins ................................................................................................................................................ 31
9. CC-Link IE Field Pins .................................................................................................................................. 33
9.1 Caution .............................................................................................................................................................. 33
10. External MCU/Memory Interface Pins ......................................................................................................... 34
10.1 External MCU Interface .................................................................................................................................... 35
10.1.1 Asynchronous-SRAM Supporting MCU Connection Mode ................................................................... 36
10.1.2 Synchronous-SRAM Supporting MCU Connection Mode ...................................................................... 38
10.1.3 Synchronous-Burst-Transfer Supporting MCU Connec tion Mode.......................................................... 40
10.2 External Memory Interface ............................................................................................................................... 44
10.2.1 Asynchronous SRAM MEMC ................................................................................................................. 44
10.2.2 Synchronous Burst Access MEM C ......................................................................................................... 47
11. Serial Flash ROM Connection Pins ............................................................................................................. 50
12. As ynchro nous Ser i al Int erfac e J Connec ti on Pins ...................................................................................... 51
13. I2C Connection Pins .................................................................................................................................... 52
14. CAN Pi ns ..................................................................................................................................................... 53
15. CSIH Pins <R> ............................................................................................................................................ 54
15.1 One Master and One Slave ............................................................................................................................... 54
15.2 One Master and Two Slaves ............................................................................................................................. 54
Contents-2
16. A/D Converter Pins ...................................................................................................................................... 55
17. JTAG/Trace Pins ......................................................................................................................................... 56
18. Implementation Conditions .......................................................................................................................... 60
19. Package Information .................................................................................................................................... 61
20. Mount Pad Information ................................................................................................................................ 62
21. BSCAN Information ..................................................................................................................................... 63
21.1 BSCAN Operating Conditions .......................................................................................................................... 63
21.2 Maximum Operating Frequency of TCK .......................................................................................................... 63
21.3 IDCODE ........................................................................................................................................................... 63
21.4 BSCAN Non-Supported Pins ............................................................................................................................ 64
21.5 How to Get BSDL ............................................................................................................................................ 65
22. IBIS Information ........................................................................................................................................... 66
23. Marking Information ..................................................................................................................................... 67
24. Countermeasure for Noise <R> .................................................................................................................. 68
24.1 Stopping Cl ock Output ..................................................................................................................................... 68
Contents-3
Description
Low level
This pin is connected to GND.
High level
This pin supplies VDD33 (3.3 V).
Frame GNDAnalog GND
GND
R18UZ0046EJ0200
R-IN32M4-CL2 User’s Manual: Board design edition Dec. 28, 2018
1. Overview
This manual is intended for being us ed by engi neers that work on a circuit and P C B design that is equipp ed with an
Ethernet communication LSI from the R-IN32M4-CL2 made by Renesas Electronics.
The target device is the R-IN32M4-CL2. It is recommended to stud y thi s manual carefully and to follow the
recommend ations duri ng the circ uit and board design.
1.1 Definition o f Pin Handling and Symbols in This Manual
Pin handling and symbols are defined as follows in this manual.
Table 1.1 Definition of Pin Handling
Figure 1.1 Definition of GND Symbols
R18UZ0046EJ0200 Page 1 of 68
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External Power Supply
Voltage[V]
Power Supplied to
External Pin Name
R-IN32M4
VDD33, AVDD
GbE-PHY
VDD33_GPHY
VDD25
2.5±0.125
GbE-PHY
VDD25A
PLL_VDD
VDD1A
R-IN32M4-CL2 User’s Manual: Board design edition 2. Power/Reset Pins
2. Power/Reset Pins
2.1 Power-On/Off Sequence
Table 2.1 lists the external power supply to the R-IN32M4 and GbE-PHY. In addition, Figure 2.1 shows the power on/off
sequence. (GbE stands for Gigabit Ethernet.)
Though ther e is no spec ific order for supplying the power-supply voltages, we recommend supplying the VDD33
external power after supplying the VDD10 external power. Conversely, we recommend shutting down VDD10 after
VDD33.
If VDD33 is supplied first, the input/output modes of I/O buffer are unstable rather than fixed during the period from
VDD33 rising to VDD10 rising, and thus caution is required on this point.
Make sure to confirm that the power supply voltage is stable before applying 3.3 V to I/O pins.
Table 2.1 External Power Supply
VDD33 3.3±0.165
VDD10 1.0±0.05 R-IN32M4 VDD10
GbE-PHY VDD1
R18UZ0046EJ0200 Page 2 of 68
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GND
90
% VDD33
90%
VDD33
10%
VDD10
10
% VDD10
95
%
VDD33
95
%
VDD25
95
%
VDD10
50 ms
100
ms
50
ms
VDD
33
VDD
25
VDD
10
100 ms
External power supply
R-
IN32M4
-CL2
R-IN32M4
GbE-PHY
2.
5±0.125V
VDD33
VDD10 VDD10
VDD33 VDD25
3.3±0.165V
1.0±0.05V
R-IN32M4-CL2 User’s Manual: Board design edition 2. Power/Reset Pins
(1) Power on
Supply power in a way that satisfies both conditions below.
1. The time from whichever is first to do so among VDD33, VDD25, and VDD10 reaches 10% VDD until all power
supplies exceed 90% VDD is within 100 ms.
2. The time from whichever is first to do so among VDD33, VDD25, and VDD10 reaches 95% VDD until all power
supplies exceed 95% VDD is within 50 ms.
(2) Power off
Supply power in a way that satisfies both conditions below.
1. The time from whichever is first to do so among VDD33, VDD25, and VDD10 reaches 90% until all power
supplies fall below 10% VDD is within 100 ms.
2. The time from whichever is first to do so among VDD33, VDD25, and VDD10 reaches 95% until all power
supplies fall below 95% VDD is within 50 ms.
Figure 2.1 Power-On/Off Sequence
Figure 2.2 Power Supply Channel to R-IN32M4 Chip and GbE-PHY
R18UZ0046EJ0200 Page 3 of 68
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Pin Name
Function
Reference for Connection Example
PLL_VDD
PLL power supply (1.0 V)
See section 4, PLL Power Supply Pins.
PLL_GND
PLL_GND
See section 4, PLL Power Supply Pins.
regulator or DC-DC converter.
regulator or DC-DC converter.
GND
Ground potential for power supply (GND)
Connect GND of the system (board).
use the ferrite bead or the lik e.
use the ferrite bead or the lik e.
VDD33_GPHY
GbE-PHY internal power supply (3.3 V)
See Section 6.1, Power Supply Peripheral Circuit.
VDD25A
GbE-PHY analog power supply (2.5 V)
See Section 6.1, Power Supply Peripheral Circuit.
VDD1
GbE-PHY internal power supply (1.0 V)
See Section 6.1, Power Supply Peripheral Circuit.
VDD1A
GbE-PHY analog power supply (1.0 V)
See Section 6.1, Power Supply Peripheral Circuit.
R-IN32M4-CL2 User’s Manual: Board design edition 2. Power/Reset Pins
2.2 Power Supply Pins
This is a list of power supply pins of R-IN32M4-CL2. When designing with these pins, r efer to the connection example
as follows.
VDD33 R-IN32M4 I/O power supply (3.3 V) Supply power from the power unit such as a
VDD10 R-IN32M4 internal power supply (1.0 V) Supply power from the power unit such as a
AVDD Analog power supply for A/D converter
(3.3 V)
AGND Analog power supply for A/D converter
(GND)
Supply power from the power unit such as a
regulator or DC-DC converter.
To reduce the effect of noise, it is recommended to
Connect GND of the system (board).
To reduce the effect of noise, it is recommended to
R18UZ0046EJ0200 Page 4 of 68
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Pin Name
Function
Reference for Connection Example
RESETZ
Reset input
-
Link IE field)
TRSTZ
JTAG reset signal
See Section 17, JTAG/Trace Pins.
RSTOUTZ
External reset output
-
R-IN32M4-CL2 User’s Manual: Board design edition 2. Power/Reset Pins
2.3 Reset Pins
This is a list of rese t pins of R-IN32M4-CL2.
As a width at low level of at least 1 µs is required for the reset input signals, secure this by applying the low level of the
reset signal over the oscillation stabilization time of the external oscillator (25 MHz).
In addition, de-assert the RESETZ and HOTRESETZ signals after de-asserting t he P ONRZ signal.
HOTRESETZ Hot reset input (reset pin for bypass mode of CC-
PONRZ Power-on reset input for built-in RAM
-
-
R18UZ0046EJ0200 Page 5 of 68
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Pin Name
Attribute
Function
In external clock input mode (OSCTH = 1), drive XT1 to the low level.
input via XT2.
High level: XT2 is to be connected to an oscillator.
Note:
Connection with an oscillator is recommended.
R-IN32M4-CL2 User’s Manual: Board design edition 3. Clock Input Pins
3. Clock Input Pins
3.1 Pin Functions
This is a list of pin functions of clock input pins.
XT1 Input Connects an external oscillator .
XT2 I/O Connects an external oscillator .
When OSCTH = 0, this pin functions as an output pin.
In external clock input mode (OSCTH = 1), the clock signal from an external oscillator is
OSCTH
Note
Input Selects the clock oscillation source to be conne cted to the clock pin .
Low level: XT1 and XT2 are to be connected to a resonator.
R18UZ0046EJ0200 Page 6 of 68
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R
-IN32M4-CL2
OSCTH
XT1 XT2
Board
GND pattern
R-IN32M4-CL2 User’s Manual: Board design edition 3. Clock Input Pins
3.2 Notes on Configuring the Oscillation Circuit
As the R-IN32M4-CL2 includes an oscillation block, oscillation circuits are easily configurable by externally connecting
a resonator and components for external constants. Though configuring an osci lla tion circuit is easy, the configured
circuit is analog and operates at a high frequency, so notes that differ for logic become applicable.
To achieve stable operation of the o scilla tion circuit, set components for external constants to the optimum values
(capacitors on the input and output sides, and limiting resistors) and observe the following points required for an analog
circuit.
・Place the oscillation circuit near the R-IN32M4-CL2.
・Place the oscillation circuit as far as p ossible from high-frequency input pins such as clock pins.
・Place the resonators and components for external constants immediately clo se to the input and output pins of
oscillation circuit, and keep the connections as short as possible.
・Make the ground connections of the capacitors to the GND pins of R-IN32M4-CL2 as short and thick as possible.
・Make the lead wires between the resonator and capacitors as short as possible.
・Surround the components for external constant parts by as muc h GND wiring as is possible.
Figure 3.1 Example of GND Pattern for the Components for Ex ternal Constants
R18UZ0046EJ0200 Page 7 of 68
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R-IN32M4-CL2 User’s Manual: Board design edition 3. Clock Input Pins
In addition, the following points to note should be observed in evaluating and determining the external constants.
・The range o f oscillating operati on may vary due to the dielectric constant of the board’s material, so use the actual
printed circuit board that will be used in the finished des ign.
・Check use of the board with the developed R-IN32M4-CL2 and the actual resonator to be mounted on it.
R18UZ0046EJ0200 Page 8 of 68
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(1) Resonator input mode (2) External clock input mode
OSCTH
XT1
XT2
Resonator
C
1
C
2
Rd
OSCTH
XT1
XT2
Though Rd is an element to suppress the
excitation current and negative resistance of the
resonator, it may not be required depending on
the resonator to be used.
In external clock input mode, drive
XT1 to the low level.
R-IN32M4-CL2 R-IN32M4-CL2
VDD33 (3.3 V)
:
The input of
When
corresponding
Renesas
•
•
https://global.kyocera.com/prdct/electro/product/crystal-device/
R-IN32M4-CL2 User’s Manual: Board design edition 3. Clock Input Pins
3.3 Configuration Example of Oscillation Circuits
The following figure shows the configuration example of oscillation circu its.
Figure 3.2 Configuration Example of the Oscillation Circuit
Caution
a resonator is to be used, contact the resonator manufacturer and ask for a
Nihon Dempa Kogyo Co., Ltd. (NDK)
http://www.ndk.com/en/index.html
KYOCERA Crystal Device Corporation
the R-IN32M4-CL2 is fixed to 25 MHz.
part number and external constants.
recommends the following oscillator and resonator manufacturers.
R18UZ0046EJ0200 Page 9 of 68
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C
1
PLL
PLL_GND
PLL_VDD
R
-
IN32
M
4-
CL2
VDD10 (1.0 V)
C
2
C1
: 0.
1-µ
F ceramic capacitor
C2: ≥ 4.7-µF capacitor
FB
FB
FB: Impedance
: 600
Ω at
100 MHz / DC resistance component
: 0.3
Ω or below
Reference ferrite beads
: TDK MPZ2012S601
A, MPZ
1608S601A
:
Place C1
If C2 is not placed immediately close to R-IN32M4-CL2, this will not cause any problems.
R-IN32M4-CL2 User’s Manual: Board design edition 4. PLL Power Supply Pins
4. PLL Power Supply Pins
The PLL circuit is susceptible to noise. To reduce the influence of noise, it is recommended to place filters in the power
supply pins of the PLL. In addition, to reduce the effects of noise between the power supplies for the board and PLL, the
use of ferrite beads is recommended.
4.1 Recommended Configuration of Filter
Figure 4.1 shows the rec ommended configurati on of the filter for the PLL po wer supply pins.
Figure 4.1 Recommended Configuration of Filter
Caution
immediately close to R-IN32M4-CL2.
R18UZ0046EJ0200 Page 10 of 68
Dec. 28, 2018
PLL_
GND
PLL_
VDD
C1
Pay particular attention to the effects of
noise from signals with wiring running
parallel to these lines in this region.
C2
FB
GND
FB
Power supply
n:
PLL_VDD and P
Longer
more readily leading to effects.
R-IN32M4-CL2 User’s Manual: Board design edition 4. PLL Power Supply Pins
4.2 Notes on Placement of Peripheral Components
The 0.1-µF ceramic capacitor (C1) should be placed immediately close to R-IN32M4-CL2 (in the immediate vicinity of
the pin).
Figure 4.2 is a schematic view from below the board.
In addition, the wiring pattern s for the electrolytic capacitor (C2) and ferrite beads running parallel to other signal lines
should be avoided.
Figure 4.2 Schematic View from Below the Board
Cautio
wiring leads to stronger crosstalk because the LC components of the wiring increase,
LL_GND lines should be as short and thick as possible in PCB wiring.
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R-IN32M4-CL2 User’s Manual: Board design edition 5. GPIO Port Pin s
5. GPIO Port Pins
GPIO is a general-purpose I/O port. As for the internal configur ation, see the section in the following document.
Section 7, Port Functions in the R-IN32M4-CL2 User’s Manual
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10 µF
10 µF
10 µF
For the number
of pins
R-IN32M4-CL2 power
VDD1A
VDD1A
VDD1
VDD1
VDD1
VDD1
VDD25A
VDD25A
VDD25A
3.3 V
power plane
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
VDD33_GPHY
PLL_VDD
VDD10VDD33
GbE-PHY power
Place these
capacitors as close
to the respective
power source pins as
is possible.
Place these
capacitors as close
to the respective
power source pins
as is possible.
1.0 V
power plane
2.5 V
power plane
AVDD
◎ Decoupling capacitors (bypass capacitors)
Placing one within 0.5 inches of each power supply
pin is preferable.
Give priority to the placement of bypass capacitors
for GbE-PHY power pins. When placing bypass
capacitors for all of the R-IN power supply pins is
difficult, arrange one for every two or three pins.
47 µF 10 µF
10 µF
See Section 4, PLL
Power Supply Pins.
See Section 15, A/D
Converter Pins.
R-IN power
0.1 µF
Ferrite
bead
Ferrite
bead
47 µF 10 µF
R-IN32M4-CL2 User’s Manual: Board design edition 6. Gigabit Ethernet PHY Pins
6. Gigabit Ethernet PHY Pins
Since the Gigabit Ethernet PHY interface handles high-speed transfer, designing the board pattern for it and other
components requires full consideration on numerous points.
Design it in accord with the advice in this section.
6.1 Power Supply Peripheral Circuit
6.1.1 Circuit Configuration
Figure 6.1 Configuration of Gigabit Ethernet PH Y Power Supply Peripheral Circ uit
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Manufacturer
Part Number
Capacitors
TDK
C32165R1C476M1160AB
47 µF
TDK
C2012X5R1C106K085AC
10 µF
TDK
C0603X5R0J104K030BC
0.1 µF
Manufacturer
Part Number
Impedance
Rated Current
Capacitors
muRata
BLM18PG121SN1
120Ω±25%
2 A
50mΩ
muRata
BLM21PG121SN1
120Ω±25%
3 A
30mΩ
R-IN32M4-CL2 User’s Manual: Board design edition 6. Gigabit Ethernet PHY Pins
6.1.2 Recommended Components
(1) Ceramic capacitors
We recommend using components that satisfy the following conditio ns.
Capacitors: 47 µF, 10 µF, and 0.1 µF
Thermal characteristic: X5R or X7R
ESR: No more than 0.1Ω (from 100 kHz to 100 MHz)
Table 6.1 Example of Recommended Components of Ceramic Capacitors
(2) Ferrite beads
We recommend using components that satisfy the following conditions.
Impedance: At least 80Ω (at 100 MHz)
Use beads with a high impedance in which the resistive component is dominant.
Rated current: At least 2 A
DC resistance: No more than 50mΩ
Figure 6.2 Example of Recommended Impedance Characteristics with Frequency of Ferrite Beads
Table 6.2 Example of Recommended Components of Ferrite Beads
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Remark:
n = 0, 1
R-IN32M4-CL2 User’s Manual: Board design edition 6. Gigabit Ethernet PHY Pins
6.2 Peripheral Circuit o f Pulse Tr ans f or mer
An example of the circuit configuration for the Gigabit Ethernet PHY, pulse transformers, and RJ-45 connector, and
recommended pulse transformer products are shown below.
6.2.1 Example of Circuit Configuration
The circuits should be connected as shown in the following figure.
Figure 6.3 Peripheral Connection Example of Pulse Transformer
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:
We
The impedance is 85, 100, or 115Ω
For details, contact the corresponding manufacturer.
Manufacturer
Product Type Name
Pulse
H5008NL
R-IN32M4-CL2 User’s Manual: Board design edition 6. Gigabit Ethernet PHY Pins
6.2.2 Recommended Components
We recommend using pulse transformer that satisfy the following conditions.
We also recommend the constitut i on illustrated in Transformer of Fig6.3.
Common-mode chokes are not required on the R-IN32M4-CL2 (PHY side) and is mounted on the connector.
Winding ratio: 1:1 (±2% or less, or ±3%) recommended
Return loss (see Figure 6.4): -18dB or le ss (1.0 MHz to 40 MHz)
-(12-20log(f/80))dB or less (40 MHz to 100MHz) *f: Frequency
Caution
recommend as little variation in return loss from 1.0 MHz to 40 MHz as possible.
.
Figure 6.4 Example of Return Loss of Pulse Transformer
Recommended components of the pulse transformer are as listed below.
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1.0µF
2kΩ
REF_REXT
REF_FILT
Pla c e the wiring separately from that for other high-frequency
signals, but pl ac e the components close to the pins.
Join the wires
at a single
point, and
connect this to
GND.
Pla c e GND wiring as a guard.
R-IN32M4-CL2 User’s Manual: Board design edition 6. Gigabit Ethernet PHY Pins
6.3 REF_REXT and REF_FILT Pins
The method of handling the REF_REXT and REF_FILT pins and recommended values for the connected components
are shown below.
6.3.1 Example of Circuit Configuration
Figure 6.5 Example of Circuit Configuration for REF_REXT and REF_FILT
6.3.2 Recommended Resistors
We recommend using components that satisfy the following conditions.
Resistance value: 2kΩ, 1% accuracy
Rated power: At least 0.0625 W
6.3.3 Recommended Ceramic Capacitors
We recommend using components that satisfy the following conditions.
Capacitor: 1.0 µF, 10% accuracy
Thermal characteristic: C0G, X7R, or X5R
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