RENESAS H8-3664 User Manual

REJ09B0142-0500Z

The revision list can be viewed directly by 
clicking the title page.

The revision list summarizes the locations of 
revisions and additions. Details should always 
be checked by referring to the relevant text.

16

H8/3664Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8 Family/H8/300H Tiny Series

H8/3664N HD64N3664
H8/3664F HD64F3664,
H8/3664 HD6433664,
H8/3663 HD6433663,
H8/3662 HD6433662,
H8/3661 HD6433661,
H8/3660 HD6433660

Rev.5.00
Revision Date: Mar. 18, 2004

Rev. 5.00, 03/04, page ii of xxviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 5.00, 03/04, page iii of xxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

Rev. 5.00, 03/04, page iv of xxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 5.00, 03/04, page v of xxviii

Preface

The H8/3664 Group are single-chip microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/3664 Group in the

design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8/3664 Group to the target users.
Refer to the H8/300H Series Programming Manual for a detailed description of the
instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8/300H Series Programming Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 19,
List of Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Notes:

When using the on-chip emulator (E10T) for H8/3664 program development and debugging, the
following restrictions must be noted (the on-chip debugging emulator (E7) can also be used).

1. The NMI pin is reserved for the E10T, and cannot be used.

2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.

3. Area H’7000 to H’7FFF is used by the E10T, and is not available to the user.

4. Area H’F780 to H’FB7F must on no account be accessed.

5. When the E10T is used, address breaks can be set as either available to the user or for use by
the E10T. If address breaks are set as being used by the E10T, the address break control
registers must not be accessed.

Rev. 5.00, 03/04, page vi of xxviii

6. When the E10T is used, NMI is an input/output pin (open-drain in output mode), P85 and P87

are input pins, and P86 is an output pin.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/

H8/3664 Group manuals:

Document Title Document No.

H8/3664 Group Hardware Manual This manual

H8/300H Series Programming Manual ADE-602-053

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282

H8S, H8/300 Series High-Performance Embedded Workshop,
High-Performance Debugging Interface Tutorial

High-Performance Embedded Workshop User's Manual ADE-702-201

ADE-702-247

ADE-702-231

Application notes:

Document Title Document No.

Single Power Supply F-ZTATTM On-Board Programming ADE-502-055

Rev. 5.00, 03/04, page vii of xxviii

Rev. 5.00, 03/04, page viii of xxviii

Contents

Section 1 Overview............................................................................................1

1.1 Features............................................................................................................................. 1

1.2 Internal Block Diagram..................................................................................................... 2

1.3 Pin Arrangement ............................................................................................................... 4

1.4 Pin Functions ....................................................................................................................8

Section 2 CPU....................................................................................................11

2.1 Address Space and Memory Map .....................................................................................12

2.2 Register Configuration...................................................................................................... 15

2.2.1 General Registers................................................................................................. 16

2.2.2 Program Counter (PC) .........................................................................................17

2.2.3 Condition-Code Register (CCR).......................................................................... 17

2.3 Data Formats..................................................................................................................... 19

2.3.1 General Register Data Formats............................................................................ 19

2.3.2 Memory Data Formats ......................................................................................... 21

2.4 Instruction Set ................................................................................................................... 22

2.4.1 Table of Instructions Classified by Function ....................................................... 22

2.4.2 Basic Instruction Formats ....................................................................................31

2.5 Addressing Modes and Effective Address Calculation..................................................... 33

2.5.1 Addressing Modes ............................................................................................... 33

2.5.2 Effective Address Calculation .............................................................................36

2.6 Basic Bus Cycle ................................................................................................................ 38

2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 38

2.6.2 On-Chip Peripheral Modules ............................................................................... 39

2.7 CPU States ........................................................................................................................40

2.8 Usage Notes ......................................................................................................................41

2.8.1 Notes on Data Access to Empty Areas ................................................................41

2.8.2 EEPMOV Instruction........................................................................................... 41

2.8.3 Bit Manipulation Instruction................................................................................ 41

Section 3 Exception Handling ...........................................................................47

3.1 Exception Sources and Vector Address ............................................................................ 47

3.2 Register Descriptions........................................................................................................ 49

3.2.1 Interrupt Edge Select Register 1 (IEGR1) ........................................................... 49

3.2.2 Interrupt Edge Select Register 2 (IEGR2) ........................................................... 50

3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................51

3.2.4 Interrupt Flag Register 1 (IRR1).......................................................................... 52

3.2.5 Wakeup Interrupt Flag Register (IWPR) .............................................................53

3.3 Reset Exception Handling................................................................................................. 54

Rev. 5.00, 03/04, page ix of xxviii

3.4 Interrupt Exception Handling ...........................................................................................54

3.4.1 External Interrupts ............................................................................................... 54

3.4.2 Internal Interrupts ................................................................................................55

3.4.3 Interrupt Handling Sequence ............................................................................... 56

3.4.4 Interrupt Response Time...................................................................................... 57

3.5 Usage Notes ...................................................................................................................... 59

3.5.1 Interrupts after Reset............................................................................................ 59

3.5.2 Notes on Stack Area Use ..................................................................................... 59

3.5.3 Notes on Rewriting Port Mode Registers ............................................................ 59

Section 4 Address Break ...................................................................................61

4.1 Register Descriptions........................................................................................................ 61

4.1.1 Address Break Control Register (ABRKCR) ...................................................... 62

4.1.2 Address Break Status Register (ABRKSR) ......................................................... 63

4.1.3 Break Address Registers (BARH, BARL)........................................................... 63

4.1.4 Break Data Registers (BDRH, BDRL) ................................................................ 63

4.2 Operation ..........................................................................................................................64

4.3 Usage Notes ...................................................................................................................... 65

Section 5 Clock Pulse Generators .....................................................................69

5.1 System Clock Generator ................................................................................................... 70

5.1.1 Connecting Crystal Resonator ............................................................................. 70

5.1.2 Connecting Ceramic Resonator ........................................................................... 71

5.1.3 External Clock Input Method .............................................................................. 71

5.2 Subclock Generator........................................................................................................... 72

5.2.1 Connecting 32.768-kHz Crystal Resonator .........................................................72

5.2.2 Pin Connection when Not Using Subclock.......................................................... 73

5.3 Prescalers ..........................................................................................................................73

5.3.1 Prescaler S ...........................................................................................................73

5.3.2 Prescaler W.......................................................................................................... 73

5.4 Usage Notes ...................................................................................................................... 73

5.4.1 Note on Resonators.............................................................................................. 73

5.4.2 Notes on Board Design........................................................................................ 75

Section 6 Power-Down Modes.......................................................................... 77

6.1 Register Descriptions........................................................................................................ 78

6.1.1 System Control Register 1 (SYSCR1)................................................................. 78

6.1.2 System Control Register 2 (SYSCR2)................................................................. 81

6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................82

6.2 Mode Transitions and States of LSI.................................................................................. 83

6.2.1 Sleep Mode.......................................................................................................... 85

6.2.2 Standby Mode...................................................................................................... 86

6.2.3 Subsleep Mode..................................................................................................... 86

Rev. 5.00, 03/04, page x of xxviii

6.2.4 Subactive Mode ...................................................................................................87

6.3 Operating Frequency in Active Mode............................................................................... 87

6.4 Direct Transition ...............................................................................................................87

6.4.1 Direct Transition from Active Mode to Subactive Mode ....................................87

6.4.2 Direct Transition from Subactive Mode to Active Mode ....................................88

6.5 Module Standby Function................................................................................................. 88

6.6 Usage Note........................................................................................................................ 88

Section 7 ROM ..................................................................................................89

7.1 Block Configuration.......................................................................................................... 89

7.2 Register Descriptions........................................................................................................ 90

7.2.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 91

7.2.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 92

7.2.3 Erase Block Register 1 (EBR1) ........................................................................... 92

7.2.4 Flash Memory Power Control Register (FLPWCR)............................................ 93

7.2.5 Flash Memory Enable Register (FENR).............................................................. 93

7.3 On-Board Programming Modes........................................................................................ 93

7.3.1 Boot Mode ...........................................................................................................94

7.3.2 Programming/Erasing in User Program Mode.....................................................97

7.4 Flash Memory Programming/Erasing............................................................................... 98

7.4.1 Program/Program-Verify..................................................................................... 98

7.4.2 Erase/Erase-Verify............................................................................................... 100

7.4.3 Interrupt Handling when Programming/Erasing Flash Memory..........................101

7.5 Program/Erase Protection .................................................................................................103

7.5.1 Hardware Protection ............................................................................................103

7.5.2 Software Protection..............................................................................................103

7.5.3 Error Protection....................................................................................................103

7.6 Programmer Mode ............................................................................................................104

7.7 Power-Down States for Flash Memory............................................................................. 104

Section 8 RAM ..................................................................................................105

Section 9 I/O Ports.............................................................................................107

9.1 Port 1................................................................................................................................. 107

9.1.1 Port Mode Register 1 (PMR1) ............................................................................. 108

9.1.2 Port Control Register 1 (PCR1) ...........................................................................109

9.1.3 Port Data Register 1 (PDR1)................................................................................109

9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................... 110

9.1.5 Pin Functions ....................................................................................................... 110

9.2 Port 2................................................................................................................................. 112

9.2.1 Port Control Register 2 (PCR2) ...........................................................................113

9.2.2 Port Data Register 2 (PDR2)................................................................................113

9.2.3 Pin Functions ....................................................................................................... 114

Rev. 5.00, 03/04, page xi of xxviii

9.3 Port 5................................................................................................................................. 115

9.3.1 Port Mode Register 5 (PMR5)............................................................................. 116

9.3.2 Port Control Register 5 (PCR5) ........................................................................... 117

9.3.3 Port Data Register 5 (PDR5) ...............................................................................117

9.3.4 Port Pull-Up Control Register 5 (PUCR5)........................................................... 118

9.3.5 Pin Functions ....................................................................................................... 118

9.4 Port 7................................................................................................................................. 120

9.4.1 Port Control Register 7 (PCR7) ........................................................................... 121

9.4.2 Port Data Register 7 (PDR7) ...............................................................................121

9.4.3 Pin Functions ....................................................................................................... 122

9.5 Port 8................................................................................................................................. 123

9.5.1 Port Control Register 8 (PCR8) ........................................................................... 123

9.5.2 Port Data Register 8 (PDR8) ...............................................................................124

9.5.3 Pin Functions ....................................................................................................... 124

9.6 Port B................................................................................................................................ 126

9.6.1 Port Data Register B (PDRB) .............................................................................. 127

Section 10 Timer A ...........................................................................................129

10.1 Features............................................................................................................................. 129

10.2 Input/Output Pins.............................................................................................................. 130

10.3 Register Descriptions........................................................................................................ 130

10.3.1 Timer Mode Register A (TMA)........................................................................... 131

10.3.2 Timer Counter A (TCA) ......................................................................................132

10.4 Operation ..........................................................................................................................132

10.4.1 Interval Timer Operation .....................................................................................132

10.4.2 Clock Time Base Operation................................................................................. 133

10.4.3 Clock Output........................................................................................................ 133

10.5 Usage Note........................................................................................................................ 133

Section 11 Timer V ...........................................................................................135

11.1 Features............................................................................................................................. 135

11.2 Input/Output Pins.............................................................................................................. 136

11.3 Register Descriptions........................................................................................................ 137

11.3.1 Timer Counter V (TCNTV) ................................................................................. 137

11.3.2 Time Constant Registers A and B (TCORA, TCORB) ....................................... 137

11.3.3 Timer Control Register V0 (TCRV0) .................................................................. 138

11.3.4 Timer Control/Status Register V (TCSRV) ......................................................... 140

11.3.5 Timer Control Register V1 (TCRV1) .................................................................. 141

11.4 Operation ..........................................................................................................................142

11.4.1 Timer V Operation............................................................................................... 142

11.5 Timer V Application Examples ........................................................................................ 145

11.5.1 Pulse Output with Arbitrary Duty Cycle.............................................................. 145

11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input ............. 146

Rev. 5.00, 03/04, page xii of xxviii

11.6 Usage Notes ......................................................................................................................147

Section 12 Timer W...........................................................................................149

12.1 Features............................................................................................................................. 149

12.2 Input/Output Pins.............................................................................................................. 151

12.3 Register Descriptions........................................................................................................ 152

12.3.1 Timer Mode Register W (TMRW) ......................................................................153

12.3.2 Timer Control Register W (TCRW) .................................................................... 153

12.3.3 Timer Interrupt Enable Register W (TIERW) ..................................................... 155

12.3.4 Timer Status Register W (TSRW) .......................................................................155

12.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................157

12.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................158

12.3.7 Timer Counter (TCNT)........................................................................................ 159

12.3.8 General Registers A to D (GRA to GRD)............................................................ 159

12.4 Operation ..........................................................................................................................160

12.4.1 Normal Operation ................................................................................................160

12.4.2 PWM Operation ...................................................................................................164

12.5 Operation Timing.............................................................................................................. 168

12.5.1 TCNT Count Timing ........................................................................................... 168

12.5.2 Output Compare Output Timing.......................................................................... 168

12.5.3 Input Capture Timing........................................................................................... 169

12.5.4 Timing of Counter Clearing by Compare Match ................................................. 170

12.5.5 Buffer Operation Timing ..................................................................................... 170

12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match................................. 171

12.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................172

12.5.8 Timing of Status Flag Clearing............................................................................ 172

12.6 Usage Notes ......................................................................................................................173

Section 13 Watchdog Timer ..............................................................................177

13.1 Features............................................................................................................................. 177

13.2 Register Descriptions........................................................................................................ 177

13.2.1 Timer Control/Status Register WD (TCSRWD).................................................. 178

13.2.2 Timer Counter WD (TCWD)............................................................................... 179

13.2.3 Timer Mode Register WD (TMWD) ...................................................................179

13.3 Operation ..........................................................................................................................180

Section 14 Serial Communication Interface3 (SCI3) ........................................181

14.1 Features............................................................................................................................. 181

14.2 Input/Output Pins.............................................................................................................. 183

14.3 Register Descriptions........................................................................................................ 183

14.3.1 Receive Shift Register (RSR) .............................................................................. 184

14.3.2 Receive Data Register (RDR) .............................................................................. 184

14.3.3 Transmit Shift Register (TSR) ............................................................................. 184

Rev. 5.00, 03/04, page xiii of xxviii

14.3.4 Transmit Data Register (TDR)............................................................................. 184

14.3.5 Serial Mode Register (SMR) ............................................................................... 185

14.3.6 Serial Control Register 3 (SCR3) ........................................................................ 186

14.3.7 Serial Status Register (SSR) ................................................................................188

14.3.8 Bit Rate Register (BRR) ...................................................................................... 190

14.4 Operation in Asynchronous Mode .................................................................................... 195

14.4.1 Clock.................................................................................................................... 195

14.4.2 SCI3 Initialization................................................................................................ 196

14.4.3 Data Transmission ............................................................................................... 197

14.4.4 Serial Data Reception .......................................................................................... 199

14.5 Operation in Clocked Synchronous Mode........................................................................ 203

14.5.1 Clock.................................................................................................................... 203

14.5.2 SCI3 Initialization................................................................................................ 203

14.5.3 Serial Data Transmission ..................................................................................... 204

14.5.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 206

14.5.5 Simultaneous Serial Data Transmission and Reception....................................... 208

14.6 Multiprocessor Communication Function......................................................................... 210

14.6.1 Multiprocessor Serial Data Transmission ............................................................ 212

14.6.2 Multiprocessor Serial Data Reception ................................................................. 213

14.7 Interrupts........................................................................................................................... 217

14.8 Usage Notes ...................................................................................................................... 218

14.8.1 Break Detection and Processing .......................................................................... 218

14.8.2 Mark State and Break Sending ............................................................................ 218

14.8.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .................................................................... 218

14.8.4 Receive Data Sampling Timing and Reception Margin in

Asynchronous Mode............................................................................................ 219

Section 15 I2C Bus Interface (IIC)..................................................................... 221

15.1 Features............................................................................................................................. 221

15.2 Input/Output Pins.............................................................................................................. 223

15.3 Register Descriptions........................................................................................................ 223

15.3.1 I2C bus data register(ICDR)................................................................................. 224

15.3.2 Slave address register(SAR) ................................................................................ 226

15.3.3 Second slave address register(SARX) .................................................................226

15.3.4 I2C Bus Mode Register(ICMR)............................................................................ 227

15.3.5 I2C Bus Control Register(ICCR).......................................................................... 229

15.3.6 I2C Bus Status Register(ICSR)............................................................................. 232

15.3.7 Timer Serial Control Register(TSCR) .................................................................234

15.4 Operation ..........................................................................................................................235

15.4.1 I2C Bus Data Format............................................................................................ 235

15.4.2 Master Transmit Operation .................................................................................. 237

15.4.3 Master Receive Operation ................................................................................... 238

Rev. 5.00, 03/04, page xiv of xxviii

15.4.4 Slave Receive Operation...................................................................................... 241

15.4.5 Slave Transmit Operation ....................................................................................243

15.4.6 Clock Synchronous Serial Format .......................................................................245

15.4.7 IRIC Setting Timing and SCL Control ................................................................245

15.4.8 Noise Canceler ..................................................................................................... 247

15.4.9 Sample Flowcharts............................................................................................... 247

15.5 Usage Notes ......................................................................................................................252

Section 16 A/D Converter..................................................................................257

16.1 Features............................................................................................................................. 257

16.2 Input/Output Pins.............................................................................................................. 259

16.3 Register Description.......................................................................................................... 260

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 260

16.3.2 A/D Control/Status Register (ADCSR) ...............................................................261

16.3.3 A/D Control Register (ADCR) ............................................................................ 262

16.4 Operation ..........................................................................................................................263

16.4.1 Single Mode......................................................................................................... 263

16.4.2 Scan Mode ...........................................................................................................263

16.4.3 Input Sampling and A/D Conversion Time ......................................................... 264

16.4.4 External Trigger Input Timing............................................................................. 265

16.5 A/D Conversion Accuracy Definitions............................................................................. 266

16.6 Usage Notes ......................................................................................................................267

16.6.1 Permissible Signal Source Impedance ................................................................. 267

16.6.2 Influences on Absolute Accuracy ........................................................................267

Section 17 EEPROM .........................................................................................269

17.1 Features............................................................................................................................. 269

17.2 Input/Output Pins.............................................................................................................. 271

17.3 Register Description.......................................................................................................... 271

17.3.1 EEPROM Key Register (EKR)............................................................................ 271

17.4 Operation ..........................................................................................................................272

17.4.1 EEPROM Interface .............................................................................................. 272

17.4.2 Bus Format and Timing .......................................................................................272

17.4.3 Start Condition .....................................................................................................272

17.4.4 Stop Condition .....................................................................................................272

17.4.5 Acknowledge .......................................................................................................273

17.4.6 Slave Addressing ................................................................................................. 273

17.4.7 Write Operations.................................................................................................. 274

17.4.8 Acknowledge Polling........................................................................................... 275

17.4.9 Read Operation ....................................................................................................276

17.5 Usage Notes ......................................................................................................................278

17.5.1 Data Protection at VCC On/Off.............................................................................. 278

17.5.2 Write/Erase Endurance ........................................................................................278

Rev. 5.00, 03/04, page xv of xxviii

17.5.3 Noise Suppression Time ...................................................................................... 278

Section 18 Power Supply Circuit ......................................................................279

18.1 When Using Internal Power Supply Step-Down Circuit ..................................................279

18.2 When Not Using Internal Power Supply Step-Down Circuit............................................280

Section 19 List of Registers............................................................................... 281

19.1 Register Addresses (Address Order)................................................................................. 282

19.2 Register Bits...................................................................................................................... 285

19.3 Register States in Each Operating Mode .......................................................................... 288

Section 20 Electrical Characteristics .................................................................291

20.1 Absolute Maximum Ratings ............................................................................................. 291

20.2 Electrical Characteristics (F-ZTAT™ Version, F-ZTAT™ Version with EEPROM) ..... 291

20.2.1 Power Supply Voltage and Operating Ranges ..................................................... 291

20.2.2 DC Characteristics ............................................................................................... 293

20.2.3 AC Characteristics ............................................................................................... 299

20.2.4 A/D Converter Characteristics............................................................................. 303

20.2.5 Watchdog Timer Characteristics.......................................................................... 304

20.2.6 Flash Memory Characteristics ............................................................................. 305

20.2.7 EEPROM Characteristics .................................................................................... 307

20.3 Electrical Characteristics (Mask ROM Version) ..............................................................308

20.3.1 Power Supply Voltage and Operating Ranges ..................................................... 308

20.3.2 DC Characteristics ............................................................................................... 309

20.3.3 AC Characteristics ............................................................................................... 315

20.3.4 A/D Converter Characteristics............................................................................. 319

20.3.5 Watchdog Timer Characteristics.......................................................................... 320

20.4 Operation Timing.............................................................................................................. 320

20.5 Output Load Condition ..................................................................................................... 323

Appendix A Instruction Set ...............................................................................325

A.1 Instruction List.................................................................................................................. 325

A.2 Operation Code Map......................................................................................................... 340

A.3 Number of Execution States .............................................................................................343

A.4 Combinations of Instructions and Addressing Modes ......................................................354

Appendix B I/O Port Block Diagrams...............................................................355

B.1 I/O Port Block................................................................................................................... 355

B.2 Port States in Each Operating State .................................................................................. 371

Appendix C Product Code Lineup ....................................................................372

Appendix D Package Dimensions .....................................................................374

Rev. 5.00, 03/04, page xvi of xxviii

Appendix E EEPROM Stacked-Structure Cross-Sectional View .....................379

Main Revisions and Additions in this Edition .....................................................381

Index .........................................................................................................385

Rev. 5.00, 03/04, page xvii of xxviii

Rev. 5.00, 03/04, page xviii of xxviii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTATTM and Mask-ROM Versions ............. 2

Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTATTM Version with EEPROM .............3

Figure 1.3 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions

(FP-64E, FP-64A).......................................................................................................... 4

Figure 1.4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions

(FP-48F, FP-48B) ..........................................................................................................5

Figure 1.5 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions (DS-42S) ....... 6

Figure 1.6 Pin Arrangement of H8/3664N of F-ZTATTM Version with EEPROM (FP-64E) ........7

Section 2 CPU

Figure 2.1 Memory Map (1) ......................................................................................................... 12

Figure 2.1 Memory Map (2) ......................................................................................................... 13

Figure 2.1 Memory Map (3) ......................................................................................................... 14

Figure 2.2 CPU Registers .............................................................................................................15

Figure 2.3 Usage of General Registers .........................................................................................16

Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 17

Figure 2.5 General Register Data Formats (1).............................................................................. 19

Figure 2.5 General Register Data Formats (2).............................................................................. 20

Figure 2.6 Memory Data Formats................................................................................................. 21

Figure 2.7 Instruction Formats......................................................................................................32

Figure 2.8 Branch Address Specification in Memory Indirect Mode........................................... 35

Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................39

Figure 2.11 CPU Operation States................................................................................................ 40

Figure 2.12 State Transitions........................................................................................................ 41

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to

Same Address ............................................................................................................ 42

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................ 55

Figure 3.2 Stack Status after Exception Handling........................................................................ 57

Figure 3.3 Interrupt Sequence....................................................................................................... 58

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 59

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................61

Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 64

Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 65

Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 65

Figure 4.4 Operation when Another Interrupt is Accepted at

Address Break Setting Instruction ...............................................................................66

Rev. 5.00, 03/04, page xix of xxviii

Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to

Conditions not Being Satisfied .................................................................................... 67

Section 5 Clock Pulse Generators

Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69

Figure 5.2 Block Diagram of System Clock Generator................................................................ 70

Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70

Figure 5.4 Equivalent Circuit of Crystal Resonator......................................................................70

Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71

Figure 5.6 Example of External Clock Input................................................................................ 71

Figure 5.7 Block Diagram of Subclock Generator .......................................................................72

Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72

Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72

Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73

Figure 5.11 Example of Incorrect Board Design.......................................................................... 75

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ........................................................................................... 83

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration............................................................................90

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 97

Figure 7.3 Program/Program-Verify Flowchart ........................................................................... 99

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 102

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 107

Figure 9.2 Port 2 Pin Configuration............................................................................................ 112

Figure 9.3 Port 5 Pin Configuration............................................................................................ 115

Figure 9.4 Port 7 Pin Configuration............................................................................................ 120

Figure 9.5 Port 8 Pin Configuration............................................................................................ 123

Figure 9.6 Port B Pin Configuration...........................................................................................126

Section 10 Timer A

Figure 10.1 Block Diagram of Timer A .....................................................................................130

Section 11 Timer V

Figure 11.1 Block Diagram of Timer V .....................................................................................136

Figure 11.2 Increment Timing with Internal Clock.................................................................... 142

Figure 11.3 Increment Timing with External Clock................................................................... 143

Figure 11.4 OVF Set Timing...................................................................................................... 143

Figure 11.5 CMFA and CMFB Set Timing................................................................................ 143

Figure 11.6 TMOV Output Timing ............................................................................................ 144

Figure 11.7 Clear Timing by Compare Match............................................................................ 144

Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 144

Figure 11.9 Pulse Output Example............................................................................................. 145

Rev. 5.00, 03/04, page xx of xxviii

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input.......................................146

Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 147

Figure 11.12 Contention between TCORA Write and Compare Match..................................... 148

Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 148

Section 12 Timer W

Figure 12.1 Timer W Block Diagram......................................................................................... 151

Figure 12.2 Free-Running Counter Operation............................................................................ 160

Figure 12.3 Periodic Counter Operation..................................................................................... 161

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 161

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................162

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................162

Figure 12.7 Input Capture Operating Example........................................................................... 163

Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 163

Figure 12.9 PWM Mode Example (1) ........................................................................................ 164

Figure 12.10 PWM Mode Example (2) ......................................................................................165

Figure 12.11 Buffer Operation Example (Output Compare) ......................................................165

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0)................................ 166

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1)................................ 167

Figure 12.14 Count Timing for Internal Clock Source............................................................... 168

Figure 12.15 Count Timing for External Clock Source.............................................................. 168

Figure 12.16 Output Compare Output Timing ...........................................................................169

Figure 12.17 Input Capture Input Signal Timing........................................................................ 169

Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 170

Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................170

Figure 12.20 Buffer Operation Timing (Input Capture) .............................................................171

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 171

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 172

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................172

Figure 12.24 Contention between TCNT Write and Clear .........................................................173

Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 174

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW

Occur at the Same Timing .....................................................................................175

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 177

Figure 13.2 Watchdog Timer Operation Example...................................................................... 180

Section 14 Serial Communication Interface3 (SCI3)

Figure 14.1 Block Diagram of SCI3........................................................................................... 182

Figure 14.2 Data Format in Asynchronous Communication ...................................................... 195

Rev. 5.00, 03/04, page xxi of xxviii

Figure 14.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) ..............195

Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 196

Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)............................................................................ 197

Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 198

Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)............................................................................ 199

Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode)(1)....................... 201

Figure 14.8 Sample Serial Reception Data Flowchart (2) .......................................................... 202

Figure 14.9 Data Format in Clocked Synchronous Communication ..........................................203

Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 204

Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)................ 205

Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 206

Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)......................207

Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode) ............................................................................... 209

Figure 14.15 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)........................................... 211

Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart........................................ 212

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 214

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 215

Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 216

Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 219

Section 15 I2C Bus Interface (IIC)
Figure 15.1 Block Diagram of I

Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master).............................. 223

Figure 15.3 I2C Bus Data Formats (I2C Bus Formats)................................................................ 236

Figure 15.4 I2C Bus Timing........................................................................................................ 236

Figure 15.5 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0)................. 238

Figure 15.6 Master Receive Mode Operation Timing Example (1)

(MLS = ACKB = 0, WAIT = 1) ..............................................................................240

Figure 15.6 Master Receive Mode Operation Timing Example (2)

(MLS = ACKB = 0, WAIT = 1) ..............................................................................240

Figure 15.7 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ........ 242

Figure 15.8 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ........ 243

Figure 15.9 Example of Slave Transmit Mode Operation Timing (MLS = 0) ........................... 244

Figure 15.10 I2C Bus Data Format (Serial Format).................................................................... 245

Figure 15.11 IRIC Setting Timing and SCL Control.................................................................. 246

Figure 15.12 Block Diagram of Noise Canceler......................................................................... 247

Figure 15.13 Sample Flowchart for Master Transmit Mode ......................................................248

Rev. 5.00, 03/04, page xxii of xxviii

2

C Bus Interface ....................................................................... 222

Figure 15.14 Sample Flowchart for Master Receive Mode ........................................................ 249

Figure 15.15 Sample Flowchart for Slave Receive Mode .......................................................... 250

Figure 15.16 Sample Flowchart for Slave Transmit Mode......................................................... 251

Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance

for Retransmission................................................................................................. 256

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter ...........................................................................258

Figure 16.2 A/D Conversion Timing.......................................................................................... 264

Figure 16.3 External Trigger Input Timing ................................................................................ 265

Figure 16.4 A/D Conversion Accuracy Definitions (1).............................................................. 266

Figure 16.5 A/D Conversion Accuracy Definitions (2).............................................................. 267

Figure 16.6 Analog Input Circuit Example................................................................................. 268

Section 17 EEPROM

Figure 17.1 Block Diagram of EEPROM................................................................................... 270

Figure 17.2 EEPROM Bus Format and Bus Timing ..................................................................272

Figure 17.3 Byte Write Operation ..............................................................................................274

Figure 17.4 Page Write Operation ..............................................................................................275

Figure 17.5 Current Address Read Operation............................................................................. 276

Figure 17.6 Random Address Read Operation ........................................................................... 277

Figure 17.7 Sequential Read Operation (when current address read is used)............................. 278

Section 18 Power Supply Circuit

Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................279

Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............280

Section 20 Electrical Characteristics

Figure 20.1 System Clock Input Timing.....................................................................................320

Figure 20.2 RES Low Width Timing.......................................................................................... 321

Figure 20.3 Input Timing............................................................................................................ 321

Figure 20.4 I2C Bus Interface Input/Output Timing................................................................... 321

Figure 20.5 SCK3 Input Clock Timing.......................................................................................322

Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode.................................... 322

Figure 20.7 EEPROM Bus Timing............................................................................................. 323

Figure 20.8 Output Load Circuit................................................................................................. 323

Appendix B I/O Port Block Diagrams

Figure B.1 Port 1 Block Diagram (P17) .....................................................................................355

Figure B.2 Port 1 Block Diagram (P16 to P14).......................................................................... 356

Figure B.3 Port 1 Block Diagram (P12, P11)............................................................................. 357

Figure B.4 Port 1 Block Diagram (P10) .....................................................................................358

Figure B.5 Port 2 Block Diagram (P22) .....................................................................................359

Figure B.6 Port 2 Block Diagram (P21) .....................................................................................360

Figure B.7 Port 2 Block Diagram (P20) .....................................................................................361

Figure B.8 Port 5 Block Diagram (P57, P56)............................................................................. 362

Rev. 5.00, 03/04, page xxiii of xxviii

Figure B.9 Port 5 Block Diagram (P55) ..................................................................................... 363

Figure B.10 Port 5 Block Diagram (P54 to P50)........................................................................ 364

Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 365

Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 366

Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 367

Figure B.14 Port 8 Block Diagram (P87 to P85)........................................................................ 368

Figure B.15 Port 8 Block Diagram (P84 to P81)........................................................................ 369

Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 370

Figure B.17 Port B Block Diagram (PB7 to PB0)...................................................................... 371

Appendix D Package Dimensions

Figure D.1 FP-64E Package Dimensions ...................................................................................374

Figure D.2 FP-64A Package Dimensions................................................................................... 375

Figure D.3 FP-48F Package Dimensions.................................................................................... 376

Figure D.4 FP-48B Package Dimensions ...................................................................................377

Figure D.5 DP-42S Package Dimensions................................................................................... 378

Appendix E EEPROM Stacked-Structure Cross-Sectional View

Figure E.1 EEPROM Stacked-Structure Cross-Sectional View................................................. 379

Rev. 5.00, 03/04, page xxiv of xxviii

Tables

Section 1 Overview

Table 1.1 Pin Functions ............................................................................................................ 8

Section 2 CPU
Table 2.1

Table 2.2 Data Transfer Instructions.......................................................................................23

Table 2.3 Arithmetic Operations Instructions (1) ...................................................................24

Table 2.3 Arithmetic Operations Instructions (2) ...................................................................25

Table 2.4 Logic Operations Instructions................................................................................. 26

Table 2.5 Shift Instructions..................................................................................................... 26

Table 2.6 Bit Manipulation Instructions (1)............................................................................ 27

Table 2.6 Bit Manipulation Instructions (2)............................................................................ 28

Table 2.7 Branch Instructions................................................................................................. 29

Table 2.8 System Control Instructions.................................................................................... 30

Table 2.9 Block Data Transfer Instructions ............................................................................ 31

Table 2.10 Addressing Modes .................................................................................................. 33

Table 2.11 Absolute Address Access Ranges........................................................................... 34

Table 2.12 Effective Address Calculation (1)........................................................................... 36

Table 2.12 Effective Address Calculation (2)........................................................................... 37

Section 3 Exception Handling
Table 3.1

Table 3.2 Interrupt Wait States ...............................................................................................57

Operation Notation ................................................................................................. 22

Exception Sources and Vector Address .................................................................. 48

Section 4 Address Break
Table 4.1

Section 5 Clock Pulse Generators
Table 5.1

Section 6 Power-Down Modes
Table 6.1

Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling........ 84

Table 6.3 Internal State in Each Operating Mode................................................................... 85

Section 7 ROM
Table 7.1

Table 7.2 Boot Mode Operation .............................................................................................96

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate

Table 7.4 Reprogram Data Computation Table .................................................................... 100

Table 7.5 Additional-Program Data Computation Table...................................................... 100

Table 7.6 Programming Time............................................................................................... 100

Access and Data Bus Used .....................................................................................63

Crystal Resonator Parameters................................................................................. 71

Operating Frequency and Waiting Time................................................................. 80

Setting Programming Modes ..................................................................................94

is Possible ...............................................................................................................97

Rev. 5.00, 03/04, page xxv of xxviii

Table 7.7 Flash Memory Operating States............................................................................ 104

Section 10 Timer A
Table 10.1

Section 11 Timer V
Table 11.1

Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 139

Section 12 Timer W
Table 12.1

Table 12.2 Pin Configuration.................................................................................................. 151

Section 14 Serial Communication Interface3 (SCI3)
Table 14.1

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 191

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 192

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 193

Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................193

Table 14.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 194

Table 14.5 SSR Status Flags and Receive Data Handling...................................................... 200

Table 14.6 SCI3 Interrupt Requests........................................................................................ 217

Pin Configuration.................................................................................................. 130

Pin Configuration.................................................................................................. 136

Timer W Functions ............................................................................................... 150

Pin Configuration.................................................................................................. 183

Section 15 I2C Bus Interface (IIC)
Table 15.1

Table 15.2 Communication Format........................................................................................ 227

Table 15.3 I2C Transfer Rate .................................................................................................. 229

Table 15.4 Flags and Transfer States...................................................................................... 235

Table 15.5 I2C Bus Timing (SCL and SDA Output) .............................................................. 252

Table 15.6 Permissible SCL Rise Time (tsr) Values ............................................................... 253

Table 15.7 I2C Bus Timing (with Maximum Influence of tsr/tsf) ............................................ 254

Section 16 A/D Converter
Table 16.1

Table 16.2 Analog Input Channels and Corresponding ADDR Registers.............................. 260

Table 16.3 A/D Conversion Time (Single Mode)................................................................... 265

Section 17 EEPROM
Table 17.1

Table 17.2 Slave Addresses.................................................................................................... 274

Section 20 Electrical Characteristics
Table 20.1

Table 20.2 DC Characteristics (1) ..........................................................................................293

Table 20.2 DC Characteristics (2) ..........................................................................................297

Table 20.2 DC Characteristics (3) ..........................................................................................298

Table 20.3 AC Characteristics ................................................................................................ 299

2

I

C Bus Interface Pins........................................................................................... 223

Pin Configuration.................................................................................................. 259

Pin Configuration.................................................................................................. 271

Absolute Maximum Ratings ................................................................................. 291

Rev. 5.00, 03/04, page xxvi of xxviii

Table 20.4 I2C Bus Interface Timing...................................................................................... 301

Table 20.5 Serial Interface (SCI3) Timing .............................................................................302

Table 20.6 A/D Converter Characteristics.............................................................................. 303

Table 20.7 Watchdog Timer Characteristics........................................................................... 304

Table 20.8 Flash Memory Characteristics ..............................................................................305

Table 20.9 EEPROM Characteristics...................................................................................... 307

Table 20.10 DC Characteristics (1)...........................................................................................309

Table 20.10 DC Characteristics (2)...........................................................................................314

Table 20.11 AC Characteristics ................................................................................................315

Table 20.12 I2C Bus Interface Timing...................................................................................... 317

Table 20.13 Serial Interface (SCI3) Timing ............................................................................. 318

Table 20.14 A/D Converter Characteristics.............................................................................. 319

Table 20.15 Watchdog Timer Characteristics........................................................................... 320

Appendix A Instruction Set
Table A.1

Instruction Set....................................................................................................... 327

Table A.2 Operation Code Map (1) ....................................................................................... 340

Table A.2 Operation Code Map (2) ....................................................................................... 341

Table A.2 Operation Code Map (3) ....................................................................................... 342

Table A.3 Number of Cycles in Each Instruction.................................................................. 344

Table A.4 Number of Cycles in Each Instruction.................................................................. 345

Table A.5 Combinations of Instructions and Addressing Modes ..........................................354

Rev. 5.00, 03/04, page xxvii of xxviii

Rev. 5.00, 03/04, page xxviii of xxviii

Section 1 Overview

1.1 Features

• High-speed H8/300H central processing unit with an internal 16-bit architecture

 Upward-compatible with H8/300 CPU on an object level

 Sixteen 16-bit general registers

 62 basic instructions

• Various peripheral functions

 Timer A (can be used as a time base for a clock)

 Timer V (8-bit timer)

 Timer W (16-bit timer)

 Watchdog timer

 SCI3 (Asynchronous or clocked synchronous serial communication interface)

2

 I

C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

 10-bit A/D converter

• On-chip memory

Product Classification Model EEPROM ROM RAM

Flash memory version H8/3664N HD64N3664 512 bytes 32 kbytes 2,048 bytes

(F-ZTATTM version) H8/3664F HD64F3664  32 kbytes 2,048 bytes

Mask ROM version H8/3664 HD6433664  32 kbytes 1,024 bytes

H8/3663 HD6433663  24 kbytes 1,024 bytes

H8/3662 HD6433662  16 kbytes 512 bytes

H8/3661 HD6433661  12 kbytes 512 bytes

H8/3660 HD6433660  8 kbytes 512 bytes

• General I/O ports

 I/O pins: 29 I/O pins (H8/3664N has 27 I/O pins), including 8 large current ports (I

mA, @V

= 1.5 V)

OL

 Input-only pins: 8 input pins (also used for analog input)

• EEPROM interface (only for H8/3664N)

2

 I

C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

• Supports various power-down modes

Note: F-ZTAT

TM

is a trademark of Renesas Technology Corp.

= 20

OL

Rev. 5.00, 03/04, page 1 of 388

• Compact package

G

Package Code Body Size Pin Pitch

LQFP-64 FP-64E 10.0

× 10.0 mm 0.5 mm

QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm

LQFP-48 FP-48F 10.0 × 10.0 mm 0.65 mm

LQFP-48 FP-48B 7.0 × 7.0 mm 0.5 mm

SDIP-42 DP-42S 14.0 × 37.3 mm 1.78 mm

Only LQFP-64 (FP-64E) for H8/3664N package

1.2 Internal Block Diagram

VCCVSSVCLRES

P10/TMOW

P11
P12

P14/IRQ0
P15/IRQ1
P16/IRQ2

P17/IRQ3/TRGV

P20/SCK3

P21/RXD
P22/TXD

TEST

NMI

X1

Subclock
generator

Port 1

Port 2

OSC1

System

clock

generator

OSC2

CPU

H8/300H

Data bus (lower)

ROM

Timer W

Timer A

Timer V

2

I

C bus

interface

Data bus (upper)

Address bus

RAM

SCI3

Watchdog

timer

A/D

converter

P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87

P74/TMRIV
P75/TMCIV
P76/TMOV

P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTR
P56/SDA
P57/SCL

PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4

Port B Port 5 Port 7 Port 8

PB5/AN5
PB6/AN6
PB7/AN7

AV

CC

X2

Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTATTM and Mask-ROM Versions

Rev. 5.00, 03/04, page 2 of 388