RENESAS DG 408 DJZ Datasheet

®

DG408, DG409

Data Sheet September 2004

Single 8-Channel/Differential 4-Channel, CMOS Analog Multiplexers

The DG408 Single 8-Channel, and DG409 Differential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular DG508A and DG509A series devices. They each include an array of eight analog switches, a TTL/CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ENABLE input for device selection when several multiplexers are present.

The DG408 and DG409 feature lower signal ON resistance (<100Ω) and faster switch transition time (t

TRANS

< 250ns) compared to the DG508A or DG509A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG408 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±20V.

The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range.

Ordering Information

PART

NUMBER

DG408DJ -40 to 85 16 Ld PDIP E16.3

DG408DJZ (Note) -40 to 85 16 Ld PDIP (Pb-free) E16.3

DG408DY -40 to 85 16 Ld SOIC M16.15

DG408DY-T 16 Ld SOIC Tape and Reel M16.15

DG408DYZ (Note) -40 to 85 16 Ld SOIC (Pb-free) M16.15

DG408DYZ-T (Note)

DG409DJ -40 to 85 16 Ld PDIP E16.3

DG409DJZ (Note) -40 to 85 16 Ld PDIP (Pb-free) E16.3

DG409DY -40 to 85 16 Ld SOIC M16.15

DG409DY-T 16 Ld SOIC Tape and Reel M16.15

DG409DYZ (Note) -40 to 85 16 Ld SOIC (Pb-free) M16.15

DG409DYZ-T (Note)

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

TEMP.

RANGE (°C) PACKAGE

PKG.

DWG. #

16 Ld SOIC Tape and Reel (Pb-free) M16.15

FN3283.7

Features

• ON Resistance (Max, 25°C). . . . . . . . . . . . . . . . . . . 100Ω

• Low Power Consumption (P

) . . . . . . . . . . . . . . .<11mW

D

• Fast Switching Action

-t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <250ns

TRANS ON/OFF(EN)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . <150ns

• Low Charge Injection

• Upgrade from DG508A/DG509A

• TTL, CMOS Compatible

• Single or Split Supply Operation

• Pb-free Available

Applications

• Data Acquisition Systems

• Audio Switching Systems

• Automatic Testers

• Hi-Rel Systems

• Sample and Hold Circuits

• Communication Systems

• Analog Selector Switch

Pinouts

DG408 (PDIP, SOIC)

TOP VIEW

A

1

0

2

EN

3

V-

4

S

1

5

S

2

S

6

3

S

7

4

8

D

DG409 (PDIP, SOIC)

TOP VIEW

1

A

0

2

EN

3

V-

S

4

1A

S

5

2A

S

6

3A

7

S

4A

8

D

A

16

1

A

15

2

14

GND

13

V+ S

12

5

11

S

6

10

S

7

S

9

8

16

A

1

15

GND

14

V+ S

13

1B

S

12

2B

S

11

3B

S

10

4B

D

9

B

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Block Diagrams

DG408 DG409

DG408, DG409

S

1

S

2

S

8

5V

REF

DIGITAL

†

INPUT PROTECTION

DECODER/

DRIVER

LEVEL

SHIFT

†† ††

A0A1A2EN

D

TRUTH TABLE DG408

A

2

A

1

A

EN ON SWITCH

0

XXX0 NONE

0001 1

0011 2

0101 3

0111 4

1001 5

1011 6

1101 7

1111 8

S

1A

S

4A

S

1B

S

4B

5V

REF

DIGITAL

†

INPUT PROTECTION

DECODER/

DRIVER

LEVEL

SHIFT

A0A

1

†††

EN

TRUTH TABLE DG409

A

1

A

0

EN ON SWITCH

XX0 NONE

001 1

011 2

101 3

111 4

NOTES:

1. V

Logic “1” ≥2.4V.

AH

Logic “0” ≤0.8V.

2. V

AL

D

A

D

B

2

DG408, DG409

Pin Descriptions - (DG408)

PIN SYMBOL DESCRIPTION

1A

2 EN Enable Input

3 V- Negative Power Supply Terminal

4S

5S

6S3Source (Input) for Channel 3

7S

8 D Drain (Output)

9S

10 S

11 S

12 S

13 V+ Positive Power Supply Terminal (Substrate)

14 GND Ground Terminal (Logic Common)

15 A

16 A

Logic Decode Input (Bit 0, LSB)

0

Source (Input) for Channel 1

1

Source (Input) for Channel 2

2

Source (Input) for Channel 4

4

Source (Input) for Channel 8

8

Source (Input) for Channel 7

7

Source (Input) for Channel 6

6

Source (Input) for Channel 5

5

Logic Decode Input (Bit 2, MSB)

2

Logic Decode Input (Bit 1)

1

Pin Descriptions - (DG409)

PIN SYMBOL DESCRIPTION

1A

2 EN Enable Input

3 V- Negative Power Supply Terminal

4S

5S

6S3ASource (Input) for Channel 3a

7S

8D

9DBDrain b (Output b)

10 S

11 S

12 S

13 S

14 V+ Positive Power Supply Terminal

15 GND Ground Terminal (Logic Common)

16 A

Logic Decode Input (Bit 0, LSB)

0

Source (Input) for Channel 1a

1A

Source (Input) for Channel 2a

2A

Source (Input) for Channel 4a

4A

Drain a (Output a)

A

Source (Input) for Channel 4b

4B

Source (Input) for Channel 3b

3B

Source (Input) for Channel 2b

2B

Source (Input) for Channel 1b

1B

Logic Decode Input (Bit 1, MSB)

1

3

DG408, DG409

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V

Digital Inputs, V

, VD (Note 3). . . . . .(V-) -2V to (V+) + 2V or 20mA,

S

Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA

Thermal Resistance (Typical, Note 4) θ

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . -65°C to 125°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. Signals on S is measured with the component mounted on an evaluation PC board in free air.

4. θ

JA

, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.

X

(°C/W)

JA

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V

PARAMETER TEST CONDITIONS TEMP (°C)

= 0.8V, VAH = 2.4V, Unless Otherwise Specified

AL

(NOTE 5)

MIN

(NOTE 6)

TYP

(NOTE 5)

MAX UNITS

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

Break-Before-Make Interval, t

Enable Turn-ON Time, t

ON(EN)

OPEN

(See Figure 1) Full - 160 250 ns

(See Figure 3) 25 10 - - ns

(See Figure 2) 25 - 115 150 ns

Full - - 225 ns

Enable Turn-OFF Time, t

OFF(EN)

Charge Injection, Q C

OFF Isolation V

Logic Input Capacitance, C

Source OFF Capacitance, C

Drain OFF Capacitance, C

IN

S(OFF)

D(OFF)

DG408 25 - 26 - pF

(See Figure 2) Full - 105 150 ns

= 10nF, VS = 0V 25 - 20 - pC

L

= 0V, RL = 1kΩ,

EN

f = 100kHz (Note 9)

25 - -75 - dB

f = 1MHz 25 - 8 - pF

VEN = 0V, VS = 0V,

25 - 3 - pF

f = 1MHz

VEN = 0V, VD = 0V, f = 1MHz

DG409 25 - 14 - pF

Drain ON Capacitance, C

D(ON)

DG408 25 - 37 - pF

VEN = 3V, VD = 0V, f = 1MHz, V

= 0V or 3V

A

DG409 25 - 25 - pF

DIGITAL INPUT CHARACTERISTICS

Logic Input Current, Input Voltage High, I

Logic Input Current, Input Voltage Low, I

AH

AL

VA = 2.4V, 15V Full -10 - 10 µA

VEN = 0V, 2.4V, V

= 0V

A

Full -10 - 10 µA

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Drain-Source ON Resistance, r

DS(ON)

r

Matching Between Channels,

DS(ON)

∆r

DS(ON)

Source OFF Leakage Current, I

VD = ±10V, IS = -10mA (Note 7)

VD = 10V, -10V (Note 8) 25 - - 15 Ω

S(OFF)VEN

V

D

= 0V, VS = ±10V,

= +10V

Full -15 - 15 V

25 - 40 100 Ω

Full - - 125 Ω

25 -0.5 - 0.5 nA

Full -5 - 5 nA

4

DG408, DG409

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V

PARAMETER TEST CONDITIONS TEMP (°C)

Drain OFF Leakage Current, I

D(OFF)

DG408 25 -1 - 1 nA

VEN = 0V, VD = ±10V, V

= +10V

S

= 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued)

AL

(NOTE 5)

MIN

(NOTE 6)

TYP

(NOTE 5)

MAX UNITS

Full -20 - 20 nA

DG409 25 -1 - 1 nA

Full -10 - 10 nA

Drain ON Leakage Current, I

D(ON)

VS = VD = ±10V (Note 7)

DG408 25 -1 - 1 nA

Full -20 - 20 nA

DG409 25 -1 - 1 nA

Full -10 - 10 nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V

= 0V, VA = 0V (Standby) Full - 10 75 µA

EN

Negative Supply Current, I- Full -75 1 - µA

Positive Supply Current, I+ V

= 2.4V, VA = 0V

EN

(Enabled)

25 - 0.2 0.5 mA

Full - - 2 mA

Negative Supply Current, I- Full -500 - - µA

Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, V

Unless Otherwise Specified

TEST

PARAMETER

CONDITION TEMP (°C)

= 0.8V, VAH = 2.4V,

AL

(NOTE 5)

MIN

(NOTE 6)

TYP

(NOTE 5)

MAX UNITS

DYNAMIC CHARACTERISTICS

Switching Time of Multiplexer, t

Enable Turn-ON Time, t

Enable Turn-OFF Time, t

TRANSVS1

ON(EN)

OFF(EN)

Charge Injection, Q CL = 10nF, V

= 8V, VS8 = 0V, VIN = 2.4V 25 - 180 - ns

V V

R

INH S1

GEN

= 2.4V, V

= 5V

= 0Ω

INL

GEN

= 0V,

25 - 180 - ns

25 - 120 - ns

25 - 5 - pC

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Drain-Source ON-Resistance, r

DS(ON)

VD = 3V, 10V, IS = -1mA (Note 7)

Full 0 - 12 V

25 - 90 - Ω

NOTES:

5. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested.

7. Sequence each switch ON.

8. ∆r

DS(ON)

= r

DS(ON)

(Max) - r

DS(ON)

(Min).

9. Worst case isolation occurs on channel 4 due to proximity to the drain pin.

5

Test Circuits and Waveforms

+15V

+2.4V

DG408, DG409

+15V

+2.4V

LOGIC INPUT

S1A - S

0 1

GND

DG409

-15V

V+

S

4A, DA

S

D

V-

1B

4B

±10V

±

10V

B

EN

A

0 1 2

DG408

GND

V+

S2 - S

V-

-15V

±10V

S

1

7

±

S

10V

8

D

SWITCH OUTPUT

35pF300Ω50Ω

LOGIC

V

O

INPUT

EN

A

FIGURE 1A. DG408 TEST CIRCUIT FIGURE 1B. DG409 TEST CIRCUIT

t

< 20ns

r

< 20ns

t

LOGIC

INPUT

SWITCH

OUTPUT

V

3V

0V

S1ON

V

S1

0V

O

V

S8

t

TRANS

50%

0.8 V

S8ON

50%

S8

f

0.8 V

t

S1

TRANS

FIGURE 1C. MEASUREMENT POINTS

FIGURE 1. TRANSITION TIME

SWITCH OUTPUT

V

35pF300Ω50Ω

O

LOGIC INPUT

+15V

DG408

GND

V+

S2 - S

V-

S

1

-5V

8

D

SWITCH OUTPUT

35pF300Ω50Ω

LOGIC

V

O

INPUT

V

IN

A

EN

A

0

A

1

A

V

IN

2

EN

-15V

0

DG409

1

S1A - S

S

2B - S4B, DA

GND

+15V

V+

V-

-15V

S

1B

4A

D

B

FIGURE 2A. DG408 TEST CIRCUIT FIGURE 2B. DG409 TEST CIRCUIT

t

< 20ns

r

< 20ns

t

LOGIC

INPUT

V

SWITCH

OUTPUT

V

3V

0V

IN

0V

O

V

O

t

ON(EN)

50%

0.9 V

O

f

t

OFF(EN)

FIGURE 2C. MEASUREMENT POINTS

FIGURE 2. ENABLE SWITCHING TIMES

-5V

SWITCH OUTPUT

V

35pF300Ω50Ω

o

6

Test Circuits and Waveforms (Continued)

DG408, DG409

LOGIC INPUT

V

GEN

+2.4V

FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS

R

GEN

CHANNEL

SELECT

LOGIC INPUT

ALL S AND D

EN

A

DG408

0

DG409

A

1

A

2

GND

S

A A A

EN

+15V

V+

V-

-15V

X 0

1 2

D, D

GND

A

B

+15V

V+

V-

-15V

INPUT

V

3V

0V

V

S

O

0V

+5V (VS)

SWITCH OUTPUT

35pF300Ω50Ω

LOGIC

SWITCH

V

O

OUTPUT

FIGURE 3. BREAK-BEFORE-MAKE INTERVAL

3V

LOGIC

INPUT

0V

D

C

L

10nF

V

O

SWITCH

OUTPUT

80%

t

OPEN

ON

IS THE MEASURED VOLTAGE DUE

∆V

O

TO CHARGE TRANSFER ERROR, Q

x ∆V

Q = C

L

O

80%

OFF

< 20ns

t

r

t

< 20ns

f

∆V

O

SIGNAL

GENERATOR

ANALYZER

FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS

FIGURE 4. CHARGE INJECTION

+15V

0V

V

IN

S

EN

X

| |

S

8

A

2

A

1

A

0

GND

OFF ISOLATION 20 Log

V+

V

-15V

-

V

-----------------=

D

OUT V

IN

1kΩ

V

O

1kΩ

SIGNAL

GENERATOR

ANALYZER

IN

CROSSTALK 20 Log

5V

S

1

EN

GND

V+

V

D

-

S

X

| |

S

8

A

2

A

1

A

0

-15V

V

OUT

-----------------= V

IN

FIGURE 5. OFF ISOLATION FIGURE 6. CROSSTALK

1kΩ

V

O

7

Test Circuits and Waveforms (Continued)

+15V

5V

V

IN

S

1

EN

V+

D

SIGNAL

GENERATOR

A

2

A

1

A

0

GND

V

-

R

L

-15V

ANALYZER

V

INSERTION LOSS 20 Log

FIGURE 7. INSERTION LOSS FIGURE 8. SOURCE/DRAIN CAPACITANCES

-----------------= V

OUT

IN

Typical Applications

DG408, DG409

V

O

CHANNEL

SELECT

3V OR 0V

EN

A

2

A

1

A

0

GND

+15V

V+

V

-15V

S

1

| |

S

8

D

IMPEDANCE

ANALYZER

-

Overvoltage Protection

A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 9). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal V+ or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference V+ - (V-) doesn’t exceed 44V. The addition of these diodes will reduce the analog signal range to 1V below V+ and 1V above V-, but it preserves the low channel resistance and low leakage characteristics.

Typical application information is for Design Aid Only, not guaranteed and not subject to production testing.

V+

1N4148

S

X

V

-

DG408

1N4148

V

G

D

FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING

DIODES

8

Typical Performance Curves

3.5

DG408, DG409

75

3.0

V+ = +15V V- = -15V

2.0

(pA)

IN

I

1.0

0.5pA

0.0

-1.0 0 5 10 15

VIN (V)

FIGURE 10. INPUT LOGIC CURRENT vs LOGIC INPUT

VO LTAGE

80

V+ = +15V V- = - 15 V

(pF)

S, D

C

60

40

C

D(ON)

C

D(OFF)

C

D(ON)

50

V

C

A

D(OFF)

S(OFF)

(V)

(pF)

S, D

C

25

0

04812

FIGURE 11. SOURCE/DRAIN CAPACITANCE vs ANALOG

VOLTAGE (SINGLE 12V SUPPLY)

V

= ±15V

SUPPLY

= 0V

V

0

-200

(pA)

IN

I

-400

IN

20

0

-15 0 15

C

S(OFF)

V

(V)

A

FIGURE 12. SOURCE/DRAIN CAPACITANCE vs ANALOG

VO LTAGE

60

DG408 I

40

20

0

(pA)

D

I

-20

-40

-60 0 24681012

DG409 I

DG408 I

D(OFF) D(OFF)

D(ON) D(ON)

V

(V)

D

VS = 0V FOR I VS = VD FOR I

D(OFF) D(ON)

FIGURE 14. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN

VOLTAGE (SINGLE 12V SUPPLY)

-600

-800

-55 5 45 85 125 TEMPERATURE (°C)

FIGURE 13. LOGIC INPUT CURRENT vs TEMPERATURE

100

V+ = 15V V- = -15V

60

V

= -VD FOR I

S

VD = V

20

-20

(pA)

D

I

-60

-100

-140

-15 0 15

S(OPEN)

D(OFF)

FOR I

D(ON)

V

, VD (V)

S

DG409 I

DG408 I

D(OFF) D(ON)

D(ON)

, I

D(OFF)

FIGURE 15. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN

VOLTAGE

9

Typical Performance Curves (Continued)

20

2.0

15

10

(pA)

S(OFF)

I

-5

5

0

V+ = +15V V- = -15V

V+ = +12V V- = 0 V

DG408, DG409

(V)

IN

V

1.5

1.0

0.5

-10

-15 0 15

VS (V)

FIGURE 16. SOURCE LEAKAGE CURRENT vs SOURCE

VO LTAGE

5

10

V

= ±15V

4

10

3

10

2

10

-(I-) (µA)

10

1

0.1

SUPPLY

EN = 2.4V

EN = 0V

100 1K 10K 100K 1M 10M

SWITCHING FREQUENCY (Hz)

FIGURE 18. NEGATIVE SUPPLY CURRENT vs SWITCHING

FREQUENCY

0.0 4 8 12 16 20

V

(±V)

SUPPLY

FIGURE 17. INPUT SWITCHING THRESHOLD vs SUPPLY

VOLTAGE

4

10

V

= ±15V

SUPPLY

3

10

2

10

I+ (mA)

1

0.1

0.01 100 1K 10K 100K 1M 10M

EN = 2.4V

EN = 0V

SWITCHING FREQUENCY (Hz)

FIGURE 19. POSITIVE SUPPLY CURRENT vs SWITCHING

FREQUENCY

5

10

4

10

3

10

2

10

I+, I- (nA)

1

0.1

0.01

-55 5 45 85 125

FIGURE 20. I

I+

-(I-)

TEMPERATURE (°C)

SUPPLY

vs TEMPERATURE FIGURE 21. NEGATIVE SUPPLY CURRENT vs TEMPERATURE

V

SUPPLY

10

= ±15V

0

-200

I- (nA)

-400

V+ = 15V

-600

-800

-55 5 125

V- = -15V

= 0V

V

IN

V

= 0V

EN

TEMPERATURE (°C)

45 85

DG408, DG409

Typical Performance Curves (Continued)

20

15

I+ (µA)

10

5

0

-55 5 125

TEMPERATURE (°C)

45 85

FIGURE 22. POSITIVE SUPPLY CURRENT vs TEMPERATURE

(DG408)

V+ = 15V V- = -15V

= 0V

V

IN

V

= 0V

EN

90

CL = 10,000pF

80

V

= 5V

IN

70

60

50

40

Q (pC)

30

20

10

0

-10

-15 -10 -5 0 5 10

P-P

V+ = 15V V- = -15V

V+ = 12V V- = 0V

VS (V)

FIGURE 23. CHARGE INJECTION vs ANALOG VOLTAGE

15

120

100

±5V

80

(Ω)

60

DS(ON)

r

40

±15V

20

±20V

0

-20 -16 -12 -8 -4 0 4 8 12 16 20

FIGURE 24. r

80

70

60

50

(Ω)

40

DS(ON)

r

30

20

10

0

-15 0 15

0°C

-40°C

-55°C

VD (V)

vs VD AND SUPPLY FIGURE 25. r

DS(ON)

V+ = 15V V- = -1 5V

VS (V)

±8V

±10V

125°C

85°C

25°C

±12V

160

140

120

100

(Ω)

80

DS(ON)

r

60

40

20

130

110

90

(Ω)

70

DS(ON)

r

50

30

10

V- = 0V

0

04 812162022

0°C

-40°C

-55°C

0812

V+ = 7.5V

10V

12V

VD (V)

vs VD (SINGLE SUPPLY)

DS(ON)

4

VS (V)

125°C

85°C

25°C

15V

20V

22V

V+ = 12V

V- = 0V

FIGURE 26. r

vs VS AND TEMPERATURE FIGURE 27. r

DS(ON)

11

vs VS AND TEMPERATURE

DS(ON)

(SINGLE SUPPLY)

Typical Performance Curves (Continued)

DG408, DG409

-150

V+ = +15V

-130

-110

-90

(dB)

-70

-50

-30 100 1K 10K 100K 1M 10M 100M

OFF ISOLATION

CROSSTALK

FREQUENCY (Hz)

V- = -1 5V

= 1kΩ

R

L

275

250

225

200

(ns) t

175

150

125

100

89101112131415

V

SUPPLY

t

TRANS

t

ON(EN)

(V)

t

OFF(EN)

FIGURE 28. OFF ISOLATION AND CROSSTALK vs FREQUENCY FIGURE 29. SWITCHING TIME vs SINGLE SUPPLY

200

175

150

t

TRANS

190

170

150

t

TRANS

t

ON(EN)

t (ns)

125

t

OFF(EN)

100

t

SUPPLY

ON(EN)

(±V)

75

10 12 14 16 18 20 22

V

t (ns)

130

110

90

2345

FIGURE 30. SWITCHING TIME vs BIPOLAR SUPPLY FIGURE 31. SWITCHING TIME vs V

180

t

ON(EN)

TRANS

V

t

OFF(EN)

(V)

IN

(BIPOLAR SUPPLY) FIGURE 33. INSERTION LOSS vs FREQUENCY

IN

160

140

t (ns)

120

100

80

234 5

FIGURE 32. SWITCHING TIME vs V

1

0

-1

-2

-3

LOSS (dB)

-4

-5

-6

V+ = +15V V- = -15V REF. 1V

RMS

10

2

10

10310410

FREQUENCY (Hz)

t

OFF(EN)

(V)

V

IN

(SINGLE SUPPLY)

IN

RL = 1kΩ

RL = 50Ω

5

10610710

8

12

Die Characteristics

DG408, DG409

DIE DIMENSIONS:

1800µm x 3320µm x 485µm

METALLIZATION:

Type: SiAl Thickness: 12k

Å ±1kÅ

Metallization Mask Layout

V- (3)

PAS SIVATION:

Type: Nitride Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

4

9.1 x 10

DG408

A

EN (2) (1) (16) (15) (14)

0

A

1

A/cm

A

2

GND

2

NC

(13) V+

(12) S

(11) S

NC

5

6

(4)

S

1

(5)

S

2

(6)

S

3

S

(7)

4

(8)

D

(9) S

8

(10)

S

7

13

Die Characteristics

DG408, DG409

DIE DIMENSIONS:

1800µm x 3320µm x 485µm

METALLIZATION:

Type: SiAl Thickness: 12k

Å ±1kÅ

Metallization Mask Layout

V- (3)

PAS SIVATION:

Type: Nitride Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

4

9.1 x 10

DG409

A

EN

(2) (1) (16) NC (15)

0

A

1

A/cm

GND

2

NC

(14) V+

S1A (4)

(5)

S

2A

(6)

S

3A

S

(7)

4A

(8) D

(13) S

1B

(12) S

2B

(11) S

3B

(9)

A

D

B

(10) S

4B

14

Dual-In-Line Plastic Packages (PDIP)

DG408, DG409

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-AD

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

e

A

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

B

e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A-0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 -5

E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N16 169

NOTESMIN MAX MIN MAX

Rev. 0 12/93

15

DG408, DG409

Small Outline Plastic Packages (SOIC)

N

INDEX AREA

123

-AD

e

B

0.25(0.010) C AMB

E

-B-

SEATING PLANE

A

-C-

S

M

0.25(0.010) B

H

α

µ

A1

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per AN SI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M

L

h x 45

M

o

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.053 0.069 1.35 1.75 -

A1 0.004 0.010 0.10 0.25 -

B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.228 0.244 5.80 6.20 -

h 0.010 0.020 0.25 0.50 5

C

L 0.016 0.050 0.40 1.27 6

N16 167

o

α

0

o

8

o

0

o

8

Rev. 1 02/02

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

16

RENESAS DG 408 DJZ Datasheet [it]