Page 1
R1LP0408D Series
4Mb Advanced LPSRAM (512-kword × 8-bit)
R10DS0104EJ0200
Rev.2.00
2012.5.30
Description
The R1LP0408D Series is a family of 4-Mbit static RAMs organized 512-kword × 8-bit, fabricated by Renesas’s
high-performance CMOS and TFT technologies. The R1LP0408D Series has realized higher density, higher
performance and low power consumption. The R1LP0408D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP and 32-pin TSOP.
Features
• Single 5V supply: 4.5V to 5.5V
• Access time: 55/70ns (max)
• Power dissipation:
── Standby: 4µW (typ)
• Equal access and cycle times
• Common data input and output
── Three state output
• Directly TTL compatible
── All inputs and outputs
• Battery backup operation
Part Name Information
Part Name
R1LP0408DSP-5SR#B* 0 ~ +70°C
R1LP0408DSP-5SI#B*
R1LP0408DSP-7SR#B* 0 ~ +70°C
R1LP0408DSP-7SI#B*
R1LP0408DSP-5SR#S* 0 ~ +70°C
R1LP0408DSP-5SI#S*
R1LP0408DSP-7SR#S* 0 ~ +70°C
R1LP0408DSP-7SI#S*
R1LP0408DSB-5SR#B* 0 ~ +70°C
R1LP0408DSB-5SI#B*
R1LP0408DSB-7SR#B* 0 ~ +70°C
R1LP0408DSB-7SI#B*
R1LP0408DSB-5SR#S* 0 ~ +70°C
R1LP0408DSB-5SI#S*
R1LP0408DSB-7SR#S* 0 ~ +70°C
R1LP0408DSB-7SI#S*
Access
time
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
Temperature
Range
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
-40 ~ +85°C
Package
525-mil 32-pin
plastic SOP
PRSP0032DF-A
(032P2S-A)
400-mil 32-pin
plastic TSOP(II)
PTSB0032DC-A
(032PTY-A)
Shipping
Container
Tube
Embossed
tape
Tray
Embossed
tape
Quantity
Max. 25pcs/Tube
Max. 225pcs/Inner Bag
Max. 900pcs/Inner Box
1000pcs/Reel
Max. 117pcs/Tray
Max. 936pcs/Inner Box
1000pcs/Reel
R10DS0104EJ0200 Rev.2.00 Page 1 of 1
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R1LP0408D Series
V
Pin Arrangement
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
32-pin TSOP
9
10
11
12
13
14
15
16
32-pin SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
cc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
Pin Description
Pin name Function
Vcc Power supply
Vss Ground
A0 to A18 Address input
I/O0 to I/O7 Data input/output
CS# Chip select
WE# Write enable
OE# Output enable
R10DS0104EJ0200 Rev.2.00 Page 2 of 11
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R1LP0408D Series
Block Diagram
LSB
LSB
A11
A11
A9
A9
A8
A8
A13
A13
A17
A17
A15
A15
A18
A18
A16
A16
A14
A14
A12
A12
A7
A7
MSB
MSB
I/O0
I/O0
I/O7
I/O7
CS#
CS#
WE#
WE#
OE#
OE#
Row
Row
Decoder
Decoder
Input
Input
Data
Data
Control
Control
Timing Pulse Generator
Timing Pulse Generator
Read/Write Control
Read/Write Control
・
・
・
・
・
・
・
・
・
・
・
・
・
・
LSB
LSB
Memory Matrix
Memory Matrix
2,048 x 2,048
2,048 x 2,048
Column I/O
Column I/O
Column Decoder
Column Decoder
・
・
・
・
A3
A3
Vcc
Vcc
Vss
Vss
・
・
・
・
MSB
MSB
A6A2A1A0A10A4A5
A6A2A1A0A10A4A5
R10DS0104EJ0200 Rev.2.00 Page 3 of 11
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R1LP0408D Series
Operation Table
WE# CS# OE#
× H × Not selected ISB, I
H L H Output disable Icc High-Z ─
H L L
L L H
L L L Write Icc Din Write cycle (2)
Note 1. H: VIH L:VIL ×: VIH or V
Mode Vcc current
High-Z ─
SB1
Read Icc
Write Icc
IL
I/O0 to I/O7 Ref. cycle
Dout Read cycle
Din Write cycle (1)
Absolute Maximum Ratings
Parameter Symbol Value unit
Power supply voltage relative to Vss Vcc -0.5 to +7.0 V
Terminal voltage on any pin relative to Vss VT -0.5*1 to Vcc+0.3*2 V
Power dissipation PT 0.7 W
Operation temperature Topr*3
Storage temperature range Tstg -65 to 150 °C
Storage temperature range under bias Tbias*3
Note 1. -3.0V for pulse ≤ 30ns (full width at half maximum)
2. Maximum voltage is +7.0V.
3. Ambient temperature range depends on R/I-version. Please see table on page 1.
R Ver. 0 to +70
I Ver. -40 to +85
R Ver. 0 to +70
I Ver. -40 to +85
°C
°C
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R1LP0408D Series
DC Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Note
Supply voltage
Vcc 4.5 5.0 5.5 V
Vss 0 0 0 V
Input high voltage VIH 2.2 ─ Vcc+0.3 V
Input low voltage VIL -0.3 ─ 0.8 V 1
Ambient temperature range
R Ver. 0 ─ +70 °C 2
I Ver.
Ta
-40 ─ +85 °C 2
Note 1. -3.0V for pulse ≤ 30ns (full width at half maximum)
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
Input leakage current
Output leakage current
Operating current
Average operating current
Standby current
Standby current
| ─ ─ 1 μA
| I
LI
| I
| ─ ─ 1 μA
LO
Icc ─ 5
I
─ 15*1 25 mA
CC1
I
─ 3
CC2
*1
10 mA
*1
5 mA
ISB ─ 0.1*1 0.5 mA
─ 0.8*1 2.5 μA ~+25°C
Vin = Vss to Vcc
CS# =VIH or OE# =VIH,
I/O =Vss to Vcc
V
CS# =V
Others = V
,
IL
, II/O = 0mA
IH/VIL
Min. cycle, duty =100%, II/O = 0mA
CS# =VIL, Others = VIH/VIL
Cycle =1μs, duty =100%, II/O = 0mA
CS# ≤ 0.2V,
≥ Vcc-0.2V, V
V
IH
≤ 0.2V
IL
CS# =VIH,
Others = Vss to Vcc
*2
3 μA ~+40°C
Vin = Vss to Vcc,
CS# ≥ Vcc-0.2V
I
SB1
─ 1
─ ─ 8 μA ~+70°C
─ ─ 10 μA ~+85°C
Output high voltage
Output low voltage
V
V
V
OH
OH2
OL
2.4 ─ ─ V IOH = -1mA
Vcc-0.5 ─ ─ V IOH = -0.1mA
─ ─ 0.4 V IOL = 2.1mA
Note 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=40ºC), and not 100% tested.
Capacitance
(Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2)
Parameter Symbol Min. Typ. Max. Unit Test conditions Note
Input capacitance C in ─ ─ 8 pF Vin =0V 1
Input / output capacitance C
Note 1. This parameter is sampled and not 100% tested.
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
─ ─ 10 pF VI/O =0V 1
I/O
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R1LP0408D Series
AC Characteristics
Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
• Input pulse levels: VIL = 0.4V, VIH = 2.4V
• Input rise and fall time: 5ns
• Input and output timing reference level: 1.5V
• Output load: See figures (Including scope and jig)
1.5V
= 500 ohm
R
L
I/O
CL = 50 pF ( -5SI, -5SR)
C
= 100 pF ( -7SI, -7SR)
L
Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1.
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R1LP0408D Series
Read Cycle
Parameter Symbol
R1LP0408DS*-5S* R1LP0408DS*-7S*
Min. Max. Min. Max.
Unit Note
Read cycle time tRC 55 ─ 70 ─ ns
Address access time tAA ─ 55 ─ 70 ns
Chip select access time t
─ 55 ─ 70 ns
ACS
Output enable to output valid tOE ─ 25 ─ 35 ns
Chip select to output in low-Z t
Output enable to output in low-Z t
Chip deselect to output in high-Z t
Output disable to output in high-Z t
10 ─ 10 ─ ns 2
CLZ
5 ─ 5 ─ ns 2
OLZ
0 20 0 25 ns 1,2
CHZ
0 20 0 25 ns 1,2
OHZ
Output hold from address change tOH 10 ─ 10 ─ ns
Write Cycle
Parameter Symbol
Write cycle time tWC 55 ─ 70 ─ ns
Chip select to end of write tCW 50 ─ 60 ─ ns 4
Address setup time tAS 0 ─ 0 ─ ns 5
Address valid to end of write tAW 50 ─ 60 ─ ns
Write pulse width tWP 40 ─ 50 ─ ns 3,12
Write recovery time tWR 0 ─ 0 ─ ns 6
Write to output in high-Z t
WHZ
Data to write time overlap tDW 25 ─ 30 ─ ns
Data hold from write time tDH 0 ─ 0 ─ ns
Output enable from end of write tOW 5 ─ 5 ─ ns 2
Output disable to output in high-Z t
OHZ
Note 1. t
CHZ
OHZ
and t
are defined as the time at which the outputs achieve the open circuit conditions and are not
WHZ
, t
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
) of a low CS# and a low WE#.
WP
A write begins at the later transition of CS# going low or WE# going low.
A write ends at the earlier transition of CS# going high or WE# going high.
is measured from the beginning of write to the end of write.
t
WP
4. tCW is measured from CS# going low to end of write.
5. t
6. t
is measured the address valid to the beginning of write.
AS
is measured from the earlier of WE# or CS# going high to the end of write cycle.
WR
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the
outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the
output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite
phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, t
contention.
tWP ≥ tDW min + t
WHZ
max
R1LP0408DS*-5S* R1LP0408DS*-7S*
Min. Max. Min. Max.
Unit Note
0 20 0 25 ns 1,2,7
0 20 0 25 ns 1,2,7
must satisfy the following equation to avoid a problem of data bus
WP
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R1LP0408D Series
Timing Waveforms
Read Cycle (WE# = VIH )
Address
CS#
OE#
Dout
High impedance
Valid address
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
t
RC
t
CHZ
t
OHZ
Valid Data
tOH
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R1LP0408D Series
Write Cycle (1) (OE# CLOCK)
Address
OE#
CS#
WE#
Dout
t
WC
Valid address
t
AW
tWR
tCW
*8
t
AS
t
WP
t
OHZ
High impedance
Din
t
DW
tDH
Valid Data
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R1LP0408D Series
V
Write Cycle (2) (OE# Low Fixed)
Address
CS#
WE#
tAS
Dout
Din
alid address
*8
t
t
WHZ
AW
t
WC
tCW
t
WP
t
WR
tOH
tOW
*9 *10
High impedance
t
DW
t
DH
*11
Valid Data
R10DS0104EJ0200 Rev.2.00 Page 10 of 11
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Page 11
R1LP0408D Series
V
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*3
VCC for data retention VDR 2.0 ─ 5.5 V
Vin ≥ 0V,
CS# ≥ Vcc-0.2V
─ 0.8
─ 1*2 3 μA ~+40°C
Data retention current I
Chip deselect time to data retention t
Operation recovery time tR 5 ─ ─ ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
3. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If data retention mode, Vin levels
(address, WE#, OE#, I/O) can be in the high impedance state.
CCDR
─ ─ 8 μA ~+70°C
─ ─ 10 μA ~+85°C
0 ─ ─ ns
CDR
*1
2.5 μA ~+25°C
Vcc=3.0V, Vin ≥ 0V,
CS# ≥ Vcc-0.2V
See retention waveform.
Low Vcc Data Retention Timing Waveforms
CS# Controlled
Vcc
t
t
CDR
2.2V 2.2V
4.5V 4.5V
DR
R
CS# ≥ Vcc - 0.2V
CS#
R10DS0104EJ0200 Rev.2.00 Page 11 of 11
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Page 12
Revision History R1LP0408D Series Data Sheet
Description
Rev. Date
1.00 2012.4.13 ─ First Edition issued (SOP package)
2.00 2012.5.30 P.1 Add TSOP package to Part Name Information
Page Summary
All trademarks and registered trademarks are the property of their respective owners.
Page 13
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