Renesas 5P49V6965 Datasheet
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/S CL
V
DDA
V
DDD
V
DDO
0
OUT0 _SEL_I 2CB
V
DDO
1
OUT1
OUT1B
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
V
DDO
4
OUT4
OUT4B
FOD1
FOD2
FOD3
FOD4
PLL
OTP
and
Control
Logic
VersaClock® 6E Programmable
Clock Generator
5P49V6965
Datasheet
Description
The 5P49V6965 is a programmable clock generator intended for
high-performance consumer, networking, industrial, computing,
and data-communications applications. Configurations may be
stored in on-chip One-Time Programmable (OTP) memory or
changed using I
2
C interface. This is Renesas’ sixth generation of
programmable clock technology (VersaClock 6E).
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock
inputs. A glitchless manual switchover function allows one of the
redundant clocks to be selected during normal operation.
Two select pins allow up to four different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for different
operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or system
production margin testing. The device may be configured to use
one of two I
2
C addresses to allow multiple devices to be used in a
system.
Typical Applications
▪ Ethernet switch/router
▪ PCI Express 1.0 / 2.0 / 3.0 / 4.0 Spread Spectrum on
▪ PCI Express 1.0 / 2.0 / 3.0 / 4.0 / 5.0 Spread Spectrum off
▪ Broadcast video/audio timing
▪ Multi-function printer
▪ Processor and FPGA clocking
▪ Any-frequency clock conversion
▪ MSAN/DSLAM/PON
▪ Fiber Channel, SAN
▪ Telecom line cards
▪ Laser distance sensing
Features
▪ Flexible 1.8V, 2.5V, 3.3V power-rails
▪ High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
▪ Four banks of internal OTP memory
• In-system or factory programmable
• 2 select pins accessible with processor GPIOs or
bootstrapping
2
▪ I
C serial programming interface
• 0xD0 or 0xD4 I2C address options allows multiple devices
configured in a same system
▪ Reference LVCMOS output clock
▪ Four universal output pairs individually configurable:
• Differential (LVPECL, LVDS or HCSL)
• 2 single-ended (2 LVCMOS in-phase or 180 degrees out of
phase)
• I/O V
(LVDS and LVCMOS), 2.5V, or 3.3V
▪ Output frequency ranges:
• LVCMOS clock outputs: 1kHz to 200MHz
• LVDS, LVPECL, HCSL differential clock outputs: 1kHz to
350MHz
▪ Redundant clock inputs with manual switchover
▪ Programmable output enable or power-down mode
▪ Available in 4 × 4 mm 24-VFQFPN package
▪ -40° to +85°C industrial temperature operation
s can be mixed and matched, supporting 1.8V
DD
Block Diagram
1©2020 Renesas Electronics Corporation August 20, 2020
5P49V6965 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Jitter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCI Express Jitter Performance and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features and Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device Startup and Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reference Clock and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Manual Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal Crystal Oscillator (XIN/REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmable Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fractional Output Dividers (FOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SD/OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input – Driving the XIN/REF or CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output – Single-ended or Differential Clock Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2©2020 Renesas Electronics Corporation August 20, 2020
Pin Assignments
1
7
4 × 4 mm 24-VFQFPN
19
13
XOUT
XIN/REF
V
DDO
3
CLKIN
OUT3B
OUT2
CLKINB
CLKSEL
OUT3
OUT2B
V
DDO
2
V
DDA
SD/OE
SEL1/SDA
SEL0/SCL
V
DDO
4
OUT4
OUT4B
OUT1B
OUT1
V
DDO
1
V
DDD
V
DDO
0
OUT0_SEL_I2CB
EPAD
2
3
4
5
6
8
9101112
14
15
16
17
18
2021222324
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
5P49V6965 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number Name Type Description
Pull-down
Pull-down
Power
Pull-down
Pull-down
Pull-down
Pull-down
Internal
Internal
Internal
Internal
Internal
Internal
Differential clock input. Weak 100kΩ internal pull-down.
Complementary differential clock input. Weak 100kΩ internal pull-down.
Crystal oscillator interface input, or single-ended LVCMOS clock input. Input voltage needs
to be below 1.2V. Refer to the section Driving XIN/REF with a CMOS Driver.
Analog functions power supply pin. Connect to 1.8V to 3.3V. V
the same voltage applied.
Input clock select. Selects the active input reference source in manual switchover mode.
0 = XIN/REF, XOUT (default).
1 = CLKIN, CLKINB.
See Table 20. Input Clock Select for more details.
Enables/disables the outputs (OE) or powers down the chip (SD).
Configuration select pin, or I
2
C SDA input as selected by OUT0_SEL_I2CB. Weak internal
pull-down resistor.
2
Configuration select pin, or I
C SCL input as selected by OUT0_SEL_I2CB. Weak internal
pull-down resistor.
1 CLKIN Input
2 CLKINB Input
3 XOUT Output Crystal oscillator interface output.
4 XIN/REF Input
5 V
DDA
6 CLKSEL Input
7 SD/OE Input
8 SEL1/SDA Input
9 SEL0/SCL Input
DDA
and V
should have
DDD
3©2020 Renesas Electronics Corporation August 20, 2020
Table 1. Pin Descriptions (Cont.)
Number Name Type Description
5P49V6965 Datasheet
10 V
4 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT4/OUT4B.
DDO
11 OUT4 Output Output clock 4. Refer to the Output Drivers section for more details.
12 OUT4B Output Complementary output clock 4. Refer to the Output Drivers section for more details.
13 OUT3B Output Complementary output clock 3. Refer to the Output Drivers section for more details.
14 OUT3 Output Output clock 3. Refer to the Output Drivers section for more details.
15 V
3 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3/OUT3B.
DDO
16 OUT2B Output Complementary output clock 2. Refer to the Output Drivers section for more details.
17 OUT2 Output Output clock 2. Refer to the Output Drivers section for more details.
18 V
2 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT2/OUT2B.
DDO
19 OUT1B Output Complementary output clock 1. Refer to the Output Drivers section for more details.
20 OUT1 Output Output clock 1. Refer to the Output Drivers section for more details.
21 V
22 V
23 V
1 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1/OUT1B.
DDO
DDD
0 Power
DDO
Power
Digital functions power supply pin. Connect to 1.8 to 3.3V. V
same voltage applied.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage levels
for OUT0.
DDA
and V
should have the
DDD
Latched input/LVCMOS output. At power-up, the voltage at the pin OUT0_SEL_I2CB is
latched by the part and used to select the state of pins 8 and 9. If a weak pull-up (10kΩ) is
24
OUT0_SEL
_I2CB
Input/
Output
Internal
Pull-down
placed on OUT0_SEL_I2CB, pins 8 and 9 will be configured as hardware select pins, SEL1
and SEL0. If a weak pull-down (10kΩ) is placed on OUT0_SEL_I2CB or it is left floating,
pins 8 and 9 will act as the SDA and SCL pins of an I
2
C interface. After power-up, the pin
acts as an LVCMOS reference output.
25 GND GND Connect to ground pad.
4©2020 Renesas Electronics Corporation August 20, 2020
5P49V6965 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the device at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 2. Absolute Maximum Ratings
Item Rating
Supply Voltage, V
DDA
, V
DDD
, V
DDO
3.6V.
XIN/REF Input 1.2V.
CLKIN, CLKINB Input V
, 1.2V voltage swing.
DDO0
I2C Loading Current 10mA.
Storage Temperature, T
STG
-65°C to 150°C.
Junction Temperature 125°C
ESD Human Body Model 2000V.
Thermal Characteristics
Table 3. Thermal Characteristics
Symbol Parameter Value Units
θ
JA
θ
JB
θ
JC
Theta JA. Junction to air thermal impedance (0mps). 42 °C/W
Theta JB. Junction to board thermal impedance (0mps). 2.35 °C/W
Theta JC. Junction to case thermal impedance (0mps). 41.8 °C/W
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol Parameter Minimum Typical Maximum Units
Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V
V
V
V
DDOX
DDD
DDA
T
PU
T
A
C
L
Power supply voltage for supporting 2.5V outputs. 2.375 2.5 2.625 V
Power supply voltage for supporting 3.3V outputs. 3.135 3.3 3.465 V
Power supply voltage for core logic functions. 1.71 3.465 V
Analog power supply voltage. Use filtered analog power supply. 1.71 3.465 V
Power ramp time for all VDDs to reach 90% of VDD. 0.05 50 ms
Operating temperature, ambient. -40 85 °C
Maximum load capacitance (3.3V LVCMOS only). 15 pF
5©2020 Renesas Electronics Corporation August 20, 2020
5P49V6965 Datasheet
Electrical Characteristics
Table 5. Current Consumption
V
, V
DDD
, V
DDA
Symbol Parameter Conditions Minimum Typical Maximum Units
I
DDCORE
I
DDOx
I
DDPD
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C.
DDO0
1
Core Supply Current 100MHz on all outputs, 25MHz REFCLK. 33 42 mA
Output Buffer Supply
Current
LVPECL, 350MHz, 3.3V V
LVPECL, 350MHz, 2.5V V
LVDS, 350MHz, 3.3V V
LVDS, 350MHz, 2.5V V
LVDS, 350MHz, 1.8V V
HCSL, 250MHz, 3.3V V
HCSL, 250MHz, 2.5V V
DDOx2.
DDOx2.
DDOx2.
DDOx 2.
DDOx 2.
LVCMOS, 50MHz, 3.3V, V
LVCMOS, 50MHz, 2.5V, V
LVCMOS, 50MHz, 1.8V, V
LVCMOS, 200MHz, 3.3V V
LVCMOS, 200MHz, 2.5V V
LVCMOS, 200MHz, 1.8V V
DDOx.2.
DDOx.2.
DDOx
DDOx
DDOx
DDOx
DDOx
DDOx
2,3
. 22 27 mA
2,3
. 20 24 mA
2,3
. 17 21 mA
2,3
. 43 56 mA
2,3
. 33 43 mA
2,3
. 24 31 mA
45 58 mA
36 47 mA
26 32 mA
25 30 mA
22 27 mA
39 48 mA
37 46 mA
Power Down Current SD asserted, I2C programming. 10 12 mA
1
I
2
Measured into a 5” 50Ω trace. See Test Loads section for more details.
3
Single CMOS driver active.
DDCORE
= I
DDA
+ I
DDD
.
6©2020 Renesas Electronics Corporation August 20, 2020
5P49V6965 Datasheet
Table 6. AC Timing Characteristics
V
, V
DDA
DDD
, V
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise.
DDO0
Symbol Parameter Conditions Minimum Typical Maximum Units
Input frequency limit (crystal). 8 40 MHz
1
F
IN
Input Frequency
Input frequency limit (CLKIN,CLKINB). 1 350 MHz
Input frequency limit (single-ended over XIN). 1 200 MHz
F
OUT
f
T
VCO
DC
2
Output Frequency
Single-ended clock output limit (LVCMOS),
individual FOD mode.
Differential clock output limit
(LVPECL/LVDS/HCSL), individual FOD mode.
Single-ended clock output limit (LVCMOS),
cascaded FOD mode, output 2–4.
1 200
1 350
MHz
0.001 200
Differential clock output limit
(LVPECL/LVDS/HCSL), cascaded FOD mode,
0.001 350
output 2–4.
VCO Operating Frequency
Range
Measured at V
reference output, V
Measured at V
reference output, V
3
Output Duty Cycle
Measured at V
/2, all outputs except
DD
DD
DD
= 2.5V or 3.3V.
DDOX
/2, all outputs except
= 1.8V
DDOX
/2, reference output OUT0
(5MHz–150.1MHz) with 50% duty cycle input.
Measured at V
/2, reference output OUT0
DD
(150.1MHz–200MHz) with 50% duty cycle
2500 2900 MHz
45 50 55 %
40 50 60 %
40 50 60 %
30 50 70 %
input.
Skew between the same frequencies, with
T
SKEW
Output Skew
outputs using the same driver format and
phase delay set to 0ns.
Measured after all VDDs have risen above
T
STARTUP
4,5
Startup Time
90% of their target value 6.
PLL lock time from shutdown mode. 3 4 ms
1
Practical lower frequency is determined by loop filter settings.
2
A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3
Duty cycle is only guaranteed at maximum slew rate settings.
4
Actual PLL lock time depends on the loop configuration.
5
Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
6
Power-up with temperature calibration enabled; contact Renesas if shorter lock-time is required in system.
7©2020 Renesas Electronics Corporation August 20, 2020
75 ps
30 ms
5P49V6965 Datasheet
Table 7. General Input Characteristics
V
, V
DDA
DDD
, V
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise.
DDO0
Symbol Parameter Conditions Minimum Typical Maximum Units
CLKIN,CLKINB,CLKSEL,SD/OE,SEL1/SD
A, SEL0/SCL.
CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL,
CLKIN, CLKINB, OUT0_SEL_I2CB.
3 7 pF
100 300 kΩ
V
DDD
+ 0.3 V
DDD
DDD
+ 0.3 V
DDO0
T
C
R
V
V
V
V
V
V
R/TF
Input Capacitance
IN
Pull-down Resistor
PD
Input High Voltage CLKSEL, SD/OE. 0.7 x V
IH
Input Low Voltage CLKSEL, SD/OE. GND - 0.3 0.3 x V
IL
Input High Voltage OUT0_SEL_I2CB. 1.7 V
IH
Input Low Voltage OUT0_SEL_I2CB. GND - 0.3 0.4 V
IL
Input High Voltage XIN/REF. 0.8 1.2 V
IH
Input Low Voltage XIN/REF. GND - 0.3 0.4 V
IL
Input Rise/Fall Time CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL. 300 ns
Table 8. CLKIN Electrical Characteristics
V
, V
DDA
DDD
, V
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise.
DDO0
Symbol Parameter Conditions Minimum Typical Maximum Units
V
SWING
Input Amplitude – CLKIN, CLKINB Peak to peak value, single-ended. 200 1200 mV
dv/dt Input Slew Rate – CLKIN, CLKINB Measured differentially. 0.4 8 V/ns
V
DC
I
IL
I
IH
IN
Input Leakage Low Current VIN = GND. -5 5 μA
Input Leakage High Current VIN = 1.7V. 20 μA
Input Duty Cycle
Measurement from differential
waveform.
45 55 %
8©2020 Renesas Electronics Corporation August 20, 2020
5P49V6965 Datasheet
Table 9. Electrical Characteristics – CMOS Outputs
V
, V
DDA
DDD
, V
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise.
DDO0
Symbol Parameter Conditions Minimum Typical Maximum Units
V
OH
V
OL
R
OUT
T
SR
I
OZDD
Output High Voltage
IOH = -15mA (3.3V), -12mA (2.5V). 0.7 x V
= -8mA (1.8V). 0.5 x V
I
OH
DDO
DDO
V
V
DDO
DDO
Output Low Voltage IOL = 15mA (3.3V), 12mA (2.5V), 8mA (1.8V). 0.45 V
Output Driver Impedance CMOS output driver. 17 Ω
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01 1.2 2.3
Slew Rate, SLEW[1:0] = 10 1.3 2.4
Single-ended 3.3V LVCMOS output clock rise and
fall time, 20% to 80% of V
= 3.3V.
V
DDOX
(output load = 5pF)
DDO
1.0 2.2
Slew Rate, SLEW[1:0] = 11 1.7 2.7
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01 0.7 1.4
Slew Rate, SLEW[1:0] = 10 0.6 1.4
Single-ended 2.5V LVCMOS output clock rise and
fall time, 20% to 80% of V
= 2.5V.
V
DDOX
(output load = 5pF)
DDO
0.6 1.3
V/ns
Slew Rate, SLEW[1:0] = 11 1.0 1.7
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01 0.4 0.8
Slew Rate, SLEW[1:0] = 10 0.4 0.9
Single-ended 1.8V LVCMOS output clock rise and
fall time, 20% to 80% of V
= 1.8V.
V
DD
(output load = 5pF)
DDO
0.3 0.7
Slew Rate, SLEW[1:0] = 11 0.7 1.2
Output Leakage Current
(OUT1–4)
Tri-state outputs. 5 μA
Output Leakage Current (OUT0) Tri-state outputs. 30 μA
V
V
Table 10. Electrical Characteristics – LVDS Outputs
V
, V
DDA
DDD
, V
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise.
DDO0
Symbol Parameter Minimum Typical Maximum Units
(+) Differential Output Voltage for the TRUE Binary State 247 454 mV
V
OT
(-) Differential Output Voltage for the FALSE Binary State -454 -247 mV
V
OT
Change in VOT between Complimentary Output States 50 mV
ΔV
OT
Output Common Mode Voltage (Offset Voltage) at 3.3 V ±5%, 2.5V ±5% 1.125 1.25 1.375 V
V
ΔV
I
OS
I
OS
OSD
T
R
T
OS
F
Output Common Mode Voltage (Offset Voltage) at 1.8V ±5% 0.8 0.875 0.96 V
Change in VOS between Complimentary Output States 50 mV
Outputs Short Circuit Current, V
Differential Outputs Short Circuit Current, V
OUT
+ or V
- = 0V or V
OUT
+ = V
OUT
DDO
- 6 12 mA
OUT
9 24 mA
LVDS rise time 20%–80% 300 ps
LVDS fall time 80%–20% 300 ps
9©2020 Renesas Electronics Corporation August 20, 2020
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