Renesas 4514, 4513 User Manual

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER

4500 SERIES

4513/4514

Group

User’s Manual

keep safety first in your circuit designs !

●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.

Notes regarding these materials

●These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

●Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.

●All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.

●Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.

●The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.

●If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.

●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.

Preface

This user’s manual describes the hardware and
instructions of Mitsubishi’s 4513/4514 Group CMOS
4-bit microcomputer.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 4513/4514 Group and should be able to fully
utilize the product. The manual starts with specifications
and ends with application examples.
In this manual, the 4514 Group is mainly described.
The differences from the 4513 Group are described
at the related points.

BEFORE USING THIS USER’S MANUAL

This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.

1. Organization

CHAPTER 1 HARDWARE

This chapter describes features of the microcomputer and operation of each peripheral function.

CHAPTER 2 APPLICATION

This chapter describes usage and application examples of peripheral functions, based mainly on setting
examples of related registers.

CHAPTER 3 APPENDIX

This chapter includes precautions for systems development using the microcomputer, the mask ROM
confirmation forms (mask ROM version), and mark specification forms which are to be submitted when
ordering.
Be sure to refer to this chapter because this chapter also includes necessary information for systems
development.

Note: In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are

described at the related points.

Table of contents

Table of contents

CHAPTER 1 HARDWARE

DESCRIPTION ................................................................................................................................ 1-3

FEATURES ...................................................................................................................................... 1-3

APPLICATION ................................................................................................................................ 1-3

PIN CONFIGURATION ..................................................................................................................1-4

BLOCK DIAGRAM ......................................................................................................................... 1-6

PERFORMANCE OVERVIEW ....................................................................................................... 1-8

PIN DESCRIPTION ........................................................................................................................1-9

MULTIFUNCTION ...................................................................................................................1-10

CONNECTIONS OF UNUSED PINS ................................................................................... 1-10

PORT FUNCTION ..................................................................................................................1-11

DEFINITION OF CLOCK AND CYCLE ............................................................................... 1-11

PORT BLOCK DIAGRAMS ................................................................................................... 1-12

FUNCTION BLOCK OPERATIONS ........................................................................................... 1-17

CPU.......................................................................................................................................... 1-17

PROGRAM MEMOY (ROM) .................................................................................................. 1-20

DATA MEMORY (RAM) ......................................................................................................... 1-21

INTERRUPT FUNCTION .......................................................................................................1-22

EXTERNAL INTERRUPTS .................................................................................................... 1-26

TIMERS ................................................................................................................................... 1-29

WATCHDOG TIMER .............................................................................................................. 1-35

SERIAL I/O.............................................................................................................................. 1-36

A-D CONVERTER .................................................................................................................. 1-41

VOLTAGE COMPARATOR.................................................................................................... 1-47

RESET FUNCTION ................................................................................................................ 1-49

VOLTAGE DROP DETECTION CIRCUIT ........................................................................... 1-52

RAM BACK-UP MODE ..........................................................................................................1-53

CLOCK CONTROL ................................................................................................................. 1-57

ROM ORDERING METHOD .......................................................................................................1-58

LIST OF PRECAUTIONS ............................................................................................................1-59

SYMBOL ........................................................................................................................................ 1-62

LIST OF INSTRUCTION FUNCTION ........................................................................................1-63

INSTRUCTION CODE TABLE.................................................................................................... 1-66

MACHINE INSTRUCTIONS ........................................................................................................ 1-70

CONTROL REGISTERS .............................................................................................................. 1-84

BUILT-IN PROM VERSION ........................................................................................................ 1-88

4513/4514 Group User’s Manual

i

Table of contents

CHAPTER 2 APPLICATION

2.1 I/O pins .................................................................................................................................... 2-2

2.1.1 I/O ports .......................................................................................................................... 2-2

2.1.2 Related registers ............................................................................................................ 2 -4

2.1.3 Port application examples ............................................................................................. 2 -7

2.1.4 Notes on use .................................................................................................................. 2 -9

2.2 Interrupts ............................................................................................................................... 2-11

2.2.1 Interrupt functions ........................................................................................................ 2-11

2.2.2 Related registers .......................................................................................................... 2-13

2.2.3 Interrupt application examples.................................................................................... 2-16

2.2.4 Notes on use ................................................................................................................ 2-25

2.3 Timers ....................................................................................................................................2-26

2.3.1 Timer functions .............................................................................................................2-26

2.3.2 Related registers .......................................................................................................... 2-27

2.3.3 Timer application examples ........................................................................................ 2-30

2.3.4 Notes on use ................................................................................................................ 2-39

2.4 Serial I/O ................................................................................................................................ 2-40

2.4.1 Carrier functions ...........................................................................................................2-40

2.4.2 Related registers .......................................................................................................... 2-41

2.4.3 Operation description ................................................................................................... 2-42

2.4.4 Serial I/O application example ................................................................................... 2-45

2.4.5 Notes on use ................................................................................................................ 2-48

2.5 A-D converter ....................................................................................................................... 2-49

2.5.1 Related registers .......................................................................................................... 2-50

2.5.2 A-D converter application examples .......................................................................... 2-51

2.5.3 Notes on use ................................................................................................................ 2-52

2.6 Voltage comparator ............................................................................................................. 2-54

2.6.1 Voltage comparator function ....................................................................................... 2-54

2.6.2 Related registers .......................................................................................................... 2-54

2.6.3 Notes on use ................................................................................................................ 2-55

2.7 Reset....................................................................................................................................... 2-56

2.7.1 Reset circuit ..................................................................................................................2-56

2.7.2 Internal state at reset ..................................................................................................2-57

2.8 Voltage drop detection circuit.......................................................................................... 2-58

2.9 RAM back-up ........................................................................................................................2-59

2.9.1 RAM back-up mode ..................................................................................................... 2-59

2.9.2 Related register ............................................................................................................ 2-60

2.9.3 Notes on use ................................................................................................................ 2-62

2.10 Oscillation circuit ..............................................................................................................2-63

2.10.1 Oscillation circuit ........................................................................................................ 2-63

2.10.2 Oscillation operation ..................................................................................................2-64

2.10.3 Notes on use .............................................................................................................. 2-64

ii

4513/4514 Group User’s Manual

Table of contents

CHAPTER 3 APPENDIX

3.1 Electrical characteristics ..................................................................................................... 3-2

3.1.1 Absolute maximum ratings ............................................................................................ 3- 2

3.1.2 Recommended operating conditions ............................................................................ 3- 3

3.1.3 Electrical characteristics ................................................................................................ 3 -5

3.1.4 A-D converter recommended operating conditions.................................................... 3-6

3.1.5 Voltage drop detection circuit characteristics............................................................. 3-6

3.1.6 Voltage comparator characteristics .............................................................................. 3- 7

3.1.7 Basic timing diagram ..................................................................................................... 3 -7

3.2 Typical characteristics .........................................................................................................3-8

3.2.1 VDD–IDD characteristics ................................................................................................. 3-8

3.2.2 VOL–IOL characteristics ................................................................................................ 3-11

3.2.3 VOH–IOH characteristics (Port P5) ............................................................................. 3-13

3.2.4 VDD–RPU characteristics (Ports P0, P1) ................................................................... 3-13

3.2.5 A-D converter typical characteristics .........................................................................3-14

3.2.6 Analog input current characteristics pins AIN0–AIN7 ............................................................ 3-17

3.2.7 VDD–VIH/VIL characteristics .........................................................................................3-19

3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit . 3-20

3.3 List of precautions .............................................................................................................. 3-21

3.4 Notes on noise ..................................................................................................................... 3-24

3.4.1 Shortest wiring length .................................................................................................. 3-24

3.4.2 Connection of bypass capacitor across VSS line and VDD line ............................ 3-26

3.4.3 Wiring to analog input pins ........................................................................................3-27

3.4.4 Oscillator concerns....................................................................................................... 3-27

3.4.5 Setup for I/O ports ....................................................................................................... 3-28

3.4.6 Providing of watchdog timer function by software .................................................. 3-28

3.5 Mask ROM order confirmation form ............................................................................... 3-30

3.6 Mark specification form .....................................................................................................3-36

3.7 Package outline ...................................................................................................................3-39

4513/4514 Group User’s Manual

iii

List of figures

CHAPTER 1 HARDWARE

PIN CONFIGURATION (TOP VIEW) 4513 Group..................................................................... 1- 4

PIN CONFIGURATION (TOP VIEW) 4514 Group .....................................................................1-5

BLOCK DIAGRAM (4513 Group) .................................................................................................1-6

BLOCK DIAGRAM (4514 Group) .................................................................................................1-7

PORT BLOCK DIAGRAMS .........................................................................................................1-12

External interrupt circuit structure ..............................................................................................1-16

Fig. 1 AMC instruction execution example ...............................................................................1-17

Fig. 2 RAR instruction execution example ............................................................................... 1-17

Fig. 3 Registers A, B and register E ........................................................................................1-17

Fig. 4 TABP p instruction execution example .......................................................................... 1-17

Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-18

Fig. 6 Example of operation at subroutine call .......................................................................1-18

Fig. 7 Program counter (PC) structure ..................................................................................... 1-19

Fig. 8 Data pointer (DP) structure .............................................................................................1-19

Fig. 9 SD instruction execution example.................................................................................. 1-19

Fig. 10 ROM map of M34514M8/E8 .........................................................................................1-20

Fig. 11 Page 1 (addresses 008016 to 00FF16) st ruct ure ....................................................... 1-20

Fig. 12 RAM map ......................................................................................................................... 1-21

Fig. 13 Program example of interrupt processing ................................................................... 1-23

Fig. 14 Internal state when interrupt occurs ............................................................................ 1-23

Fig. 15 Interrupt system diagram ............................................................................................... 1-23

Fig. 16 Interrupt sequence.......................................................................................................... 1-25

Fig. 17 External interrupt circuit structure ................................................................................ 1-26

Fig. 18 Auto-reload function .......................................................................................................1-29

Fig. 19 Timers structure ..............................................................................................................1-31

Fig. 20 Watchdog timer function ................................................................................................1-35

Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer.... 1-35

Fig. 22 Serial I/O structure ......................................................................................................... 1-36

Fig. 23 Serial I/O register state when transferring.................................................................. 1-37

Fig. 24 Serial I/O connection example...................................................................................... 1-38

Fig. 25 Timing of serial I/O data transfer ................................................................................. 1-39

Fig. 26 A-D conversion circuit structure ................................................................................... 1-41

Fig. 27 A-D conversion timing chart.......................................................................................... 1-44

Fig. 28 Setting registers .............................................................................................................. 1-44

Fig. 29 Comparator operation timing chart............................................................................... 1-45

Fig. 30 Definition of A-D conversion accuracy ........................................................................ 1-46

Fig. 31 Voltage comparator structure ........................................................................................ 1-47

Fig. 32 Reset release timing ......................................................................................................1-49

Fig. 33 RESET pin input waveform and reset operation .......................................................1-49

Fig. 34 Power-on reset circuit example .................................................................................... 1-50

Fig. 35 Internal state at reset .................................................................................................... 1-51

Fig. 36 Voltage drop detection reset circuit .............................................................................1-52

Fig. 37 Voltage drop detection circuit operation waveform.................................................... 1-52

Fig. 38 State transition ................................................................................................................1-55

Fig. 39 Set source and clear source of the P flag .................................................................1-55

Fig. 40 Start condition identified example using the SNZP instruction ................................1-55

Fig. 41 Clock control circuit structure .......................................................................................1-57

List of figures

iv

4513/4514 Group User’s Manual

List of figures

Fig. 42 Ceramic resonator external circuit ............................................................................... 1-58

Fig. 43 External clock input circuit ............................................................................................ 1-58

Fig. 44 External 0 interrupt program example .........................................................................1-59

Fig. 45 External 1 interrupt program example .........................................................................1-59

Fig. 46 A-D converter operating mode program example ...................................................... 1-60

Fig. 47 Analog input external circuit example-1 ...................................................................... 1-60

Fig. 48 Analog input external circuit example-2 ...................................................................... 1-60

Fig. 49 Pin configuration of built-in PROM version of 4513 Group...................................... 1-88

Fig. 50 Pin configuration of built-in PROM version of 4514 Group...................................... 1-88

Fig. 51 PROM memory map ....................................................................................................... 1-89

Fig. 52 Flow of writing and test of the product shipped in blank......................................... 1-89

CHAPTER 2 APPLICATION

Fig. 2.1.1 Key input by key scan................................................................................................. 2- 7

Fig. 2.1.2 Key scan input timing ..................................................................................................2-8

Fig. 2.2.1 INT0 interrupt operation example ............................................................................ 2-17

Fig. 2.2.2 INT0 interrupt setting example .................................................................................2-18

Fig. 2.2.3 INT1 interrupt operation example ............................................................................ 2-19

Fig. 2.2.4 INT1 interrupt setting example .................................................................................2-20

Fig. 2.2.5 Timer 1 constant period interrupt setting example................................................ 2-21

Fig. 2.2.6 Timer 2 constant period interrupt setting example................................................ 2-22

Fig. 2.2.7 Timer 3 constant period interrupt setting example................................................ 2-23

Fig. 2.2.8 Timer 4 constant period interrupt setting example................................................ 2-24

Fig. 2.3.1 Peripheral circuit example ......................................................................................... 2-30

Fig. 2.3.2 Watchdog timer function............................................................................................ 2-31

Fig. 2.3.3 Constant period measurement setting example .....................................................2-32

Fig. 2.3.4 CNTR0 output setting example ................................................................................2-33

Fig. 2.3.5 CNTR1 input setting example ..................................................................................2-34

Fig. 2.3.6 CNTR0 output control setting example ................................................................... 2-35

Fig. 2.3.7 Timer start by external input setting example (1) ................................................. 2-36

Fig. 2.3.8 Timer start by external input setting example (2) ................................................. 2-37

Fig. 2.3.9 Watchdog timer setting example .............................................................................. 2-38

Fig. 2.4.1 Serial I/O block diagram ........................................................................................... 2-40

Fig. 2.4.2 Serial I/O connection example .................................................................................2-42

Fig. 2.4.3 Serial I/O register state when transmitting/receiving ............................................2-42

Fig. 2.4.4 Serial I/O transfer timing ........................................................................................... 2-43

Fig. 2.4.5 Master serial I/O setting example ............................................................................ 2-46

Fig. 2.4.6 Slave serial I/O example ........................................................................................... 2-47

Fig. 2.4.7 Input waveform of external clock ............................................................................. 2-48

Fig. 2.5.1 A-D converter structure ............................................................................................. 2-49

Fig. 2.5.2 A-D conversion mode setting example ................................................................... 2-51

Fig. 2.5.3 Analog input external circuit example-1 .................................................................. 2-52

Fig. 2.5.4 Analog input external circuit example-2 .................................................................. 2-52

Fig. 2.5.5 A-D converter operating mode program example.................................................. 2-52

Fig. 2.7.1 Power-on reset circuit example ................................................................................ 2-56

Fig. 2.7.2 Oscillation stabilizing time after system is released from reset .......................... 2-56

Fig. 2.7.3 Internal state at reset ................................................................................................ 2-57

Fig. 2.8.1 Voltage drop detection reset circuit ......................................................................... 2-58

Fig. 2.8.2 Voltage drop detection circuit operation waveform ...............................................2-58

Fig. 2.9.1 Start condition identified example ............................................................................ 2-60

Fig. 2.10.1 Oscillation circuit example connecting ceramic resonator externally................ 2-63

Fig. 2.10.2 Structure of clock control circuit ............................................................................2-64

4513/4514 Group User’s Manual

v

List of figures

CHAPTER 3 APPENDIX

Fig. 3.2.1 A-D conversion characteristics data ........................................................................ 3-14

Fig. 44 External 0 interrupt program example .........................................................................3-21

Fig. 45 External 1 interrupt program example .........................................................................3-21

Fig. 46 A-D converter operating mode program example ...................................................... 3-22

Fig. 47 Analog input external circuit example-1 ...................................................................... 3-22

Fig. 48 Analog input external circuit example-2 ...................................................................... 3-22

Fig. 3.4.1 Selection of packages ............................................................................................... 3-24

Fig. 3.4.2 Wiring for the RESET input pin ...............................................................................3-24

Fig. 3.4.3 Wiring for clock I/O pins...........................................................................................3-25

Fig. 3.4.4 Wiring for CNVSS pin .................................................................................................3-25

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version ......................................3-26

Fig. 3.4.6 Bypass capacitor across the VSS line and the VDD line ......................................3-26

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................3-27

Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-27

Fig. 3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-28

Fig. 3.4.10 VSS pattern on the underside of an oscillator ..................................................... 3-28

Fig. 3.4.11 Watchdog timer by software ...................................................................................3-29

vi

4513/4514 Group User’s Manual

List of tables

CHAPTER 1 HARDWARE

Table Selection of system clock ................................................................................................1-11

Table 1 ROM size and pages .................................................................................................... 1-20

Table 2 RAM size ........................................................................................................................1-21

Table 3 Interrupt sources ............................................................................................................ 1-22

Table 4 Interrupt request flag, interrupt enable bit and skip instruction.............................. 1-22

Table 5 Interrupt enable bit function .........................................................................................1-22

Table 6 Interrupt control registers .............................................................................................1-24

Table 7 External interrupt activated conditions........................................................................ 1-26

Table 8 External interrupt control registers .............................................................................. 1-28

Table 9 Function related timers ................................................................................................. 1-30

Table 10 Timer control registers ................................................................................................ 1-32

Table 11 Serial I/O pins .............................................................................................................. 1-36

Table 12 Serial I/O mode register .............................................................................................1-36

Table 13 Processing sequence of data transfer from master to slave ................................ 1-40

Table 14 A-D converter characteristics ..................................................................................... 1-41

Table 15 A-D control registers ...................................................................................................1-42

Table 16 Change of successive comparison register AD during A-D conversion ..............1-43

Table 17 Voltage comparator characteristics ........................................................................... 1-47

Table 18 Voltage comparator control register Q3 ................................................................... 1-48

Table 19 Port state at reset....................................................................................................... 1-50

Table 20 Functions and states retained at RAM back-up .....................................................1-53

Table 21 Return source and return condition .......................................................................... 1-54

Table 22 Key-on wakeup control register, pull-up control register, and interrupt control . 1-56

Table 23 Clock control register MR .......................................................................................... 1-57

Table 24 Maximum value of external clock oscillation frequency ......................................... 1-58

Table 25 Product of built-in PROM version .............................................................................1-88

Table 26 Programming adapters ................................................................................................ 1-89

List of tables

CHAPTER 2 APPLICATION

Table 2.1.1 Pull-up control register PU0 ....................................................................................2-4

Table 2.1.2 Key-on wakeup control register K0 ........................................................................2-5

Table 2.1.3 A-D control register Q2 ............................................................................................2-5

Table 2.1.4 Direction register FR0 .............................................................................................. 2-6

Table 2.1.5 Timer control register W6 ........................................................................................ 2- 6

Table 2.1.6 connections of unused pins ...................................................................................2-10

Table 2.2.1 Interrupt control register V1................................................................................... 2-14

Table 2.2.2 Interrupt control register V2................................................................................... 2-14

Table 2.2.3 Interrupt control register I1 ....................................................................................2-15

Table 2.2.4 Interrupt control register I2 ....................................................................................2-15

Table 2.3.1 Interrupt control register V1................................................................................... 2-27

Table 2.3.2 Interrupt control register V2................................................................................... 2-27

Table 2.3.3 Timer control register W1 ...................................................................................... 2-28

Table 2.3.4 Timer control register W2 ...................................................................................... 2-28

Table 2.3.5 Timer control register W3 ...................................................................................... 2-29

Table 2.3.6 Timer control register W4 ...................................................................................... 2-29

Table 2.4.1 Serial I/O mode register J1 ................................................................................... 2-41

Table 2.4.2 Recommended operating conditions (serial I/O) ................................................. 2-48

4513/4514 Group User’s Manual

vii

List of tables

Table 2.5.1 A-D control register Q1 .......................................................................................... 2-50

Table 2.5.2 A-D control register Q2 .......................................................................................... 2-50

Table 2.5.3 Recommended operating conditions (when using A-D converter) ................... 2-53

Table 2.6.1 Voltage comparator control register Q3 ............................................................... 2-54

Table 2.9.1 Functions and states retained at RAM back-up mode ......................................2-59

Table 2.9.2 Return source and return condition ...................................................................... 2-60

Table 2.9.3 Start condition identification................................................................................... 2-60

Table 2.9.4 Key-on wakeup control register K0 ......................................................................2-60

Table 2.9.5 Pull-up control register PU0 ..................................................................................2-61

Table 2.9.6 Interrupt control register I1 ....................................................................................2-61

Table 2.9.7 Interrupt control register I2 ....................................................................................2-62

Table 2.10.1 Maximum value of oscillation frequency and supply voltage .........................2-63

CHAPTER 3 APPENDIX

Table 3.1.1 Absolute maximum ratings ....................................................................................... 3 -2

Table 3.1.2 Recommended operating conditions 1 ................................................................... 3 -3

Table 3.1.3 Recommended operating conditions 2 ................................................................... 3 -4

Table 3.1.4 Electrical characteristics ........................................................................................... 3 -5

Table 3.1.5 A-D converter recommended operating conditions............................................... 3-6

Table 3.1.6 A-D converter characteristics .................................................................................. 3 -6

Table 3.1.7 Voltage drop detection circuit characteristics........................................................ 3-6

Table 3.1.8 Voltage comparator recommended operating conditions ..................................... 3 -7

Table 3.1.9 Voltage comparator characteristics ......................................................................... 3 -7

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4513/4514 Group User’s Manual

CHAPTER 1CHAPTER 1

HARDWARE

DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
BLOCK DIAGRAM
PERFORMANCE OVERVIEW
PIN DESCRIPTION
FUNCTION BLOCK OPERATIONS
ROM ORDERING METHOD
LIST OF PRECAUTIONS
SYMBOL
LIST OF INSTRUCTION FUNCTION
INSTRUCTION CODE TABLE
MACHINE INSTRUCTIONS
CONTROL REGISTERS
BUILT-IN PROM VERSION

HARDWARE

1-2

4513/4514 Group User’s Manual

HARDWARE

DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION

DESCRIPTION

The 4513/4514 Group is a 4-bit single-chip microcomputer de­signed with CMOS technology. Its CPU is that of the 4500 series
using a simple, high-speed instruction set. The computer is
equipped with serial I/O, four 8-bit timers (each timer has a reload
register), and 10-bit A-D converter.
The various microcomputers in the 4513/4514 Group include varia­tions of the built-in memory type and package as shown in the
table below.

FEATURES

●Minimum instruction execution time ................................ 0.75 µs

(at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0
V to 5.5 V)

●Supply voltage

• Middle-speed mode

...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask

ROM version and One Time PROM version)

...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask

ROM version)
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)

• High-speed mode

...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask

ROM version and One Time PROM version)

...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask

ROM version and One Time PROM version)

...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask

ROM version)
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)

●Timers

Timer 1...................................... 8-bit timer with a reload register

Timer 2...................................... 8-bit timer with a reload register

Timer 3...................................... 8-bit timer with a reload register

Timer 4...................................... 8-bit timer with a reload register

●Interrupt ........................................................................ 8 sources

●Serial I/O....................................................................... 8 bit-wide

●A-D converter ..................10-bit successive comparison method

●Voltage comparator........................................................2 circuits

●Watchdog timer ................................................................. 16 bits

●Voltage drop detection circuit

●Clock generating circuit (ceramic resonator)

●LED drive directly enabled (port D)

APPLICATION

Electrical household appliance, consumer electronic products, of­fice automation equipment, etc.

Product

M34513M2-XXXSP/FP
M34513M4-XXXSP/FP
M34513E4SP/FP (Note)
M34513M6-XXXFP
M34513M8-XXXFP
M34513E8FP (Note)
M34514M6-XXXFP
M34514M8-XXXFP
M34514E8FP (Note)

Note: shipped in blank

ROM (PROM) size

(✕ 10 bits)
2048 words
4096 words
4096 words
6144 words
8192 words
8192 words
6144 words
8192 words
8192 words

RAM size

(✕ 4 bits)
128 words
256 words
256 words
384 words
384 words
384 words
384 words
384 words
384 words

Package

SP: 32P4B FP: 32P6B-A
SP: 32P4B FP: 32P6B-A
SP: 32P4B FP: 32P6B-A

32P6B-A
32P6B-A
32P6B-A
42P2R-A
42P2R-A
42P2R-A

ROM type

Mask ROM
Mask ROM

One Time PROM

Mask ROM
Mask ROM

One Time PROM

Mask ROM
Mask ROM

One Time PROM

4513/4514 Group User’s Manual

1-3

HARDWARE

PIN CONFIGURATION

PIN CONFIGURATION (TOP VIEW) 4513 Group

D
D

D
D

D
D

D6/CNTR0

D

7

/CNTR1

P2

0/SCK

P21/S

OUT

P22/S

IN

RESET

CNV

SS

X

OUT

X

IN

V

SS

1

0
1

2
3

2

4

3

5

4

6

5

7
8

9
10
11
12
13
14
15
16

M34513E4SP

M34513Mx-XXXSP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

P1

3

P1

2

P1

1

P1

0

P0

3

P0

2

P0

1

P0

0

A

IN3

/CMP1+

A

IN2

/CMP1-

A

IN1

/CMP0+

A

IN0

/CMP0­P31/INT1
P3

0

/INT0

VDCE
V

DD

Outline 32P4B

D6/CNTR
D7/CNTR

P20/S

P21/S

OUT

P22/S

D
D

D

CK

3

0

2

P13P1

28

29

13

12

IN

SS

X

V

1

P1

27

14

DD

V

P0

P1

25

26

16

15

/INT0

VDCE

0

P3

24
23
22
21
20
19
18
17

P0
P0
P0

A
A

A
A
P3

IN3
IN2

IN1
IN0

2
1
0

/CMP1+
/CMP1-

/CMP0+
/CMP0-

1

/INT1

0

2

1

D

D

D

32

30

31

3

1
2

4
5

3

M34513Mx-XXXFP

4

0

5

1

6
7

IN

8

M34513ExFP

9

11

10

SS

OUT

X

RESET

CNV

Outline 32P6B-A

1-4

4513/4514 Group User’s Manual

PIN CONFIGURATION (TOP VIEW) 4514 Group

HARDWARE

PIN CONFIGURATION

P1

D
D
D
D
D

D
D6/CNTR0
D

7

/CNTR1

P5
P5
P5
P5

P20/S

CK

P2

1/SOUT

P22/S

IN

RESET

CNV

SS

X

OUT

X

IN

V

SS

1

3

2

0

3

1

4

2

5

3

6

4

7

5

8
9

10

0

11

1

12

2

13

3

14
15
16

17
18

19
20

21

M34514E8FP

M34514Mx-XXXFP

42
41

40
39
38

37
36
35
34

33
32
31
30
29
28
27
26
25
24

23
22

P1

2

P1

1

P1

0

P0

3

P0

2

P0

1

P0

0

P43/A
P42/A
P41/A
P40/A
A

IN3

/CMP1+

A

IN2

/CMP1-

A

IN1

/CMP0+

A

IN0

/CMP0-

P3

3

P3

2

P3

1

/INT1

P3

0

/INT0
VDCE
V

DD

IN7
IN6
IN5
IN4

Outline 42P2R-A

4513/4514 Group User’s Manual

1-5

HARDWARE

|[go1

Voltage drop detection circuit

4

Serial I/O

(8 bi ts ✕ 1)

Voltage comparator

(2 circuits)

X

IN

–X

OUT

I/O port

Internal peripheral functions

Timer

System clock generating circuit

Watchdog timer

(16 bits)

Memory

ROM

2048, 4096,6144, 8192

words × 10 bits

RAM

128, 256, 384 words × 4 bits

4500 Series

CPU core

ALU (4 bits)

Register A (4 bits) Register B (4 bits)

Register D (3 bits) Register E (8 bits)

Stack register SK (8 levels)

Interrupt stack register SDP (1 level)

Timer 1 (8 bits)

Timer 2 (8 bits)

Timer 3 (8 bits)

Timer 4 (8 bits)

A-D converter

(10 bits ✕ 4 ch)

Port D

Port P3

Port P2

Port P1

Port P0

4

3

2

8

BLOCK DIAGRAM

BLOCK DIAGRAM (4513 Group)

1-6

4513/4514 Group User’s Manual

BLOCK DIAGRAM (4514 Group)

Voltage drop detection circuit

Serial I/O

(8 bi ts ✕ 1)

Voltage comparator

(2 circuits)

X

IN

—XOUT

I/O port

Internal peripheral functions

Timer

System clock generating circuit

Watchdog timer

(16 bits)

Memory

ROM

6144, 8192 words × 10 bits

RAM

384 words × 4 bits

4500 Series

CPU core

ALU (4 bits)

Register A (4 bits) Register B (4 bits)

Register D (3 bits) Register E (8 bits)

Stack register SK (8 levels)

Interrupt stack register SDP (1 level)

Timer 1 (8 bits)

Timer 2 (8 bits)

Timer 3 (8 bits)

Timer 4 (8 bits)

A-D converter

(10 bits ✕ 8 ch)

Port DPort P3Port P2Port P1Port P0 Port P5Port P4

4

4

4

4

4

8

3

HARDWARE

BLOCK DIAGRAM

4513/4514 Group User’s Manual

1-7

HARDWARE

PERFORMANCE OVERVIEW

PERFORMANCE OVERVIEW

Parameter
Number of
basic instructions
Minimum instruction execution time
Memory sizes

Input/Output
ports

Timers

A-D converter
Voltage comparator
Serial I/O
Interrupt

Subroutine nesting
Device structure
Package

Operating temperature range
Supply voltage

Power
dissipation
(typical value)

ROM

RAM

D0–D7

P00–P03

P10–P13

P20–P22
P30–P33

P40–P43
P50–P53
CNTR0
CNTR1
INT0
INT1
Timer 1
Timer 2
Timer 3
Timer 4

Sources
Nesting

4513 Group
4514 Group

Active mode

RAM back-up mode

4513 Group
4514 Group

M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
I/O (Input is

examined by
skip decision)

I/O

I/O

Input
I/O

I/O
I/O
I/O
I/O
Input
Input

123
128

0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode)
2048 words ✕ 10 bits
4096 words ✕ 10 bits
6144 words ✕ 10 bits
8192 words ✕ 10 bits
6144 words ✕ 10 bits
8192 words ✕ 10 bits
128 words ✕ 4 bits
256 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
Eight independent I/O ports;

ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.

3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively.
4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and

INT1, respectively. The 4513 Group does not have ports P32, P33.
4-bit I/O port; The 4513 Group does not have this port.
4-bit I/O port with a direction register ; The 4513 Group does not have this port.
1-bit I/O; CNTR0 pin is also used as port D6.
1-bit I/O; CNTR1 pin is also used as port D7.
1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function.
1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 circuits (CMP0, CMP1)
8-bit ✕ 1
8 (two for external, four for timer, one for A-D, and one for serial I/O)
1 level
8 levels
CMOS silicon gate
32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A)
42-pin plastic molded SSOP (42P2R-A)
–20 °C to 85 °C

2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the
electrical characteristics because the supply voltage depends on the oscillation frequency.)

1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transis-

3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors

0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

Function

tors in the cut-off state)

in the cut-off state)

1-8

4513/4514 Group User’s Manual

PIN DESCRIPTION

Pin
VDD
VSS
VDCE

CNVSS
RESET

XIN
XOUT
D0–D7

P00–P03

P10–P13
P20–P22

P30–P33

P40–P43

P50–P53

AIN0–AIN7

CNTR0

CNTR1

INT0, INT1

SIN

SOUT

SCK

CMP0­CMP0+

CMP1­CMP1+

Name
Power supply
Ground
Voltage drop detec-

tion circuit enable

CNVSS
Reset input

System clock input
System clock output
I/O port D

(Input is examined
by skip decision.)

I/O port P0

I/O port P1
Input port P2

I/O port P3

I/O port P4

I/O port P5

Analog input

Timer input/output

Timer input/output

Interrupt input

Serial data input

Serial data output

Serial I/O clock
input/output

Voltage comparator
input

Voltage comparator
input

Input/Output

—
—

Input

—

I/O

Input

Output

I/O

I/O
I/O

Input

I/O

I/O

I/O

Input

I/O

I/O

Input

Input

Output

I/O

Input

Input

HARDWARE

PIN DESCRIPTION

Function
Connected to a plus power supply.
Connected to a 0 V power supply.
VDCE pin is used to control the operation/stop of the voltage drop detection circuit.

When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to
this pin, the circuit is stopped.

Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer

causes the system to be reset or system reset is performed by the voltage drop de­tection circuit, the RESET pin outputs “L” level.

I/O pins of the system clock generating circuit. XIN and XOUT can be connected to
ceramic resonator. A feedback resistor is built-in between them.

Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out­put latch. For input use, set the latch of the specified bit to “1.” The output structure
is N-channel open-drain.
Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.

Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs
when the output latch is set to “1.” The output structure is N-channel open-drain.
Every pin of the ports has a key-on wakeup function and a pull-up function. Both
functions can be switched by software.

3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, re­spectively.

4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the
specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and
P31 are also used as INT0 and INT1, respectively.
The 4513 Group does not have ports P32, P33.

4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Ports P40–P43 are also used as analog input
pins AIN4–AIN7, respectively.
The 4513 Group does not have port P4.

4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O
function. For input use, set the direction register to “0.” For output use, set the di­rection regiser to “1.” The output structure is CMOS.
The 4513 Group does not have port P5.

Analog input pins for A-D converter. AIN0–AIN3 are also used as voltage compara­tor input pins and AIN4–AIN7 are also used as port P4.
The 4513 Group does not have AIN4–AIN7.

CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the timer 1 underflow signal divided by 2.
CNTR0 pin is also used as port D6.

CNTR1 pin has the function to input the clock for the timer 4 event counter, and to
output the timer 3 underflow signal divided by 2.
CNTR1 pin is also used as port D7.

INT0, INT1 pins accept external interrupts. They also accept the input signal to re­turn the system from the RAM back-up state.
INT0, INT1 pins are also used as ports P3 0 and P31, respectively.

SIN pin is used to input serial data signals by software.
SIN pin is also used as port P22.

SOUT pin is used to output serial data signals by software.
SOUT pin is also used as port P21.

SCK pin is used to input and output synchronous clock signals for serial data trans­fer by software.
SCK pin is also used as port P20.

CMP0-, CMP0+ pins are used as the voltage comparator input pin when the volt­age comparator function is selected by software.
CMP0-, CMP0+ pins are also used as AIN0 and AIN1.

CMP1-, CMP1+ pins are used as the voltage comparator input pin when the volt­age comparator function is selected by software.
CMP1-, CMP1+ pins are also used as AIN2 and AIN3.

4513/4514 Group User’s Manual

1-9

HARDWARE

PIN DESCRIPTION

MULTIFUNCTION

Pin
D6
D7
P20
P21
P22
P30
P31

Notes 1: Pins except above have just single function.

2: The input of D

S

3: The 4513 Group does not have P4

CONNECTIONS OF UNUSED PINS

XOUT
VDCE
D0–D5

D6/CNTR0
D7/CNTR1

P20/SCK
P21/SOUT
P22/SIN

P30/INT0
P31/INT1
P32, P33

P40/AIN4–P43/AIN7

P50–P53 (Note 1)

AIN0/CMP0­AIN1/CMP0+
AIN2/CMP1­AIN3/CMP1+

P00–P03
P10–P13

Multifunction
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1

6, D7, P20–P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40–P43 can be used even when CNTR0, CNTR1,

CK, SOUT, SIN, INT0, INT1, and AIN0–AIN7 are selected.

Pin

Pin
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1

0/AIN4–P43/AIN7.

Connection
Open (when using an external clock).
Connect to VSS.
Connect to VSS, or set the output latch to

“0” and open.

Connect to VSS.

Connect to VSS, or set the output latch to
“0” and open.

Connect to VSS, or set the output latch to
“0” and open.

When the input mode is selected by soft­ware, pull-up to VDD through a resistor or
pull-down to VDD.
When selecting the output mode, open.

Connect to VSS.

Open or connect to VSS (Note 2)
Open or connect to VSS (Note 2)

Multifunction
D6
D7
P20
P21
P22
P30
P31

Pin
AIN0
AIN1
AIN2
AIN3
P40
P41
P42
P43

Notes 1: After system is released from reset, port P5 is in an input mode (di-

2: When the P0

(Note when the output latch is set to “0” and pins are open)

● After system is released from reset, port is in a high-impedance state un-

til it is set the output latch to “0” by software. Accordingly, the voltage
level of pins is undefined and the excess of the supply current may occur
while the port is in a high-impedance state.

● To set the output latch periodically by software is recommended because

value of output latch may change by noise or a program run away
(caused by noise).

(Note when connecting to V

● Connect the unused pins to V

shortest distance against noise.

Multifunction
CMP0­CMP0+
CMP1­CMP1+
AIN4
AIN5
AIN6
AIN7

rection register FR0 = 0000

0–P03 and P10–P13 are connected to VSS , turn off

their pull-up transistors (register PU0i=“0”) and also invalidate the
key-on wakeup functions (register K0i=“0”) by software. When
these pins are connected to V
tions are left valid, the system fails to return from RAM back-up
state. When these pins are open, turn on their pull-up transistors
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up
functions with every two pins. If only one of the two pins for the
key-on wakeup function is used, turn on their pull-up transistors by
software and also disconnect the other pin. (i = 0, 1, 2, or 3.)

SS and VDD)

Pin
CMP0­CMP0+
CMP1­CMP1+
AIN4
AIN5
AIN6
AIN7

2)

SS while the key-on wakeup func-

SS and VDD using the thickest wire at the

Multifunction
AIN0
AIN1
AIN2
AIN3
P40
P41
P42
P43

1-10

4513/4514 Group User’s Manual

PORT FUNCTION

Port

Port D

Port P0

Port P1

Port P2

Port P3
(Note 1)

Port P4
(Note 2)

Port P5
(Note 2)

Notes 1: The 4513 Group does not have P32 and P33.

2: The 4513 Group does not have these ports.

Pin

D0–D5
D6/CNTR0
D7/CNTR1

P00–P03

P10–P13

P20/SCK
P21/SOUT
P22/SIN

P30/INT0
P31/INT1
P32, P33

P40/AIN4
–P43/AIN7

P50–P53

Input

Output

I/O
(8)

I/O
(4)

I/O
(4)

Input

(3)

I/O
(4)

I/O
(4)

I/O
(4)

N-channel open-drain

N-channel open-drain

N-channel open-drain

N-channel open-drain

N-channel open-drain

CMOS

Output structure

I/O

unit

1

4

4

3

4

4

4

Control

instructions

SD, RD
SZD
CLD

OP0A
IAP0

OP1A
IAP1

IAP2

OP3A
IAP3

OP4A
IAP4

OP5A
IAP5

Control

registers

W6
PU0, K0

PU0, K0

J1

I1, I2

Q2

FR0

HARDWARE

PIN DESCRIPTION

Remark

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

Built-in key-on wakeup
function
(P30/INT0, P31/INT1)

DEFINITION OF CLOCK AND CYCLE

● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg­ister MR.

Table Selection of system clock

Register MR

MR3

0
1

Note: f(XIN)/2 is selected after system is released from reset.

● Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.

● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.

System clock

f(XIN)

f(XIN)/2

4513/4514 Group User’s Manual

1-11

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS

Key-on wakeup input

K0

0

IAP0 instruction

Pull-up
transistor

PU0

0

Register A

Ai

OP0A instruction

Key-on wakeup input

Register A

Ai

OP0A instruction

Key-on wakeup input

D

T

Q

K0

1

IAP0 instruction

D

Q

T

K0

2

IAP1 instruction

Pull-up
transistor

PU0

1

Pull-up
transistor

PU0

2

P00,P01

P02,P03

Register A

Ai

OP1A instruction

Key-on wakeup input

Register A

Ai

OP1A instruction

D

T

Q

K0

3

IAP1 instruction

D

T

Q

Pull-up
transistor

PU0

3

•

i represents 0, 1, 2, or 3.

•

This symbol represents a parasitic diode on the port.

P10,P11

P12,P13

1-12

4513/4514 Group User’s Manual

PORT BLOCK DIAGRAMS (continued)

Synchronous clock input for serial transfer

Synchronous clock output for serial transfer

J1

Register A

0

Register A

IAP2 instruction

J1

1

0

1

IAP2 instruction

HARDWARE

PIN DESCRIPTION

P20/SCK

Serial data output

Register A

Key-on wakeup input

External interrupt circuit

Register A

Ai

OP3A instruction

Register A

Serial data input

IAP2 instruction

IAP3 instruction

D

T

IAP3 instruction

J1

1

0

1

P21/SOUT

P22/SIN

P30/INT0,P31/INT1

Q

P32,P33

Ai

OP3A instruction

•

• Applied potential to ports P2

• i represents 0, 1, 2, or 3.

• The 4513 Group does not have ports P3

This symbol represents a parasitic diode on the port.

D

T

Q

0

—P22 must be VDD.

4513/4514 Group User’s Manual

2

, P33.

1-13

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS (continued)

Q1

Decoder

Analog input

Q3

0

CMP0

Analog input

Analog input

Q3

1

Q3

A

IN0

/CMP0-

-

+

2

Q1

Decoder

A

IN1

/CMP0+

Q1

Decoder

A

IN2

/CMP1-

-

+

Analog input

Register A

Ai

OP4A instruction

Analog input

CMP1

IAP4 instruction

D
T

Q

Q3

3

Q1

Decoder

A

IN3

/CMP1+

P40/A

IN4

–P43/A

IN7

Q1

Decoder

•

• i represents 0, 1, 2, or 3.

• The 4513 Group does not have port P4.

This symbol represents a parasitic diode on the port.

1-14

4513/4514 Group User’s Manual

PORT BLOCK DIAGRAMS (continued)

Direction register FR0i

DTQ

Ai

OP5A instruction

Register A

IAP5 instruction

P50–P5

HARDWARE

PIN DESCRIPTION

3

Register Y

Decoder

CLD instruction

SD instruction

RD instruction

Skip decision

Clock input for timer 2 event count

DecoderRegister Y

CLD instruction

SD instruction

RD instruction

Timer 1 underflow signal divided by 2 or

signal of AND operation between

timer 1 underflow signal divided by 2 and

timer 2 underflow signal divided by 2

Skip decision

Clock input for timer 4 event count

Skip decision

(SZD instruction)

(SZD instruction)

S

R

Q

(SZD instruction)

S

R

W6

D0–D

5

Q

0

0

1

D6/CNTR0

DecoderRegister Y

CLD instruction
SD instruction
RD instruction

Timer 3 underflow signal divided by 2 or

signal of AND operation between

timer 3 underflow signal divided by 2 and

timer 4 underflow signal divided by 2

S
R

W6

2

0

Q

1

•

• Applied potential to ports D

This symbol represents a parasitic diode on the port.

• i represents 0, 1, 2, or 3.

• The 4513 Group does not have port P5.

4513/4514 Group User’s Manual

D7/CNTR1

0–D7

must be 12 V.

1-15

HARDWARE

PIN DESCRIPTION

0

/INT0

P3

I1

2

Falling

Rising

One-sided edge

0

1

detection circuit

Both edges
detection circuit

Wakeup

SNZI0

Skip

I1

1

0

EXF0

1

External 0
interrupt

1

/INT1

P3

External interrupt circuit structure

I2

2

Falling

Rising

0

1

SNZI1

One-sided edge
detection circuit

Both edges
detection circuit

Wakeup

Skip

This symbol represents a parasitic diode on the port.

I2

1

0

EXF1

1

External 1
interrupt

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4513/4514 Group User’s Manual

FUNCTION BLOCK OPERATIONS
CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4­bit data addition, comparison, AND operation, OR operation, and
bit manipulation.

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer, ex­change, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig­ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.

HARDWARE

FUNCTION BLOCK OPERATIONS

<Carry>

(CY)

(M(DP))

Addition

(A)

Fig. 1 AMC instruction execution example

<Set>

SC instruction

RC instruction

CY A3 A2 A1 A0

ALU

<Result>

<Clear>

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).

(4) Register D

Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).

TABP p instruction

Specifying address

RAR instruction

A0 CY A3 A2 A1

Fig. 2 RAR instruction execution example

Register B Register A

Register E

Fig. 3 Registers A, B and register E

E7 E6 E5 E4 E3 E2 E1 E0

B3 B2 B1 B0

Register B Register A

TAB instruction

A3 A2 A1 A0B3 B2 B1 B0

TEAB instruction

TABE instruction

A3 A2 A1 A0

TBA instruction

ROM

840

<Rotation>

PCH

p6 p5 p4 p3 p2 p1 p0

Immediate field

value p

Fig. 4 TABP p instruction execution example

DR2DR1DR0

The contents of

register D

4513/4514 Group User’s Manual

PCL

A3 A2 A1 A0

The contents of

register A

Low-order 4bits

Register A (4)

Middle-order 4 bits

Register B (4)

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