RENESAS 3803 Technical data
查询M38030F1-XXXHP供应商
3803 Group (Spec.L)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3803 group (Spec.L) is the 8-bit microcomputer based on the
740 family core technology.
The 3803 group (Spec.L) is designed for household products,
office automation equipment, and controlling systems that
require analog signal processing, including the A/D converter
and D/A converters.
FEATURES
• Basic machine-language instructions ................................. 71
• Minimum instruction execution time .......................... 0.24 µs
(at 16.8 MHz oscillation frequency)
• Memory size
Mask ROM/Flash memory ............................ ........ 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports ................ ....................... 56
• Software pull-up resistors............................................ Built-in
• Interrupts
21 sources, 16 vectors........................ .......................................
(external 8, internal 12, software 1)
• Timers .. ............................... ................................ ..... 16-bit × 1
8-bit × 4
(with 8-bit prescaler)
• Serial interface.........8-bit × 2 (UART or Clock-synchronized)
8-bit × 1 (Clock-synchronized)
• PWM ....................................... 8-bit × 1 (with 8-bit prescaler)
• A/D converter ........................................ 10-bit × 16 channels
(8-bit reading enabled)
• D/A converter ............................................ 8-bit × 2 channels
• Watchdog timer ...................................................... 16-bit × 1
• LED direct drive port..............................................................8
• Clock generating circuit ............................. Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (Mask ROM version)
[In high-speed mode]
At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency ....................4.0 to 5.5 V
At 8.4 MHz oscillation frequency ......................2.7 to 5.5 V
At 4.2 MHz oscillation frequency ......................2.2 to 5.5 V
At 2.1 MHz oscillation frequency ......................2.0 to 5.5 V
[In middle-speed mode]
At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency ....................2.7 to 5.5 V
At 8.4 MHz oscillation frequency ......................2.2 to 5.5 V
At 6.3 MHz oscillation frequency ......................1.8 to 5.5 V
[In low-speed mode]
At 32 kHz oscillation frequency.........................1.8 to 5.5 V
REJ03B0212-0100
Rev.1.00
Apr 2, 2007
• Power source voltage (Flash memory version)
[In high-speed mode]
At 16.8 MHz oscillation frequency....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency............ ........4.0 to 5.5 V
At 8.4 MHz oscillation frequency......................2.7 to 5.5 V
[In middle-speed mode]
At 16.8 MHz oscillation frequency....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency............ ........2.7 to 5.5 V
[In low-speed mode]
At 32 kHz oscillation frequency......................... 2.7 to 5.5 V
• Power dissipation (Mask ROM version)
In high-speed mode ........................................... 40 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ................... ......................... 45 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
• Power dissipation (Flash memory version)
In high-speed mode ........................................ 27.5 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ........................................ 1200 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
• Operating temperature range ............................. −20 to 85 °C
• Packages
SP...............PRDP0064BA-A (64P4B) (64-pin 750 mil SDIP)
......PLQP0064KB-A (64P6Q-A) (64-pin 10 × 10 mm LQFP)
HP
KP
......PLQP0064GA-A (64P6U-A) (64-pin 14 × 14 mm LQFP)
WG ........PTLG0064JA-A (64F0G) (64-pin 6 × 6 mm FLGA)
<Flash memory mode>
• Power source voltage .................. .............. V
• Program/Erase voltage ............................. VCC = 2.7 to 5.5 V
• Programming method .. ............. Programming in unit of byte
• Erasing method ................................................. Block erasing
• Program/Erase control by software command
• Number of times for programming/erasing ...................... 100
<Notes>
The flash memory version cannot be used for application
embedded in the MCU card.
CC = 2.7 to 5.5 V
Rev.1.00 Apr 2, 2007 Page 1 of 117
REJ03B0212-0100
3803 Group (Spec.L)
P37/SRDY3
P36/SCLK3
P35/TXD3
P34/RXD3
P33
P32
P31/DA2
P30/DA1
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P00/AN8
P01/AN9
P02/AN10
48
474645444342414039383736353433
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
M38039MFL-XXXHP/KP
M38039FFLHP/KP
123456789
P03/AN11
P04/AN12
P05/AN13
P06/AN14
P07/AN15
P10/INT41
P11/INT01
P12
P13
P16
P14
P15
P17
32
P20(LED0)
31
P2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
10111213141516
1(LED1)
P2
2(LED2)
3(LED3)
P2
4(LED4)
P2
P2
5(LED5)
P2
6(LED6)
P27(LED7)
VSS
XOUT
XIN
P40/INT40/XCOUT
P41/INT00/XCIN
RESET
SS
CNV
P42/INT1
P61/AN1
P60/AN0
P62/AN2
5/CNT R1
P57/INT3
P56/PWM
P54/CNT R0
P5
P50/SIN2
P52/SCLK2
P51/SOUT2
P53/SRDY2
P47/SRDY1/C NTR2
P43/INT2
P45/TXD1
P44/RXD1
P46/SCLK1
Package code : PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A)
Fig 1. Pin configuration (Top view) PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A)
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/INT3
P56/PWM
5/CNTR1
P5
P54/CNTR0
P53/SRDY2
P52/SCLK2
P51/SOUT2
P50/SIN2
P47/SRDY1/CNTR2
P46/SCLK1
P45/TXD1
P44/RXD1
P43/INT2
P42/INT1
CNVSS
RESET
P4
1/INT00/XCIN
P40/INT40/XCOUT
XOUT
VCC
XIN
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
M38039MFL-XXXSP
M38039FFLSP
641
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P30/DA1
P31/DA2
P32
P33
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
P00/AN8
P01/AN9
P02/AN10
P03/AN11
P04/AN12
P05/AN13
P06/AN14
P07/AN15
P10/INT41
P11/INT01
P1
2
P13
P14
P15
P16
P17
P20(LED0)
1(LED1)
P2
P2
2(LED2)
P23(LED3)
P2
4(LED4)
P2
5(LED5)
P2
6(LED6)
P27(LED7)
Package code : PRDP0064BA-A (64P4B)
Fig 2. Pin configuration (Top view) (PRDP0064BA-A (64P4B))
Rev.1.00 Apr 2, 2007 Page 2 of 117
REJ03B0212-0100
3803 Group (Spec.L)
PIN CONFIGURATION (TOP VIEW)
ABCDEFGH
8
7
6
5
4
3
2
50 46 44 41 40 32 31 30
P3
6/SCLK3 P02/AN10 P04/AN12 P07/AN15 P10/INT41 P20(LED0)P21(LED1)P22(LED2)
51 47 45 42 39 27 29 28
P3
5/TXD3 P01/AN9 P03/AN11 P06/AN14 P11/INT01 P25(LED5)P23(LED3)P24(LED4)
53 52 48 43 38 37 26 25
P33 P34/RXD3 P00/AN8 P05/AN13 P12 P13 P26(LED6)P27(LED7)
56 55 54 49 33 36 35 34
P30/DA1 P31/DA2 P32 P37/SRDY3 P17 P14 P15 P16
1 64 58 59 57 24 22 23
2/AN2 P63/AN3 VREF AVSS VCC VSS XIN XOUT
P6
60 61 4 7 12 14 21 20
P67/AN7 P66/AN6 P57/INT3 P54/CNTR0
P4
7/SRDY1/CNTR2
P45/TXD1
P4
62 63 5 8 10 13 17 19
P65/AN5 P64/AN4 P56/PWM P53/SRDY2 P51/SOUT2 P46/SCLK1 P42/INT1 RESET
0/INT40/XCOUT
8
7
6
5
4
3
P41/INT00/XCIN
2
1
2 3 6 9 11 15 16 18
P61/AN1 P60/AN0 P55/CNTR1 P52/SCLK2 P50/SIN2 P44/RXD1 P43/INT2 CNVSS
ABCDEFGH
Package code : PTLG0064JA-A (64F0G)
Note : The numbers in circles corresponds with the number on the packages FP/HP/KP.
Fig 3. Pin configuration (Top view) (PTLG0064JA-A (64F0G))
1
M38039MFL
-XXXWG
M38039
FFLWG
Package (TOP VIEW)
Rev.1.00 Apr 2, 2007 Page 3 of 117
REJ03B0212-0100
3803 Group (Spec.L)
Table 1 Performance overview
Parameter Function
Number of basic instructions 71
Minimum instruction execution time 0.24 µs (Oscillation frequency 16.8 MHz)
Oscillation frequency Oscillation frequency 16.8 MHz(Maximum)
Memory
sizes
I/O port P0-P6 56 pins
Software pull-up resistors Built-in
Interrupt 21 sources, 16 vectors (8 external, 12 internal, 1 software)
Timer 8-bit × 4 (with 8-bit prescaler), 16-bit × 1
Serial interface 8-bit × 2 (UART or Clock-synchronized)
PWM 8-bit × 1 (with 8-bit prescaler)
A/D converter 10-bit × 16 channels (8-bit reading enabled)
D/A converter 8-bit × 2 channels
Watchdog timer 16-bit × 1
LED direct drive port
Clock generating circuits Built-in 2 circuits
Power
source
voltage
Power
dissipation
Input/Output
characteristics
Operating temperature range -20 to 85 °C
Device structure CMOS sillicon gate
Package 64-pin plastic molded SDIP/LQFP/FLGA
Mask ROM version ROM 60 Kbytes
RAM 2048 bytes
Flash memory version ROM 60 Kbytes
RAM 2048 bytes
8-bit × 1 (Clock-synchronized)
8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)
(connect to external ceramic rasonator or quartz-crystal oscillator)
In high-speed
mode
In middlespeed mode
In low-speed
mode
In high-speed mode Mask ROM version 40 mW
In low-speed mode Mask ROM version 45 µW
Input/Output withstand voltage VCC
Output current 10 mA
At 16.8 MHz
At 12.5 MHz
At 8.4 MHz
At 4.2 MHz Mask ROM version 2.2 to 5.5 V
At 2.1 MHz Mask ROM version 2.0 to 5.5 V
At 16.8 MHz
At 12.5 MHz
At 8.4 MHz Mask ROM version 2.2 to 5.5 V
At 6.3 MHz Mask ROM version 1.8 to 5.5 V
At 32 MHz
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version 1.8 to 5.5 V
Flash memory version 2.7 to 5.5 V
Flash memory version 27.5 mW
Flash memory version 1200 µW
4.5 to 5.5 V
4.0 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
Rev.1.00 Apr 2, 2007 Page 4 of 117
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3803 Group (Spec.L)
Reset in p ut
26
CNVSS
27
RESET
1
VCC
32
VSS
P0 (8)
Timer 1 (8 )
Timer 2 (8 )
Timer Y (8)
Timer X (8 )
INT01
INT41
Timer Z (16)
P1 (8)
Prescaler Y (8)
Prescaler X (8)
Prescaler 12 (8)
CNTR0
CNTR1
CNTR2
SI/O3 (8)
P2 (8)
P3 (8)
D/A
1 (8)
converter
A
X
Y
S
PS
PCLPCH
Data bus
D/A
2 (8)
converter
INT00
INT1
INT2
INT40
I/O port P0
49 50 51 52 5354 55 56
44 46 48
43 45 47
I/O port P1
42
41
I/O port P2
(LED drive)
33 35 37 3934 36 38 40
I/O port P3
58 6259 61 6360 6457
C P U
0
P4 (8)
I/O port P4
21 2522 24 2823 2920
R A M R O M
29
Sub-clock
output
28
XCIN XCOUT
Sub-clock
input
31
Main
clock
output
30
XIN XOUT
Main
clock
input
Clock generating circuit
FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0064BA-A (64P4B))
Fig 4. Functional block diagram
Rev.1.00 Apr 2, 2007 Page 5 of 117
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SI/O2 (8) SI/O1 (8)
P5 (8)
INT3
PWM (8)
P6 (8)
A/D
(10)
converter
1912
13 1714 16 1815
4681057911
3
2
I/O port P5
I/O port P6
AVSS
VREF
3803 Group (Spec.L)
PIN DESCRIPTION
Table 2 P in des c r iption
Pin Name Functions
CC, VSS Power source • Apply voltage of 1.8 V − 5.5 V to VCC, and 0 V to VSS. In the flash memory version, apply
V
SS CNVSS input • This pin controls the operation mode of the chip.
CNV
REF Reference
V
voltage of 2.7 V − 5.5 V to V
• Normally connected to V
CC.
SS.
• Reference voltage input pin for A/D and D/A converters.
Function except a port function
voltage
SS Analog power
AV
source
RESET
IN Main clock input • Input and output pins for the clock generating circuit.
X
OUT Main clock
X
Reset input • Reset input pin for active “L”.
output
P0
P0
P1
0/AN8−
7/AN15
0/INT41
I/O port P0 • 8-bit CMOS I/O port.
I/O port P1 • Interrupt input pin
P11/INT01
2−P17
P1
P20(LED0)P2
7(LED7)
0/DA1
P3
I/O port P2
I/O port P3 • 8-bit CMOS I/O port.
P31/DA2
P3
2, P33
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
0/INT40/XCOUT
P4
I/O port P4 • 8-bit CMOS I/O port.
P41/INT00/XCIN
P4
2/INT1
P43/INT2
4/RXD1
P4
• Analog power source input pin for A/D and D/A converters.
• Connect to V
SS.
• Connect a ceramic resonator or quartz-crystal oscillator between the X
the oscillation frequency.
• When an external clock is used, connect the clock source to the X
IN pin and leave the XOUT pin
open.
• A/D converter input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
•P2
0 − P27 (8 bits) are enabled to output large current for
LED drive.
• D/A converter input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
•P3
0, P31, P34 − P37 are CMOS 3-state output structure.
•P3
2, P33 are N-channel open-drain output structure.
• Pull-up control of P3
0, P31, P34 − P37 is enabled in a bit unit.
• Serial I/O3 function pin
• Interrupt input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• Sub-clock generating I/O pin
(resonator connected)
• Interrupt input pin
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• Serial I/O1 function pin
IN and XOUT pins to set
P45/TXD1
P46/SCLK1
P4
7/SRDY1/CNTR2
0/SIN2
P5
I/O port P5 • Serial I/O2 function pin
• Serial I/O1, timer Z function pin
P51/SOUT2
P52/SCLK2
P53/SRDY2
4/CNTR0 • Timer X function pin
P5
5/CNTR1 • Timer Y function pin
P5
6/PWM • PWM output pin
P5
7/INT3 • Interrupt input pin
P5
P6
P6
0/AN0−
7/AN7
I/O port P6 • A/D converter input pin
Rev.1.00 Apr 2, 2007 Page 6 of 117
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3803 Group (Spec.L)
PART NUMBERING
Product name
M3803 9 M F
−
L
XXX SP
Package code
SP : PRDP0064BA-A (64P4B)
HP : PLQP0064KB-A (64P6Q-A)
KP : PLQP0064GA-A (64P6U-A)
WG : PTLG0064JA-A (64F0G)
ROM number
Omitted in the flash memory version.
−: standard
Omitted in the flash memory version.
−: Minner spec. change product
L
ROM/Flash memory size
1: 4096 bytes
2: 8192 bytes
3: 12288 bytes
4: 16384 bytes
5: 20480 bytes
6: 24576 bytes
7: 28672 bytes
8: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
Fig 5. Part numbering
Memory type
M:Mask ROM version
F: Flash memory version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Rev.1.00 Apr 2, 2007 Page 7 of 117
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3803 Group (Spec.L)
GROUP EXPANSION
Renesas plans to expand the 3803 group (Spec.L) as follows.
Memory Size
• Flash memory size .....................................................60 Kbytes
• Mask ROM size.........................................................60 Kbytes
• RAM size................................................................. 2048 bytes
Memory Expansion Plan
ROM size (bytes)
60 K
48 K
32 K
Packages
• PRDP0064BA-A (64P4B)
..............................................64-pin shrink plastic-molded DIP
• PLQP0064KB-A (64P6Q-A)
...........................................0.5 mm-pitch plast ic molded LQFP
• PLQP0064GA-A (64P6U-A)
...........................................0.8 mm-pitch plast ic molded LQFP
• PTLG0064JA-A (64F0G)
........................................0.65 mm-pitch plastic molded FLGA
M38039FFL
M38039MFL
28 K
24 K
20 K
16 K
12 K
8 K
512
384 768640
1024896 12801152 1408 20481536
RAM size (byte s)
Fig 6. Memory expansion plan
Table 3 S up port products
Part No.
M38039MFL-XXXSP
M38039MFL-XXXHP PLQP0064KB-A (64P6Q-A)
M38039MFL-XXXKP PLQP0064GA-A (64P6U-A)
M38039MFL-XXXWG PTLG0064JA-A (64F0G)
M38039FFLSP
M38039FFLHP PLQP0064KB-A (64P6Q-A)
M38039FFLKP PLQP0064GA-A (64P6U-A)
M38039FFLWG PTLG0064JA-A (64F0G)
ROM size (bytes)
ROM size for User in ( )
61440
(61310)
57344+4096 (NOTE) 2048
RAM size
(bytes)
2048
Package Remarks
PRDP0064BA-A (64P4B)
PRDP0064BA-A (64P4B)
NOTE:
1. ROM size includes the ID code area.
Mask ROM version
Flash memory version
VCC = 2.7 to 5.5 V
40323072
Rev.1.00 Apr 2, 2007 Page 8 of 117
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3803 Group (Spec.L)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3803 group (Spec.L) uses the standard 740 Family
instruction set. Refer to the table of 740 Family addressing
modes and machine instructions or the 740 Family Software
Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc. are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y
and specifies the real address.
b7 b0
A
b7 b0
X
b7 b0
Y
b7 b0
S
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and
interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0”, the high-order 8 bits becomes
“00
16”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “01
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 8.
Store registers other than those described in Fi gure 7 with
program when the user needs them during interrupts or
subroutine calls (see Table 4).
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC
next instruction to be executed.
16”.
H and PCL. It is used to indicate the address of the
Accumulator
Index Register X
Index Register Y
Stack Pointer
b15
b7 b0
b7 b0
Fig 7. 740 Family CPU register structure
PC
LPCH
Program Counter
CZIDBTVN
Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
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3803 Group (Spec.L)
On-going Routine
Push Return
Address
on Stack
POP Return
Address from
Stack
Interrupt request
M(S)←(PCH)
(S)←(S) − 1
M(S)←(PCL)
(S)←(S) − 1
Subroutine
.....
Execute RTS
(S)←(S) + 1
(PCL)←M(S)
(1)
Execute JSR
M(S)←(PCH)
(S)←(S) − 1
M(S)←(PCL)
(S)←(S) − 1
M(S)←(PS)
(S)←(S) − 1
Interrupt
Service Routine
.....
Execute RTI
(S)←(S) + 1
(PS)←M(S)
(S)←(S) + 1
Push Return Address
on Stack
Push Contents of
Processor
Status Register on Stack
I Flag is Set from
“0” to “1”
Fetch the Jump
Vector
POP Contents of
Processor Status Register
from Stack
(S)←(S) + 1
(PCH)←M(S)
Note 1 : Condition for acceptance of an interrupt → Interrupt enable flag is “1”
Interrupt disable flag is “0”
(PCL)←M(S)
(S)←(S) + 1
(PCH)←M(S)
POP Return
Address from Stack
Fig 8. Register push and pop at interrupt generatio n and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack Pop instruction from stack
Accumulator PHA PLA
Processor status register PHP PLP
Rev.1.00 Apr 2, 2007 Page 10 of 117
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3803 Group (Spec.L)
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a sh ift or rotate
instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it
is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can execute decimal arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”.
Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to −
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the
BIT instruction is stored in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction SEC
Clear instruction CLC − CLI CLD − CLT CLV −
− SEI SED − SET −−
Rev.1.00 Apr 2, 2007 Page 11 of 117
REJ03B0212-0100
3803 Group (Spec.L)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
internal system clock control bits, etc.
The CPU mode register is allocated at address 003B16.
b7 b0
1
CPU mode register
(CPUM: address 003B
Processor mode bits
b1 b0
0 0 : Single-chip mode
01:
1 0 : Not available
11:
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
CIN-XCOUT oscillating function
1:X
Main clock (X
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
00:φ = f(X
01:φ = f(X
10:φ = f(X
1 1 : Not available
IN-XOUT) stop bit
16)
IN)/2 (high-speed mode)
IN)/8 (middle-speed mode)
CIN)/2 (low-speed mode)
Fig 9. Structure of CPU mode register
Rev.1.00 Apr 2, 2007 Page 12 of 117
REJ03B0212-0100
3803 Group (Spec.L)
MISRG
(1) Bit 0 of address 0010
16: Oscillation stabilizing time
set after STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external
interrupt source, usually, the fixed values of Timer 1 and
Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are
automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by setting “1” to bit 0
of MISRG (address 0010
16).
However, by setting this bit to “1”, the previous values, set just
before the STP instruction was executed, will remain in Timer 1
and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation
stabilizing time, before executing the STP instruction.
Figure 10 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 0010
16: Middle-speed Mode
Automatic Switch Function
In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary:
set CPU mode register (003B
16) --> start main clock oscillation
--> wait for oscillation stabilization --> switch to middle-speed
mode (or high-speed mode).
However, the 3803 group (Spec.L) has the built-in function
which automatically switches from low to middle-spee d mode by
program.
• Middle-speed mode automatic switch by program
The middle-speed mode can also be automatically switche d by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG
(address 0010
16) to “1” in the condition that the middle-speed
mode automatic switch set bit is “1” while operating in lowspeed mode, the MCU will automatically switch to middle-speed
mode. In this case, the oscillation stabilizing time of the main
clock can be selected by the middle-speed automatic switch wait
time set bit (bit 2) of MISRG (address 0010
16).
b7 b0
Note 1 : When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B
MISRG
(MISRG: address 0010
Oscillation stabilizing time set after STP instruction
released bit
0 : Automatically set “01
Prescaler 12
1 : Automatically set disabled
Middle-speed mode automatic switch set bit
0 : Not set automatically
1 : Au tomatic switching enabled
Middle-speed mode automatic switch wait time set bit
0 : 4.5 to 5.5 machine cycles
1 : 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0 : Invalid
1 : Automatic switch start
Not used (return “0” when read)
(Do not write “1” to this bit)
16) change.
16)
16” to Timer 1, “FF16” to
(1)
(1)
Fig 10. Structure of MISRG
Rev.1.00 Apr 2, 2007 Page 13 of 117
REJ03B0212-0100
3803 Group (Spec.L)
MEMORY
• Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
• RAM
The RAM is used for data storage and for stack area of
subroutine calls and interrupts.
•ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
The reserved ROM area can program/erase in the flash memory
version.
RAM area
RAM size
(bytes)
192
256
384
512
640
768
896
1024
1536
2048
Address
XXXX
00FF
16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
16
RAM
ROM area
ROM size
(bytes)
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
Address
YYYY
F000
16
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
Address
16
ZZZZ
16
F08016
E08016
D08016
C08016
B08016
A08016
ROM
908016
808016
708016
608016
508016
408016
308016
208016
108016
• Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
• Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
• Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
<Note>
Since the contents of RAM are undefined at reset, be sure to set
an initial value before use.
000016
004016
SFR area
Zero page
010016
XXXX16
0FE016
0FEF16
0FF016
0FFF
16
Not used
SFR area (Note 1)
SFR area
Not used
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
FFFF16
Notes1: Only flash memory version has this SFR area.
2: The reserved ROM area can program/erase in
Reserved ROM area
the flash memory version. Note the difference of
the mask version.
Fig 11. Memory map diagram
Rev.1.00 Apr 2, 2007 Page 14 of 117
REJ03B0212-0100
3803 Group (Spec.L)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1 STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator (BRG1)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
Timer Z mode register (TZM)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control regist er (SIO3CON)
UART3 control register (UART3CON)
AD/DA control register (ADCON)
AD conversion register 1 (AD1)
DA1 conversion register (DA1)
DA2 conversion register (DA2)
AD conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
Flash memory control register 0 (FMCR0)
Flash memory control register 1 (FMCR1)
Flash memory control register 2 (FMCR2)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Reserved (Note 1)
Fig 12. Memory map of special function register (SFR)
Rev.1.00 Apr 2, 2007 Page 15 of 117
REJ03B0212-0100
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
Notes1: Do not write any data to these addresses, because these are
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
reserved area.
2: Do not access to the SFR area including nothing.
3803 Group (Spec.L)
I/O PORTS
The I/O ports have direction registers which determine the
input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, and each pin can be set
to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
By setting the port P0 pull-up control register (address 0FF016)
to the port P6 pull-up control register (address 0FF6
16) ports can
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
Table 6 I /O po rt function
Pin Name Input/
Output
0/AN8−P07/AN15 Port P0 Input/output,
P0
P10/INT
41
P11/INT
01
2−P17 (3)
P1
0(LED0)−
P2
7(LED7)
P2
0/DA1
P3
Port P1 External interrupt input Interrupt edge selection register (2)
Port P2
Port P3 D/A converter output AD/DA control register (4)
individual
bits
P31/DA2
2, P33 CMOS compatible
P3
P3
4/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
P4
0/INT40/XCOUT
Port P4 External interrupt input
P41/INT00/XCIN
2/INT1
P4
P43/INT2
4/RXD1
P4
P45/TXD1
P46/SCLK1
P4
7/SRDY1/CNTR2
P5
0/SIN2
Port P5 Serial I/O2 function I/O Serial I/O2 control register (13)
P51/SOUT2
P52/SCLK2
P53/SRDY2
P5
4/CNTR0
P5
5/CNTR1
6/PWM PWM output PWM control register (18)
P5
7/INT3 External interrupt input Interrupt edge selection register (2)
P5
0/AN0−P67/AN7 Port P6 A/D converter input AD/DA control register (1)
P6
I/O Structure Non-Port Function Related SFRs Ref.
CMOS compatible
A/D converter input AD/DA control register (1)
input level
CMOS 3-state
output
input level
N-channel
open-drain output
CMOS compatible
input level
Serial I/O3 function I/O Serial I/O3 control register
UART3 control register
CMOS 3-state
output
Interrupt edge selection register
Sub-clock generating circuit
CPU mode register
External interrupt input Interrupt edge selection register (2)
Serial I/O1 function I/O Serial I/O1 control register
UART1 control register
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O1 control register
Timer Z mode register
Timer X, Y function I/O Timer XY mode register (17)
NOTES:
1. Refer to the applicable sections how to use double-function ports as function I/O ports.
2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC to VSS through the input-stage gate.
No.
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(6)
(7)
(8)
(12)
(14)
(15)
(16)
Rev.1.00 Apr 2, 2007 Page 16 of 117
REJ03B0212-0100
3803 Group (Spec.L)
(1) Ports P0, P6
Data bus
(3) Ports P12 to P17, P2
Data bus
Pull-up control bit
Direction
register
Port latch
A/D converter input
Pull-up control bit
Direction
register
Port latch
Analog input pin
selection bit
(2) Ports P10, P11, P42, P43, P57
Pull-up control bit
Direction
register
Data bus
Port latch
(4) Ports P30, P31
Pull-up control bit
Direction
register
Data bus
Port latch
D/A converter output
Interrupt input
DA1 output enable bit (P30)
2 output enable bit (P31)
DA
(5) Ports P32, P33
Data bus
(7) Ports P35, P45
Serial I/O enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O output
Direction
register
Port latch
Pull-up control bit
P-channel
output
disable bit
(6) Ports P34, P44
Serial I/O enable bit
Receive enable bit
Data bus
(8) Ports P36, P46
Serial I/O synchronous clock
Serial I/O mode selection bit
selection bit
Serial I/O enable bit
Serial I/O enable bit
Data bus
Serial I/O clock output
Pull-up control bit
Direction
register
Port latch
Direction
register
Port latch
Serial I/O external clock input
Serial I/O input
Pull-up control bit
Fig 13. Port block diagram (1)
Rev.1.00 Apr 2, 2007 Page 17 of 117
REJ03B0212-0100
3803 Group (Spec.L)
(9) Port P37
Serial I/O3 mode selection bit
Serial I/O3 enable bit
SRDY3 output enable bit
Direction
register
Data bus
Serial I/O3 ready output
Port latch
(11) Port P41
Port XC switch bit
Direction
register
Data bus
Port latch
Sub-clock generating circuit input
Pull-up control bit
Pull-up control bit
INT00 Interrupt input
Port XC
switch bit
(10) Port P40
Port XC switch bit
Direction
register
Data bus
Port latch
(12) Port P47
Timer Z operating
mode bits
Bit 2
Bit 1
Bit 0
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction
register
Data bus
Port latch
Pull-up control bit
INT40 Interrupt input
Pull-up control bit
Port XC
switch bit
(13) Port P50
Pull-up control bit
Direction
register
Data bus
Port latch
Fig 14. Port block diagram (2)
Serial I/O2 input
Timer output
Serial I/O1 ready output
(14) Port P51
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Data bus
Port latch
Serial I/O2 output
2 interrupt input
CNTR
Pull-up control bit
P-channel
output
disable bit
Rev.1.00 Apr 2, 2007 Page 18 of 117
REJ03B0212-0100
3803 Group (Spec.L)
(15) Port P52
Serial I/O2 synchronous clock
Data bus
selection bit
Serial I/O2 port selection bit
Direction
register
Port latch
Serial I/O2 clock output
(17) Ports P54, P55
Direction
register
Data bus
Port latch
Pulse output mode
Timer output
Pull-up control bit
Serial I/O2 external clock input
Pull-up control bit
CNTR Interrupt input
(16) Port P53
SRDY2 output enable bit
Data bus
(18) Port P56
PWM function enable bit
Data bus
Direction
register
Port latch
Serial I/O2 ready output
Direction
register
Port latch
PWM output
Pull-up control bit
Pull-up control bit
Fig 15. Port block diagram (3)
Rev.1.00 Apr 2, 2007 Page 19 of 117
REJ03B0212-0100
3803 Group (Spec.L)
b7 b0
Port P0 pull-up control register
(PULL0: address 0FF0
0 pull-up control bit
P0
16)
0: No pull-up
1: Pull-up
P0
1 pull-up control bit
0: No pull-up
1: Pull-up
2 pull-up control bit
P0
0: No pull-up
1: Pull-up
P0
3 pull-up control bit
0: No pull-up
1: Pull-up
4 pull-up control bit
P0
0: No pull-up
1: Pull-up
P0
5 pull-up control bit
0: No pull-up
1: Pull-up
6 pull-up control bit
P0
0: No pull-up
1: Pull-up
7 pull-up control bit
P0
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
b7 b0
Port P1 pull-up control register
(PULL1: address 0FF1
0 pull-up control bit
P1
16)
0: No pull-up
1: Pull-up
P1
1 pull-up control bit
0: No pull-up
1: Pull-up
2 pull-up control bit
P1
0: No pull-up
1: Pull-up
P1
3 pull-up control bit
0: No pull-up
1: Pull-up
4 pull-up control bit
P1
0: No pull-up
1: Pull-up
P1
5 pull-up control bit
0: No pull-up
1: Pull-up
P1
6 pull-up control bit
0: No pull-up
1: Pull-up
7 pull-up control bit
P1
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cann ot be
set to the port of which pull-up is selected.
Fig 16. Structure of port pull-up control register (1)
Rev.1.00 Apr 2, 2007 Page 20 of 117
REJ03B0212-0100
3803 Group (Spec.L)
b7 b0
Port P2 pull-up control register
(PULL2: address 0FF2
0 pull-up control bit
P2
16)
0: No pull-up
1: Pull-up
1 pull-up control bit
P2
0: No pull-up
1: Pull-up
P2
2 pull-up control bit
0: No pull-up
1: Pull-up
P2
3 pull-up control bit
0: No pull-up
1: Pull-up
4 pull-up control bit
P2
0: No pull-up
1: Pull-up
P2
5 pull-up control bit
0: No pull-up
1: Pull-up
6 pull-up control bit
P2
0: No pull-up
1: Pull-up
P2
7 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
b7 b0
Port P3 pull-up control register
(PULL3: address 0FF3
0 pull-up control bit
P3
16)
0: No pull-up
1: Pull-up
1 pull-up control bit
P3
0: No pull-up
1: Pull-up
Not used
(return “0” when read)
P3
4 pull-up control bit
0: No pull-up
1: Pull-up
5 pull-up control bit
P3
0: No pull-up
1: Pull-up
P3
6 pull-up control bit
0: No pull-up
1: Pull-up
7 pull-up control bit
P3
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cann ot be
set to the port of which pull-up is selected.
Fig 17. Structure of port pull-up control register (2)
Rev.1.00 Apr 2, 2007 Page 21 of 117
REJ03B0212-0100
3803 Group (Spec.L)
b7 b0
Port P4 pull-up control register
(PULL4: address 0FF4
0 pull-up control bit
P4
16)
0: No pull-up
1: Pull-up
P4
1 pull-up control bit
0: No pull-up
1: Pull-up
2 pull-up control bit
P4
0: No pull-up
1: Pull-up
P4
3 pull-up control bit
0: No pull-up
1: Pull-up
4 pull-up control bit
P4
0: No pull-up
1: Pull-up
P4
5 pull-up control bit
0: No pull-up
1: Pull-up
6 pull-up control bit
P4
0: No pull-up
1: Pull-up
7 pull-up control bit
P4
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
b7 b0
Port P5 pull-up control register
(PULL5: address 0FF5
0 pull-up control bit
P5
16)
0: No pull-up
1: Pull-up
P5
1 pull-up control bit
0: No pull-up
1: Pull-up
2 pull-up control bit
P5
0: No pull-up
1: Pull-up
P5
3 pull-up control bit
0: No pull-up
1: Pull-up
4 pull-up control bit
P5
0: No pull-up
1: Pull-up
P5
5 pull-up control bit
0: No pull-up
1: Pull-up
P5
6 pull-up control bit
0: No pull-up
1: Pull-up
7 pull-up control bit
P5
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cann ot be
set to the port of which pull-up is selected.
Fig 18. Structure of port pull-up control register (3)
Rev.1.00 Apr 2, 2007 Page 22 of 117
REJ03B0212-0100
3803 Group (Spec.L)
b7 b0
Port P6 pull-up control register
(PULL6: address 0FF6
0 pull-up control bit
P6
16)
0: No pull-up
1: Pull-up
1 pull-up control bit
P6
0: No pull-up
1: Pull-up
2 pull-up control bit
P6
0: No pull-up
1: Pull-up
P6
3 pull-up control bit
0: No pull-up
1: Pull-up
P6
4 pull-up control bit
0: No pull-up
1: Pull-up
5 pull-up control bit
P6
0: No pull-up
1: Pull-up
6 pull-up control bit
P6
0: No pull-up
1: Pull-up
7 pull-up control bit
P6
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
Fig 19. Structure of port pull-up control register (4)
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3803 Group (Spec.L)
Termination of unused pins
• Termination of common pins
I/O ports: Select an input port or an output port and follow
each processing method.
In addition, it is recommended that related
registers be overwritten periodically to prevent
malfunctions, etc.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply
current may increase.
Table 7 Termination of unused pins
Pins Termination
P0, P1, P2, P3, P4, P5, P6 • Set to the input mode and connect each to V
REF Connect to VCC or VSS (GND).
V
SS Connect to VCC or VSS (GND).
AV
OUT Open (only when using external clock)
X
• Set to the output mode and open at “L” or “H” output state.
Especially, when expecting low consumption
current (at STP or WIT instruction execution etc.),
pull-up or pull-down input ports to prevent
through current (builtin resistor can be used).
We recommend processing unused pins through a
resistor which can secure I
OH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation
etc.
CC or VSS through a resistor of 1 kΩ to 10 kΩ.
Rev.1.00 Apr 2, 2007 Page 24 of 117
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3803 Group (Spec.L)
INTERRUPTS
The 3803 group (Spec.L) interrupts are vector interrupts with a
fixed priority scheme, and generated by 16 sources among 21
sources: 8 external, 12 internal, and 1 software.
(1)
The interrupt sources, vector addresses
, and interrupt priority
are shown in Table 8.
An interrupt requests is accepted when all of the following
conditions are satisfied:
• Interrupt disable flag ................................ .“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit............. .......................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
Each interrupt except the BRK instruction interrupt has the
and flag.
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 20 shows an interrupt control diagram.
Table 8 Interrupt vector addresses and priority
Vector
Interrupt Source Priority
Addresses
(1)
High Low
(2)
Reset
INT
0 2FFFB16 FFFA16 At detection of either rising or falling
1FFFD16 FFFC16 At reset Non-maskable
Timer Z At timer Z underflow
1 3 FFF916 FFF816 At detection of either rising or falling
INT
Serial I/O1 reception 4 FFF7
Serial I/O1
5 FFF5
16 FFF616 At completion of serial I/O1 data
16 FFF416 At completion of serial I/O1
transmission
Timer X 6 FFF3
Timer Y 7 FFF1
Timer 1 8 FFEF
Timer 2 9 FFED
0 10 FFEB16 FFEA16 At detection of either rising or falling
CNTR
1 11 FFE916 FFE816 At detection of either rising or falling
CNTR
16 FFF216 At timer X underflow
16 FFF016 At timer Y underflow
16 FFEE16 At timer 1 underflow STP release timer underflow
16 FFEC16 At timer 2 underflow
Serial I/O3 reception At completion of serial I/O3 data
Serial I/O2 12 FFE7
16 FFE616 At completion of serial I/O2 data
Timer Z At timer Z underflow
2 13 FFE516 FFE416 At detection of either rising or falling
INT
3 14 FFE316 FFE216 At detection of either rising or falling
INT
4 15 FFE116 FFE016 At detection of either rising or falling
INT
2 At detection of either rising or falling
CNTR
A/D conversion 16 FFDF
16 FFDE16 At completion of A/D conversion
Serial I/O3
transmission
BRK instruction 17 FFDD
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Interrupt Request Generating
Conditions
edge of INT
edge of INT
0 input
1 input
reception
transmission shift or when
transmission buffer is empty
edge of CNTR
edge of CNTR
0 input
1 input
reception
transmission or reception
edge of INT
edge of INT
edge of INT
edge of CNTR
2 input
3 input
4 input
2 input
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Remarks
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
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3803 Group (Spec.L)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Fig 20. Interrupt control diagram
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SET instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remaines set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remaines “1” until the
request is accepted. When the request is accepted, this bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Reset
Interrupt request
• Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt source selection register (0039
1. INT
0 or timer Z
16).
2. CNTR1 or Serial I/O3 reception
3. Serial I/O2 or timer Z
4 or CNTR2
4. INT
5. A/D conversion or serial I/O3 transmission
• External Interrupt Pin Selection
For external interrupts INT
0 and INT4, the INT0, INT4 interrupt
switch bit in the interrupt edge selection register (bit 6 of address
003A16) can be used to select INT00 and INT40 pin input or
INT
01 and INT41 pin input.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of t he
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.1.00 Apr 2, 2007 Page 26 of 117
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3803 Group (Spec.L)
b7 b0
b7 b0
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
0 interrupt edge selection bit
INT
1 interrupt edge selection bit
INT
16)
Not used (returns “0” when read)
INT
2 interrupt edge selection bit
INT
3 interrupt edge selection bit
INT
4 interrupt edge selection bit
INT
0, INT4 interrupt switch bit
00, INT40 interrupt
0 : INT
01, INT41 interrupt
1 : INT
Not used (returns “0” when read)
Interrupt request register 1
(IREQ1 : address 003C
INT
0/Timer Z interrupt request bit
1 interrupt request bit
INT
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
16)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt control register 1
(ICON1 : address 003E
16)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
b7 b0
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0
Interrupt request register 2
(IREQ2 : address 003D
0 interrupt request bit
CNTR
1/Serial I/O3 receive interrupt
CNTR
16)
request bit
Serial I/O2/Timer Z interrupt request bit
INT
2 interrupt request bit
INT
3 interrupt request bit
4/CNTR2 interrupt request bit
INT
AD converter/Serial I/O3 transmit
interrupt request bit
Not used (returns “0” when read)
Interrupt control register 2
(ICON2 : address 003F
16)
0 : Interrupts disabled
1 : Interrupts enabled
b7 b0
INT
0/Timer Z interrupt enable bit
1 interrupt enable bit
INT
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Interrupt source selection register
(INTSEL : address 0039
0/Timer Z interrupt source selection bit
INT
0 interrupt
0 : INT
1 : Timer Z interrupt
Serial I/O2/Timer Z interrupt source selection bit
16)
(Do not write “1” to these bits simultaneously.)
0 : Serial I/O2 interrupt
1 : Timer Z interrupt
Not used (Do not write “1”.)
INT
4/CNTR2 interrupt source selection bit
0 : INT
4 interrupt
1 : CNTR
2 interrupt
Not used (Do not write “1”.)
1/Serial I/O3 receive interrupt source selection bit
CNTR
0 : CNTR
1 interrupt
1 : Serial I/O3 receive interrupt
AD converter/Serial I/O3 transmit interrupt source selection bit
0 : A/D converter interrupt
1 : Serial I/O3 transmit interrupt
CNTR0 interrupt enable bit
CNTR
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT
2 interrupt enable bit
INT
3 interrupt enable bit
4/CNTR2 interrupt enable bit
INT
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
(Do not write “1”.)
0 : Interrupts disabled
1 : Interrupts enabled
1/Serial I/O3 receive interrupt
Fig 21. Structure of interrupt-related registers
Rev.1.00 Apr 2, 2007 Page 27 of 117
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3803 Group (Spec.L)
• Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source
(external interrupt signal input, timer underflow, etc.) and
the corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance
conditions (interrupt request bit, interrupt enable bit, and
interrupt disable flag) and interrupt priority levels for
accepting interrupt requests. When two or more interrupt
requests are generated simultaneo usly, the highest priority
interrupt is accepted. The value of interrupt request bit for
an unaccepted interrupt remains the same and acceptance is
determined at the next interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 22 shows the time up to execution in the interrupt
processing routine, and Figure 23 shows the interrupt sequence.
Figure 24 shows the timing of interrupt request generation,
interrupt request bit, and interrupt request acceptance.
• Interrupt Handling Execution
When interrupt handling is executed, the following operations
are performed automatically.
(1) Once the currently executing instruction is completed, an
interrupt request is accepted.
(2) The contents of the program counters and the processor
status register at this point are pushed onto the stack area in
order from 1 to 3.
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
(3) Concurrently with the push operation, the jump address of
the corresponding interrupt (the start address of the interrupt
processing routine) is transferred from the interrupt vector to
the program counter.
(4) The interrupt request bit for the corresponding interrupt is
set to “0”. Also, the interrupt disable flag is set to “1” and
multiple interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the
registers pushed onto the stack area are popped off in the
order from 3 to 1. Then, the routine that was before running
interrupt processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each
interrupt to execute the interrupt processing routine.
<Notes>
The interrupt request bit may be set to “1” in the following cases.
• When setting the external interrupt active edge
Related registers:Interrupt edge selection register
(address 003A
16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A
16)
• When switching the interrupt sources of an interrupt vector
address where two or more interrupt sources are assigned
Related registers:Interrupt source selection register
(address 0039
16)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt request
generated
Main routine
* When executing DIV instruction
*
0 to 16 cycles
Interrupt request
acceptance
7 to 23 cycles
Interrupt sequence
Stack push and
Vector fetch
7 cycles
Interrupt routine
starts
Interrupt handling
routine
Fig 22. Time up to execution in interrupt routine
Push onto stack
Vector fetch
φ
SYNC
RD
WR
Address bus
Data bus
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
16” or “0116”
SPS : “00
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
S,SPS S-1,SPS S-2,SPS
PC
Not used PCH PCL PS AL AH
BL BH AL,AH
Execute interrupt
routine
Rev.1.00 Apr 2, 2007 Page 28 of 117
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Fig 23. Interrupt sequence
3803 Group (Spec.L)
Push onto stack
Vector fetch
Instruction cycle
IR2T3
Internal clock φ
SYNC
Instruction cycle
12
T1
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
IR1T2
Fig 24. Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Rev.1.00 Apr 2, 2007 Page 29 of 117
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3803 Group (Spec.L)
TIMERS
•8-bit Timers
The 3803 group (Spec.L) has four 8-bit timers: timer 1, timer 2 ,
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “00
16”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt
request bit corresponding to that timer is set to “1”.
• Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B
16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), X
(low-speed mode), X
IN is selected. When these bits are “10”
CIN is selected.
• Prescaler 12
The prescaler 12 counts the output of the timer divider. The
count source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512, 1/1024 of f(XIN) or f(XCIN).
• Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and
periodically set the interrupt request bit.
• Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(X
X count source selection register (address 000E
Y, Z count source selection register (address 000F
CIN). The count source is selected by the timer 12,
16) and the timer
16) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of
f(XIN) or f(XCIN); and f(XCIN).
(1) Timer mode
• Mode selection
This mode can be selected by setting “00” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the t imer XY mode re gister (add ress
0023
16).
• Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 0023
When the timer reaches “00
16”, an underflow occurs at the next
16).
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse Output Mode
• Mode selection
This mode can be selected by setting “01” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the t imer XY mode re gister (add ress
16).
0023
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
not the output of CNTR
0/CNTR1 pin. Regardless of the timer counting or
0/CNTR1 pin is initialized to the level of
specified by their active edge switch bits when writing to the
timer. When the CNTR0 active edge switch bit (bit 2) and the
CNTR
1 active edge switch bit (bit 6) of the timer XY mode
register (address 0023
16) is “0”, the output starts with “H” level.
When it is “1”, the output starts with “L” level.
Switching the CNTR
reverse the output level of the corresponding CNTR
0 or CNTR1 active edge switch bit will
0 or CNTR1
pin.
• Precautions
Set the double-function port of CNTR
4/P55 to output in this mode.
P5
0/CNTR1 pin and port
• Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 0023
16).
(3) Event Counter Mode
• Mode selection
This mode can be selected by setting “10” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the t imer XY mode re gister (add ress
0023
16).
• Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR
valid edge for the count operation depends on the CNTR
edge switch bit (bit 2) or the CNTR
of the timer XY mode register (address 0023
0 or CNTR1 pin. The
0 active
1 active edge switch bit (bit 6)
16). When it is “0”,
the rising edge is valid. When it is “1”, the falling edge is valid.
• Precautions
Set the double-function port of CNTR
P5
4/P55 to input in this mode.
0/CNTR1 pin and port
Rev.1.00 Apr 2, 2007 Page 30 of 117
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