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Rev. 1.02
Revision date: Jul. 01, 2005
www.renesas.com
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•
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
XXX
XXX
(b2)
(b4-b3)
*1
Symbol
XXX
Bit
0
1
-
-
Bit Name
XXX Bit
Nothing is assigned. When write, set to "0",
When read, its content is indeterminate.
Reserved BitSet to "0"
Address
XXX
Function
b1b0
0 0: XXX
0 1: XXX
1 0: Do not set a value
1 1: XXX
After Reset
00h
*5
RW
RW
RW
WO
*2
*3
*4
XXX5
XXX
XXX
XXX Bit
6
7
XXX Bit
Function varies depending on
mode of operation
0: XXX
1: XXX
*1
Blank:Set to “0” or “1” according to the application
0 :Set to “0”
1 :Set to “1”
X :Nothing is assigned
*2
RW : Read and write
RO : Read only
WO: Write only
–: Nothing is assigned
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when
writing to this bit.
• Do not set to this value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
RW
RW
RO
3. M16C Family Documents
The following documents were prepared for the M16C family
DocumentContents
Short SheetHardware overview
Data SheetHardware overview and electrical characteristics
1.4 Product List ..................................................................................................................................................5
2.7 Static Base Register (SB) .......................................................................................................................... 11
2.8 Flag Register (FLG) ................................................................................................................................... 11
2.8.1 Carry Flag (C Flag) ............................................................................................................................ 11
2.8.2 Debug Flag (D Flag) .......................................................................................................................... 11
2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 11
2.8.4 Sign Flag (S Flag) .............................................................................................................................. 11
2.8.5 Register Bank Select Flag (B Flag).................................................................................................... 11
2.8.6 Overflow Flag (O Flag)....................................................................................................................... 11
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 11
2.8.8 Stack Pointer Select Flag (U Flag)..................................................................................................... 11
2.8.10 Reserved Area ................................................................................................................................. 11
7.1 Types of Clock Generating Circuit ............................................................................................................. 31
7.1.1 Main Clock ......................................................................................................................................... 39
7.1.2 Sub Clock........................................................................................................................................... 40
7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 43
7.2.1 CPU Clock and BCLK ........................................................................................................................43
7.2.2 Peripheral Function Clock .................................................................................................................. 43
7.3 Clock Output Function ............................................................................................................................... 43
7.4 Power Control ............................................................................................................................................ 44
7.4.1 Normal Operation Mode..................................................................................................................... 44
9.1 Type of Interrupts ....................................................................................................................................... 56
9.3.1 Special Interrupts ...............................................................................................................................58
9.3.2 Peripheral Function Interrupts............................................................................................................ 58
9.4 Interrupts and Interrupt Vector ...................................................................................................................59
9.5 Interrupt Control .........................................................................................................................................61
9.5.1 I Flag ..................................................................................................................................................63
9.5.2 IR Bit .................................................................................................................................................. 63
9.5.3 ILVL2 to ILVL0 Bits and IPL ............................................................................................................... 63
9.6 INT Interrupt ...............................................................................................................................................69
11.1 Transfer Cycle .......................................................................................................................................... 83
11.1.1 Effect of Source and Destination Addresses .................................................................................... 83
11.1.2 Effect of Software Wait ..................................................................................................................... 83
11.2 DMA Transfer Cycles ................................................................................................................................ 85
12.1 Timer A .....................................................................................................................................................90
15.2 Function ................................................................................................................................................. 191
15.2.1 Resolution Select Function ............................................................................................................ 191
15.2.2 Sample and Hold ........................................................................................................................... 191
15.2.3 Extended Analog Input Pins........................................................................................................... 191
18.4 CAN SFR Registers ...............................................................................................................................203
18.5.1 CAN Reset/Initialization Mode ....................................................................................................... 210
18.5.2 CAN Operation Mode..................................................................................................................... 211
18.5.3 CAN Sleep Mode ........................................................................................................................... 211
18.5.4 CAN Interface Sleep Mode ............................................................................................................ 211
18.5.5 Bus Off State.................................................................................................................................. 212
18.6 Configuration CAN Module System Clock ............................................................................................. 213
18.7 Bit Timing Configuration ......................................................................................................................... 213
18.9 Acceptance Filtering Function and Masking Function............................................................................215
18.10 Acceptance Filter Support Unit (ASU)..................................................................................................216
18.11 Basic CAN Mode ..................................................................................................................................217
18.12 Return from Bus off Function ...............................................................................................................218
18.13 Time Stamp Counter and Time Stamp Function ..................................................................................218
18.16 CAN Interrupt .......................................................................................................................................222
20.3.6 Data Protect Function .................................................................................................................... 252
20.3.7 Status Register (SRD Register) .....................................................................................................252
20.3.8 Full Status Check ........................................................................................................................... 254
A-4
20.4 Standard Serial I/O Mode ...................................................................................................................... 256
20.4.1 ID Code Check Function ................................................................................................................ 256
20.4.2 Example of Circuit Application in Standard Serial I/O Mode .......................................................... 260
22.3 PLL Frequency Synthesizer ...................................................................................................................278
22.4 Power Control ........................................................................................................................................ 279
22.5 Oscillation Stop, Re-oscillation Detection Function ............................................................................... 281
22.7.5 INT Interrupt ................................................................................................................................... 284
22.7.6 Rewrite Interrupt Control Register ................................................................................................. 285
22.10 Thee-Phase Motor Control Timer Function .......................................................................................... 293
22.11 Serial I/O ..............................................................................................................................................294
22.11.1 Clock Synchronous Serial I/O Mode ............................................................................................ 294
22.11.2 Special Modes .............................................................................................................................. 295
22.13 CAN Module ......................................................................................................................................... 299
22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ..... 306
22.17 Mask ROM Version ............................................................................................................................. 307
_____
A-5
22.18 Flash Memory Version .........................................................................................................................308
22.18.1 Functions to Prevent Flash Memory from Rewriting ....................................................................308
CAN0 Wake-up Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
SI/O5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
CAN0 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
INT7 Interrupt Control Register
Timer A3 Interrupt Control Register
INT6 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
SI/O6 Interrupt Control Register
Timer B1 Interrupt Control Register
INT8 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
AddressRegisterSymbolPage
0000h
0001h
0002h
0003h
Processor Mode Register 0
0004h
Processor Mode Register 1
0005h
System Clock Control Register 0
0006h
0007h
The blank areas are reserved.
System Clock Control Register 1
0008h
0009h
Address Match Interrupt Enable Register
000Ah
Protect Register
000Bh
000Ch
Oscillation Stop Detection Register
000Dh
000Eh
Watchdog Timer Start Register
000Fh
Watchdog Timer Control Register
0010h
0011h
Address Match Interrupt Register 0
0012h
0013h
0014h
0015h
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set Counter
Interrupt Cause Select Register 2
Timer B3 Register
Timer B4 Register
Timer B5 Register
SI/O6 Transmit/Receive Register
SI/O6 Control Register
SI/O6 Bit Rate Generator
SI/O3, 4, 5, 6 Transmit/Receive Register
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Cause Select Register 0
Interrupt Cause Select Register 1
SI/O3 Transmit/Receive Register
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
SI/O4 Control Register
SI/O4 Bit Rate Generator
SI/O5 Transmit/Receive Register
SI/O5 Control Register
SI/O5 Bit Rate Generator
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
A/D Control Register 0
A/D Control Register 1
D/A Register 0
D/A Register 1
D/A Control Register
Port P14 Control Register
Pull-Up Control Register 3
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Pull-up Control Register 0
Pull-up Control Register 1
Pull-up Control Register 2
Port Control Register
Operating Ambient Temperature-40 to 85°C
Device ConfigurationCMOS high performance silicon gate
Package128-pin plastic mold LQFP
NOTES:
1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN).
8
Port P0
Port P18Port P2
Internal peripheral functions
Expandable up to 26 channels)
Timer (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits ✕ 2 channels)
NOTES:
1: ROM size depends on microcomputer type.
2: RAM size depends on microcomputer type.
3: Ports P11 to P14 are only in the 128-pin version.
4: 8 bits ✕ 2 channels in the 100-pin version.
Clock synchronous serial I/O
CRC arithmetic circuit (CCITT)
8888
A/D converter
(10 bits ✕ 8 channels
UART or
(3 channels)
(Polynomial: X
R0HR0L
R1HR1L
R2
R3
A0
A1
FB
16+X12+X5
+1)
SB
USP
ISP
INTB
PC
FLG
Port P14
(3)
2
Port P5Port P4Port P3
System clock generating circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits ✕ 4 channels)
CAN module
(1 channel)
(4)
MemoryM16C/60 series CPU core
(1)
ROM
(2)
RAM
Multiplier
Port P13
Port P12
(3)
8
(3)
8
8
Port P6
Port P7
8
Port P8
7
Port P8_5
Port P9
8
Port P10
8
Port P11
(3)
8
Figure 1.1 Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)1. Overview
1.4 Product List
Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.2 shows the type numbers,
memory sizes and packages.
Table 1.3 Product List
As of Jul. 2005
Type No.ROM Capacity RAM Capacity Package TypeRemarks
M306NLFHGP384 K + 4 Kbytes 31 KbytesPLQP0100KB-A Flash memory
M306NNFHGPPLQP0128KB-A version
M306NLFJGP(D) 512 K + 4 Kbytes 31 KbytesPLQP0100KB-A
M306NNFJGPPLQP0128KB-A
M306NLME-XXXGP192 Kbytes16 KbytesPLQP0100KB-A Mask ROM version
M306NNME-XXXGPPLQP0128KB-A
M306NLMG-XXXGP256 Kbytes20 KbytesPLQP0100KB-A
M306NNMG-XXXGPPLQP0128KB-A
(D): Under development
Type No.
M30 6N L M G - XXX GP
Package type:
GP: Package PLQP0100KB-A, PLQP0128KB-A
ROM No.
Omitted on flash memory version
ROM capacity:
E : 192 Kbytes
G: 256 Kbytes
H : 384 Kbytes
J : 512 Kbytes
Figure 1.2 Type No., Memory Size, and Package
Memory type:
M : Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
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M16C/6N Group (M16C/6NL, M16C/6NN)1. Overview
1.5 Pin Configuration
Figures 1.3 and 1.4 show the pin configuration (top view).
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M16C/6N Group (M16C/6NL, M16C/6NN)1. Overview
1.6 Pin Description
Tables 1.4 and 1.5 list the pin descriptions.
Table 1.4 Pin Description (100-pin and 128-pin Versions) (1)
Signal NamePin NameI/O TypeDescription
Power supply
input
Analog power
supply input
Reset input
CNVSS
External data
VCC1, VCC2,
VSS
AVCC, AVSS
_____________
RESET
CNVSS
BYTE
bus width
select input
Main clock
XIN
input
Main clock
XOUT
output
Sub clock
XCIN
input
Sub clock
XCOUT
output
Clock output
______
INT interrupt input
_______
NMI interrupt
input
Key input
CLKOUT
________________
INT0 to INT8
________
NMI
____________
KI0 to KI3
(3)
interrupt input
Timer A
TA0OUT to TA4OUT
I/O
TA0IN to TA4IN
ZP
Timer B
Three-phase motor
control output
Serial I/O
TB0IN to TB5IN
__________
U, U, V, V, W, W
____________________
CTS0 to CTS2
____________________
RTS0 to RTS2
CLK0 to CLK6
(3)
I/O
RXD0 to RXD2
SIN3 to SIN6
(3)
TXD0 to TXD2
SOUT3 to SOUT6
(3)
CLKS1
2
I
C mode
SDA0 to SDA2
SCL0 to SCL2
I/O
I/O
I: Input O: Output I/O: Input/Output
Apply 3.0 to 5.5V to the VCC1 and VCC2 pins and 0V to the
I
VSS pin. The VCC apply condition is that VCC2 = VCC1
Applies the power supply for the A/D converter. Connect the
I
AVCC pin to VCC1. Connect the AVSS pin to VSS.
The microcomputer is in a reset state when applying “L” to the
I
this pin.
Connect this pin to VSS.
I
Connect this pin to VSS.
I
I/O pins for the main clock oscillation circuit. Connect a ceramic
I
resonator or crystal oscillator between XIN and XOUT
To use the external clock, input the clock from XIN and leave
O
XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal
I
oscillator between XCIN and XCOUT
To use the external clock, input the clock from XCIN and leave
O
(2)
.
XCOUT open.
The clock of the same cycle as fC, f8, or f32 is output.
O
Input pins for the INT interrupt.
I
Input pin for the NMI interrupt.
I
Input pins for the key input interrupt.
I
______
_______
These are timer A0 to timer A4 I/O pins.
These are timer A0 to timer A4 input pins.
I
Input pin for the Z-phase.
I
These are timer B0 to timer B5 input pins.
I
These are Three-phase motor control output pins.
O
These are send control input pins.
I
These are receive control output pins.
O
These are transfer clock I/O pins.
These are serial data input pins.
I
These are serial data input pins.
I
These are serial data output pins.
O
These are serial data output pins.
O
This is output pin for transfer clock output from multiple pins function.
O
These are serial data I/O pins.
These are transfer clock I/O pins. (except SCL2 for the
N-channel open drain output.)
(1)
.
(2)
.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. Ask the oscillator maker the oscillation characteristic.
________________
3. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)1. Overview
Table 1.5 Pin Description (100-pin and 128-pin Versions) (2)
Signal NamePin NameI/O TypeDescription
Reference
voltage input
A/D converter
VREF
AN0 to AN7
Applies the reference voltage for the A/D converter and D/A
I
converter.
Analog input pins for the A/D converter.
I
AN0_0 to AN0_7
AN2_0 to AN2_7
_____________
ADTRG
ANEX0
I/O
This is an A/D trigger input pin.
I
This is the extended analog input pin for the A/D converter,
and is the output in external op-amp connection mode.
D/A converter
CAN module
I/O port
ANEX1
DA0, DA1
CRX0
CTX0
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0
to
P4_7
P5_0 to P5_7
I/O
This is the extended analog input pin for the A/D converter.
I
These are the output pins for the D/A converter.
O
This is the input pin for the CAN module.
I
This is the output pin for the CAN module.
O
8-bit I/O ports in CMOS, having a direction register to select
an input or output.
Each pin is set as an input port or output port. An input port
can be set for a pull-up or for no pull-up in 4-bit unit by
program.
(except P7_1 and P9_1 for the N-channel open drain output.)
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_0 to P9_7
P10_0 to P10_7
(1)
(1)
(1)
(1)
I
Input pin for the NMI interrupt.
_______
Input port
P11_0 to P11_7
P12_0 to P12_7
P13_0 to P13_7
P14_0, P14_1
P8_5
Pin states can be read by the P8_5 bit in the P8 register.
I: Input O: Output I/O: Input/Output
NOTE:
1. Ports P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31b15b8 b7b0
R2
R3
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
R2
R3
A0
A1
FB
Data Registers
Address Registers
Frame Base Registers
(1)
(1)
(1)
b19b15
INTBLINTBH
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
PC
b15b0
USP
ISP
SB
b15b0
FLG
b15b0
IPL U I O B S Z D C
NOTE:
1. These registers comprise a register bank. There are two register banks.
b7b8
b0
Interrupt Table Register
b0
Program Counter
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M16C/6N Group (M16C/6NL, M16C/6NN)2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is
set to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
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M16C/6N Group (M16C/6NL, M16C/6NN)3. Memory
3. Memory
Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN). The address space
extends the 1 Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be
used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60 and M16C/20 Series Software Manual.
00000h
00400h
h
h
(program area)
Internal RAM
Reserved area
Internal ROM
(data area)
Reserved area
Internal ROM
Internal RAM
Capacity
16 Kbytes043FF
20 Kbytes
31 Kbytes
Address XXXXX
053FF
07FFF
h
Capacity
h
192 KbytesD0000
h
256 KbytesC0000
h
384 KbytesA0000
512 Kbytes80000
Internal ROM
Address YYYYY
XXXXX
0F000h
0FFFFh
10000h
(1)
h
h
h
h
h
YYYYY
FFFFFh
NOTES:
1. As for the flash memory version, 4-Kbyte space (block A) exists.
2. Shown here is a memory map for the case where the PM13 bit in the PM1 register is "1".
If the PM13 bit is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
3. When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1 Memory Map
SFR
FFE00h
Special page
(1)
FFFDCh
(3)
FFFFFh
vector table
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop and re-oscillation
detection / watchdog timer
DBC
NMI
Reset
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M16C/6N Group (M16C/6NL, M16C/6NN)4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions.
Tables 4.1 to 4.12 list the SFR information.
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Address Match Interrupt Enable Register
Protect Register
Oscillation Stop Detection Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
Address Match Interrupt Register 1
PLL Control Register 0
Processor Mode Register 2
DMA0 Source Pointer
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DMA1 Source Pointer
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
(1)
PM0
PM1
CM0
CM1
AIER
PRCR
CM2
WDTS
WDC
RMAD0
RMAD1
PLC0
PM2
SAR0
DAR0
TCR0
DM0CON
SAR1
DAR1
TCR1
DM1CON
00h
00001000b
01001000b
00100000b
XXXXXX00b
XX000000b
0X000000b
XXh
00XXXXXXb
00h
00h
X0h
00h
00h
X0h
0001X010b
XXX00000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00000X00b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00000X00b
NOTES:
1. The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset.
2. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)4. Special Function Register (SFR)
Table 4.2 SFR Information (2)
AddressRegister
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
CAN0 Wake-up Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
SI/O5 Interrupt Control Register
(1)
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
CAN0 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
INT7 Interrupt Control Register
Timer A3 Interrupt Control Register
INT6 Interrupt Control Register
(1)
(1)
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
SI/O6 Interrupt Control Register
Timer B1 Interrupt Control Register
INT8 Interrupt Control Register
(1)
(1)
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set Counter
SI/O4 Control Register
SI/O4 Bit Rate Generator
SI/O5 Transmit/Receive Register
SI/O5 Control Register
(1)
SI/O5 Bit Rate Generator
(1)
(1)
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
S4C
S4BRG
S5TRR
S5C
S5BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
X: Undefined
000XXXXXb
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
X0000000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
01000000b
XXh
XXXX0000b
00XX0000b
00XX0000b
00XX0000b
00h
00h
XXh
01000000b
XXh
XXh
01000000b
XXh
XXh
01000000b
XXh
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
NOTES:
1. These registers exist only in the 128-pin version.
2. The S5TRF and S6TRF bits in the S3456TRR register are used in the 128-pin version.
3. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)4. Special Function Register (SFR)
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
Port P14 Control Register
Pull-Up Control Register 3
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
(1)
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
(1)
(1)
Port P12 Direction Register
Port P13 Direction Register
Pull-up Control Register 0
Pull-up Control Register 1
Pull-up Control Register 2
Port Control Register
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. Set the PM10 bit to "0" for Mask ROM version.
For the flash memory version, when the PM10 bit is set to "1", addresses 0F000h to 0FFFFh can be used as
internal ROM area. In addition, the PM10 bit is automatically set to "1" while the FMR01 bit in the FMR0 register
is set to "1" (CPU rewrite mode).
3. The PM12 bit is set to "1" by writing a "1" in a program. (writing a "0" has no effect.)
4. Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes.
The PM13 bit is automatically set to "1" when the FMR01 bit is "1" (CPU rewrite mode).
5. When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM
or internal ROM.
6. The access area is changed by the PM13 bit as listed in the table below.
Access areaPM13 = 0PM13 = 1
Internal
RAM
ROM
Up to addresses 00400h to 03FFFh (15 Kbytes)
Up to addresses D0000h to FFFFFh (192 Kbytes)
The entire are is usable
The entire are is usable
RW
RW
RW
RW
RW
RW
RW
Figure 6.2 PM1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)6. Processor Mode
Single-chip mode
00000h
SFR
00400h
XXXXXh
YYYYYh
FFFFFh
NOTES:
1. If the PM13 bit in the PM1 register is set to "0", 15 Kbytes of the internal RAM and 192
Kbytes of the internal ROM can be used.
2. For the mask ROM version, set the PM10 bit in the PM1 register to "0" (block A disable).
Oscillation stop,
re-oscillation detection
interrupt signal
CM21 switch signal
Voltage
control
(VCO)
Internal
1/2
PLL clock
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
System Clock Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
SymbolAddressAfter Reset
(1)
CM00006h 01001000b
Bit NameFunctionBit Symbol
CM00
CM01
CM02
CM03
CM04
CM05
CM06
CM07
Clock Output Function
Select Bit
(Valid only in single-chip
mode)
WAIT Mode Peripheral
Function Clock Stop Bit
XCIN-XCOUT Drive
Capacity Select Bit
Port XC Select Bit
Main Clock Stop Bit
Main Clock Division Select
(7) (10) (12)
Bit 0
System Clock Select
(6) (11)
Bit
(3)
(3)
(5) (6) (7)
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The fC32 clock does not stop. During low-speed or low power dissipation mode, do not set this bit to "1"
(peripheral clock turned off when in wait mode).
3. The CM03 bit is set to "1" (high) while the CM04 bit is set to "0" (I/O port) or when entered to stop mode.
4. To use a sub clock, set this bit to "1". Also make sure ports P8_6 and P8_7 are directed for input, with no
pull-ups.
5. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low
power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped
or not. To stop the main clock, set bits in the following order.
(1) Set the CM07 bit to "1" (sub clock select) or the CM21 bit in the CM2 register to "1" (on-chip oscillator select)
with the sub clock stably oscillating.
(2) Set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (stop).
6. To use the main clock as the clock source for the CPU clock, set bits in the following order.
(1) Set the CM05 bit to "0" (oscillate)
(2) Wait until the main clock oscillation stabilizes.
(3) Set the CM11, CM21 and CM07 bits all to "0".
7. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
8. During external clock input, set the CM05 bit to "0" (oscillate).
9. When the CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor
remains connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.
10. When entering stop mode from high- or medium-speed mode, on-chip oscillator mode or on-chip oscillator
low power dissipation mode, the CM06 bit is set to "1" (divide-by-8 mode).
11. After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub clock oscillates stably
before switching the CM07 bit from "0" to "1" (sub clock).
12. To return from on-chip oscillator mode to high-speed or medium-speed mode, set the CM06 and CM15 bits
both to "1".
clock in wait mode
1 : Stop peripheral function clock
in wait mode
(2)
0 : LOW
1 : HIGH
0 : I/O port P8_6, P8_7
1 : XCIN-XCOUT generation
function
0 : On
1 : Off
(4)
(8) (9)
0 : CM16 and CM17 valid
1 : Division by 8 mode
0 : Main clock, PLL clock,
or on-chip oscillator clock
1 : Sub clock
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 7.2 CM0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
System Clock Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
CM10007h00100000b
(1)
AddressAfter Reset
Bit NameFunctionBit Symbol
CM10
CM11
-
(b4-b2)
CM15
CM16
CM17
All Clock Stop Control
(2) (3)
Bit
System Clock Select Bit 1
Reserved Bit
XIN-XOUT Drive Capacity
Select Bit
Main Clock Division
Select Bit 1
(6)
(7)
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable)
2. If the CM10 bit is "1" (stop mode), XOUT goes "H" and the internal feedback resistor is disconnected.
The XCIN and XCOUT pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL
clock), or the CM20 bit in the CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled),
do not set the CM10 bit to "1".
3. When the PM22 bit in the PM2 register is set to "1" (watchdog timer count source is on-chip oscillator clock),
writing to the CM10 bit has no effect.
4. Effective when the CM07 bit is "0" and the CM21 bit is "0".
5. After setting the PLC07 bit in the PLC0 register to "1" (PLL operation), wait until tsu(PLL) elapses before
setting the CM11 bit to "1" (PLL clock).
6. When entering stop mode from high- or medium-speed mode, or when the CM05 bit is set to "1" (main clock
turned off) in low-speed mode, the CM15 bit is set to "1" (drive capability high).
7. Effective when the CM06 bit is "0" (CM16 and CM17 bits enabled).
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
(4)
1 : PLL clock
(5)
Set to "0"
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
RW
RW
RW
RW
RW
RW
RW
Figure 7.3 CM1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Oscillation Stop Detection Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
CM2000Ch0X000000b
Bit Symbol
CM20
CM21
CM22
CM23
-
(b5-b4)
-
(b6)
CM27
(1)
Address
Bit Name
Oscillation Stop,
Re-Oscillation Detection
Enable Bit
System Clock Select
Bit 2
Oscillation Stop,
Re-Oscillation Detection
Flag
XIN Monitor Flag
(2) (3) (4)
(2) (5) (6) (7) (8) (11)
(9)
After Reset
(10)
Function
0 : Oscillation stop, re-oscillation
detection function disabled
1 : Oscillation stop, re-oscillation
detection function enabled
0 : Main clock or PLL clock
1 : On-chip oscillator clock
(On-chip oscillator oscillating)
0 : Main clock stop, re-oscillation
not detected
1 : Main clock stop, re-oscillation
detected
0 : Main clock oscillating
1 : Main clock turned off
Reserved BitSet to "0"
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
3. Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back
to "1" (enable).
4. Set the CM20 bit to "0" (disable) before setting the CM05 bit in the CM0 register.
5. When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit
is set to "1" (on-chip oscillator clock) if the main clock stop is detected.
6. If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0".
7. Effective when the CM07 bit in the CM0 register is "0".
8. Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL clock),
the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0" under these
conditions, an oscillation stop, re-oscillation detection interrupt request is generated at main clock stop detection;
it is, therefore, necessary to set the CM21 bit to "1" (on-chip oscillator clock) inside the interrupt routine.
9. This bit is set to "1" when the main clock is detected to have stopped and when the main clock is detected to
have restarted oscillating. When this bit changes state from "0" to "1", an oscillation stop and re-oscillation
detection interrupt request is generated. Use this bit in an interrupt routine to discriminate the causes of
interrupts between the oscillation stop and re-oscillation detection interrupt and the watchdog timer interrupt.
This bit is set to "0" by writing "0" in a program. (Writing "1" has no effect. Nor is it set to "0" by an oscillation
stop, re-oscillation detection interrupt request acknowledged.)
If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation
detection interrupt requests are generated.
10. Read the CM23 bit in an oscillation stop and re-oscillation detection interrupt handling routine to determine
the main clock status.
11. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
RW
RW
RW
RW
RO
RW
-
RW
Figure 7.4 CM2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
000
SymbolAddress After Reset
PCLKR025Eh00h
(1)
Bit NameFunctionBit Symbol
Timers A, B, and A/D Clock
PCLK0
Select Bit
(Clock source for the timers A, B,
the dead time timer and A/D)
SI/O Clock Select Bit
PCLK1
-
(b4-b2)
PCLK5
PCLK6
PCLK7
(Clock source for UART0 to UART2,
SI/O3 to SI/O6)
(5)
Reserved Bit
Pin Function Swirch Bit
Software Interrupt Number/SFR
Location Switch Bit
A/D Clock Direct Input Bit
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. If this bit is set to "1", the software interrupt number and SFR location can be changed as follows.
(1) Software interrupt number of the key input interrupt in the vector table can be changed from 14 to 13.
- No.13 is changed from the CAN0 error interrupt to the CAN0 error/key input interrupt.
- No.14 is changed from the A/D/key input interrupt to the A/D interrupt.
(2) Address of the KUPIC register in the SFR can be changed from 004Eh to 004Dh.
- Address 004Dh is changed from the C01ERRIC register to the C01ERRIC/KUPIC register.
- Address 004Eh is changed from the ADIC/KUPIC register to the ADIC register.
3. When this bit = 1, the A/D clock is set to divide-by-1 of fAD mode regardless of whether the PCLK0 bit is set.
4. When the PCLK5 bit and the SM43 bit in the S4C register = 1, the pin function of SI/O4 can be changed as follows.
P8_0/TA4OUT/U/(SIN4)
P7_5/TA2IN/W/(SOUT4)
P7_4/TA2OUT/W/(CLK4)
5. SI/O5 and SI/O6 are only in the 128-pin version.
0 : Divide-by-2 of fAD, f2
1 : fAD, f1
0 : f2SIO
1 : f1SIO
Set to "0"
0: Normal mode
1: Swiching mode
0: Normal mode
1: Swiching mode
0: Normal mode
1: Swiching mode
(4)
(2)
(3)
RW
RW
RW
RW
RW
RW
RW
Figure 7.5 PCLKR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
CAN0 Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
1000
(1)
SymbolAddressAfter Reset
CCLKR025Fh00h
Bit NameFunctionBit Symbol
b2 b1 b0
CCLK0
CCLK1
CAN0 Clock Select Bits
CCLK2
CCLK3
-
(b6-b4)
-
(b7)
CAN0 CPU Interface
Sleep Bit
(3)
Reserved Bit
Reserved Bit
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
2. Set to this bit after setting the C1CTLR register to "0020h", and set only when the Reset bit in the C0CTLR
register = 1 (Reset/Initialization mode).
3. Before setting this bit to "1", set the Sleep bit in the C0CTLR register to "1" (Sleep mode enabled).
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 : Do not set a value
1 1 1 :
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
Set to
"0"
Set to
"1"
RW
RW
RW
RW
RW
RW
RW
Figure 7.6 CCLKR Register
Processor Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
000
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20
bit when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit t "0" (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to "1", it cannot be set to "0" in a program.
4. Setting the PM22 bit to "1" results in the following conditions:
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.
The CM10 bit in the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
(1)
SymbolAddress After Reset
PM2001EhXXX00000b
Bit Symbol
Bit NameFunction
Specifying Wait when
PM20
-
(b1)
PM22
-
(b4-b3)
-
(b7-b5)
Accessing SFR at PLL
Operation
(2)
Reserved BitSet to "0"
WDT Count Source
Protective Bit
(3) (4)
Reserved Bit
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
0 : 2 waits
1 : 1 wait
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used for
the watchdog timer count source
Set to "0"
RW
RW
RW
RW
RW
-
Figure 7.7 PM2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved BitSet to "1"
Reserved BitSet to "0"
0 : PLL Off
Operation Enable Bit
(3)
1 : PLL On
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. This bit can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
cannot be modified.
3. Before setting this bit to "1", set the CM07 bit in the CM0 register to "0" (main clock), set the CM17 to
CM16 bits in the CM1 register to "00b" (main clock undivided mode), and set the CM06 bit in the CM0
register to "0" (CM16 and CM17 bits enable).
RW
RW
RW
RW
-
RW
RW
RW
Figure 7.8 PLC0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
The following describes the clocks generated by the clock generating circuit.
7.1.1 Main Clock
The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for
the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,
which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power
consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 7.9 shows the examples of main clock connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1”
(main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or
on-chip oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resis-
tor remains on, XIN is pulled “H” to XOUT via the feedback resistor. Note, that if an externally generated
clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1” unless the
sub clock is selected as a CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to 7.4 Power Control.
Microcomputer
(Built-in feedback resistor)
XINXOUTXINXOUT
(1)
Rd
CIN
NOTE:
1. Place a damping resistor if required. The resistance will vary depending on the oscillator
and the oscillation drive capacity setting. Use the value recommended by each
oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer
recommends
lacing the resistor externally.
COUT
Figure 7.9 Examples of Main Clock Connection Circuit
Microcomputer
(Built-in feedback resistor)
Open
Externally derived clock
VCC
VSS
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.1.2 Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 7.10 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscilla-
tor circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the
sub clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 7.4 Power Control.
Microcomputer
(Built-in feedback resistor)
XCINXCOUTXCINXCOUT
(1)
RCd
CCIN
NOTE:
1. Place a damping resistor if required. The resistance will vary depending on the oscillator
and the oscillation drive capacity setting. Use the value recommended by each
oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer
recommends placing the resistor externally.
CCOUT
Figure 7.10 Examples of Sub Clock Connection Circuit
Microcomputer
(Built-in feedback resistor)
Open
Externally derived clock
VCC
VSS
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.1.3 On-chip Oscillator Clock
This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock
source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1”
(on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for
the watchdog timer (refer to 10.1 Count Source Protective Mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register
to “1” (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function
clocks, in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register
is “1” (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop,
re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the nec-
essary clock for the microcomputer.
7.1.4 PLL Clock
The PLL clock is generated by a PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait a fixed period of tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 7.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency = f(XIN) ✕ (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register)
(However, PLL clock frequency = 16 MHz, 20 MHz or 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 7.2 shows the example for setting PLL
clock frequencies.
Table 7.2 Example for Setting PLL Clock Frequencies
XIN
(MHz)
8
4
10
5
12
6
4
PLC02
0
0
0
0
0
0
0
PLC01 PLC00
0
1
0
1
0
1
1
1
0
1
0
1
0
1
Multiply
Factor
2
4
2
4
2
4
6
PLL Clock
(1)
(MHz)
16
20
24
NOTE:
1. PLL clock frequency = 16 MHz , 20 MHz or 24 MHz
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to "0" (main clock), the CM17 to CM16
bits to "00b" (main clock undivided), and the CM06 bit to "0"
(CM16 and CM17 bits enabled).
(1)
Set the PLC02 to PLC00 bits (multiplying factor).
(When PLL clock > 16 MHz)
Set the PM20 bit to "0" (2-wait state).
Set the PLC07 bit to "1" (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to "1" (PLL clock for the CPU clock source).
END
NOTE:
1. PLL operation mode can be entered from high-speed mode.
Figure 7.11 Procedure to Use PLL Clock as CPU Clock Source
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.2 CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
7.2.1 CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “00b” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
Note that when entering stop mode from high- or medium-speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).
These are operating clocks for the peripheral functions.
Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator
clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8
and f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the
A/D converter.
The fCAN0 clock is derived from the main clock, PLL clock or on-chip oscillator clock by dividing them by
1 (undivided), 2, 4, 8 or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO, fAD, and fCAN0 clocks are turned off
(1)
.
The fC32 clock is derived from the sub clock, and is used for timers A and B. This clock can be used when
the sub clock is activated.
NOTE
1. fCAN0 clock stops at “H” in CAN0 sleep mode.
7.3 Clock Output Function
The f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits in the CM0 register
to select.
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.4 Power Control
Normal operation mode, wait mode and stop mode are provided as the power consumption control.
All mode states, except wait mode and stop mode, are called normal operation mode in this document.
7.4.1 Normal Operation Mode
Normal operation mode is further classified into seven sub modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low-speed or low power dissipation mode to
on-chip oscillator or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low-speed or low power
dissipation mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock,
change the operation mode to the medium-speed mode (divide-by-8 mode) after the clock was divided by
8 (the CM06 bit in the CM0 register was set to “1”) in the on-chip oscillator mode.
7.4.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is activated, fC32 can be used as
the count source for timers A and B.
7.4.1.2 PLL Operation Mode
The main clock multiplied by 2, 4 or 6 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. PLL
operation mode can be entered from high speed mode. If PLL operation mode is to be changed to wait
or stop mode, first go to high speed mode before changing.
7.4.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is activated, fC32 can be
used as the count source for timers A and B.
7.4.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator turned off), and the
on-chip oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
7.4.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes “1” (divide-by-8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divide-by-8) mode is to be selected when the main clock is operated next.
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.4.1.6 On-chip Oscillator Mode
The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is activated,
fC32 can be used as the count source for timers A and B.
7.4.1.7 On-chip Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be
selected like in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the
peripheral function clocks. If the sub clock is activated, fC32 can be used as the count source for timers
A and B. When the operation mode is returned to the high- and medium-speed modes, set the CM06 bit
in the CM0 register to “1” (divide-by-8 mode).
Table 7.3 lists the setting clock related bit and modes.
Table 7.3 Setting Clock Related Bit and Modes
Modes
CM2 Register
CM21CM11
CM1 RegisterCM0 Register
CM17, CM16
CM07CM06CM05CM04
PLL Operation Mode010 0b000-
High-Speed Mode0000b000-
Medium-
Speed
Mode
divided by 2
divided by 4
divided by 8
divided by 16
0001b000-
0010b000-
00-0 10-
0011b000-
Low-Speed Mode-0-1-01
Low Power00-11
(1)
1
(1)
1
Dissipation Mode
On-chip
Oscillator
Mode
divided by 1
divided by 2
divided by 4
divided by 8
divided by 16
1000b000-
1001b000-
1010b000-
10-0 10-
1011b000-
On-chip Oscillator10(NOTE 2)0(NOTE 2)1Low power Dissipation
Mode
-: “0” or “1”
NOTES:
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and the CM06 bit is set to “1” (divide-by-8 mode) simultaneously.
2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.4.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock and on-chip
oscillator clock all are on, the peripheral functions using these clocks keep operating.
7.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is “1” (peripheral function clocks turned off during wait mode), the f1,
f2, f8, f32, f1SIO, f8SIO, f32SIO, fAD and fCAN0 clocks are turned off when in wait mode, with the power
consumption reduced that much. However, fC32 remains on.
7.4.2.2 Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to set the CM11 bit in the CM1
register to “0” (CPU clock source is the main clock) before going to wait mode. The power consumption
of the chip can be reduced by setting the PLC07 bit in the PLC0 register to “0” (PLL stops).
7.4.2.3 Pin Status During Wait Mode
Table 7.4 lists the pin status during wait mode.
Table 7.4 Pin Status During Wait Mode
PinSingle-Chip Mode
I/O PortsRetains status before wait mode
CLKOUTDoes not stop
When fC selected
When f8, f32 selected
•CM02 bit = 0: Does not stop
•CM02 bit = 1: Retains status before wait mode
7.4.2.4 Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function
interrupt.
______
If the microcomputer is to be moved out of wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b” (interrupt disabled) before executing
the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If
the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions
using the peripheral function clocks stop operating, so that only the peripheral functions clocked by
external signals can be used to exit wait mode.
Table 7.5 lists the interrupts to exit wait mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Table 7.5 Interrupts to Exit Wait Mode
_______
InterruptCM02 Bit = 0CM02 Bit = 1
NMI InterruptCan be usedCan be used
Serial I/O InterruptCan be used when operating withCan be used when operating with
internal or external clockexternal clock
Key Input InterruptCan be usedCan be used
A/D Conversion InterruptCan be used in one-shot mode or- (Do not use)
single sweep mode
Timer A InterruptCan be used in all modesCan be used in event counter mode
Timer B interruptor when the count source is fc32
______
INT InterruptCan be usedCan be used
CAN0 Wake-up InterruptCan be used in CAN sleep modeCan be used in CAN sleep mode
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
(1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used to
exit wait mode.
The ILVL2 to ILVL0 bits in all other interrupt control registers, for peripheral function interrupts not
used to exit wait mode, are set to “000b” (interrupt disable).
(2) Set the I flag to “1”.
(3) Start operating the peripheral functions used to exit wait mode.
When the peripheral function interrupt is used, an interrupt routine is performed as soon as an
interrupt request is acknowledged and the CPU clock is supplied again.
When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the same
clock as the CPU clock executing the WAIT instruction.
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.4.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to VCC is VRAM or more, the internal
RAM is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
7.4.3.1 Entering Stop Mode
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• CAN0 Wake-up interrupt (when CAN sleep mode is selected)
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit in the CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit in the CM2 register to “0” (oscillation stop, re-oscillation
detection function disabled).
Also, if the CM11 bit in the CM1 register is “1” (PLL clock for the CPU clock source), set the CM11 bit to
“0” (main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to “0” (PLL turned off)
before entering stop mode.
7.4.3.2 Pin Status in Stop Mode
Table 7.6 lists the pin status in stop mode.
Table 7.6 Pin Status in Stop Mode
PinSingle-Chip Mode
I/O PortsRetains status before stop mode
CLKOUT“H”
When fC selected
When f8, f32 selected
Retains status before stop mode
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.4.3.3 Exiting Stop Mode
Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.
_______
_______
When the hardware reset or NMI interrupt is used to exit wait mode, set all ILVL2 to ILVL0 bits in the
interrupt control registers for the peripheral function interrupt to “000b” (interrupt disabled) before setting
the CM10 bit in the CM1 register to “1”.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following
settings are completed.
(1) The ILVL2 to ILVL0 bits in the interrupt control registers, for the peripheral function interrupt used to
exit stop mode, must have larger value than that of the RLVL2 to RLVL0 bits.
The ILVL2 to ILVL0 bits in all other interrupt control registers, for the peripheral function interrupts
which are not used to exit stop mode, must be set to “000b” (interrupt disabled).
(2) Set the I flag to “1”.
(3) Start operation of peripheral function being used to exit wait mode.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when
an interrupt request is generated and the CPU clock is supplied again.
_______
When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is
as follows, in accordance with the CPU clock source setting before the microcomputer had entered stop
mode.
• When the sub clock is the CPU clock before entering stop mode:Sub clock
• When the main clock is the CPU clock source before entering stop mode: Main clock divided by 8
• When the on-chip oscillator clock is the CPU clock source before entering stop mode:
On-chip oscillator clock divided by 8
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Figure 7.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.13 shows the state transition in normal operation mode.
Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows
current state and horizontal line show state after transition.
Reset
CPU operation stoppedAll oscillators stopped
Wait Mode
Wait Mode
Wait Mode
Wait Mode
CM07 = 0
CM06 = 1
CM05 = 0
CM11 = 0
CM10 = 1
(5)
CM10 = 1
Stop Mode
(3)
Stop Mode
Stop Mode
Stop Mode
Interrupt
Interrupt
CM10 = 1
CM10 = 1
Interrupt
CM10 = 1
Interrupt
(5)
(5)
(5)
(4)
When
power
dissipation
mode
Medium-Speed Mode
(divided-by-8 mode)
High-Speed Mode,
Medium-Speed Mode
When
low
low-
speed
mode
PLL Operation Mode
Low-Speed Mode,
Low Power Dissipation Mode
On-chip Oscillator Mode,
On-chip Oscillator Dissipation Mode
(NOTES 1, 2)
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
Normal Mode
CM05, CM06, CM07: Bits in CM0 register
CM10, CM11: Bits in CM1 register
NOTES:
Do not go directly from PLL operation mode to wait or stop mode.
1.
2.PLL operation mode can be entered from high-speed mode. Similarly, PLL operation mode can be changed back to high-speed mode.
3.Write to the CM0 and CM1 registers per 16 bits with the CM21 bit in the CM2 register = 0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
4.The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
Figure 7.12 State Transition to Stop Mode and Wait Mode
Rev.1.02 Jul 01, 2005 page 50 of 314
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Main Clock Oscillation
PLL operation mode
: f(PLL)
: f(PLL)
PLC07 = 1
CM11 = 1
PLC07 = 0
CM11 = 0
PLC07 = 1
CM11 = 1
PLC07 = 0
CM11 = 0
CPU clock
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CPU clock
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
PLL operation mode
High-Speed Mode
CPU clock
(6)
CM07 = 0
CM06 = 0
CM17 = 0
(7)
CM16 = 0
High-Speed mode
CPU clock
(6)
CM07 = 0
CM06 = 0
CM17 = 0
(7)
CM16 = 0
: f(XIN)
: f(XIN)
Medium-Speed Mode
(divide by 2)
CPU clock
: f(XIN)/2
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
Medium-Speed Mode
(divide by 2)
CPU clock
: f(XIN)/2
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
Medium-Speed Mode
(divide by 4)
CPU clock
: f(XIN)/4
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
CM04 = 1CM04 = 1 CM04 = 0CM04 = 0
Medium-Speed Mode
(divide by 4)
CPU clock
: f(XIN)/4
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
(3)
CM07 =1
CPU clock: f(XCIN)
CM07 = 0
(1) (9)
CM05 = 1
Low Power Dissipation Mode
CPU clock: f(XCIN)
CM07 = 0
CM06 = 1
CM15 = 1
Medium-Speed Mode
(divide by 8)
CPU clock
: f(XIN)/8
CM07 = 0
CM06 = 1
Medium-Speed Mode
(divide by 8)
CPU clock
: f(XIN)/8
CM07 = 0
CM06 = 1
CM07 = 0
CM05 = 0
Medium-Speed Mode
Medium-Speed Mode
(2) (4)
(divide by 16)
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
(divide by 16)
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
CM21 = 0
CM21 = 1
CM21 = 0
CM21 = 1
CM21 = 0
CM21 = 1
On-chip Oscillator
Mode
CPU clock
(8)
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04 = 1
CM04 = 0
CPU clock
(8)
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
On-chip Oscillator
Mode
Low-Speed ModeLow-Speed Mode
CPU clock: f(XCIN)
CM07 = 0
On-chip Oscillator
Clock Oscillation
On-chip Oscillator
Low Power Dissipation Mode
CPU clock
CM05 = 0
f(Ring)
f(Ring)/2
f(Ring)/4
(1)
CM05 = 1
f(Ring)/8
f(Ring)/16
CM04 = 1
CM04 = 0
CPU clock
CM05 = 0
f(Ring)
f(Ring)/2
f(Ring)/4
(1)
CM05 = 1
f(Ring)/8
f(Ring)/16
On-chip Oscillator
Low Power Dissipation Mode
Sub clock oscillation
CM04, CM05, CM06, CM07: Bits in CM0 register
CM11, CM15, CM16, CM17: Bits in CM1 register
CM20, CM21: Bits in CM2 register
PLC07: Bit in PLC0 register
NOTES:
1. Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait for the main clock oscillation stabilization time.
3. Switch clock after oscillation of sub clock is sufficiently stable.
4. Change the CM17 and CM16 bits before changing the CM06 bit.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit is set to "1" (PLL on). Change the PM20 bit when the PLC07 bit is
set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
PM20 bit to "0" (SFR accessed with two wait states) before setting the PLC07 bit to "1" (PLL operation).
7. PLL operation mode can only be changed to high-speed mode.
8. Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
9. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode)
and the CM15 bit is fixed to "1" (drive capability High).
Figure 7.13 State Transition in Normal Operation Mode
Rev.1.02 Jul 01, 2005 page 51 of 314
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
Table 7.7 Allowed Transition and Setting
State after transition
High-Speed Mode,
Medium-Speed Mode
Low-Speed
(2)
Mode
Low Power
Dissipation Mode
PLL Operation
(2)
Mode
On-chip Oscillator
Mode
Current state
On-chip Oscillator Low
Power Dissipation Mode
Stop Mode
High-Speed Mode,
Medium-Speed
Mode
(NOTE 8) (9)
Low-Speed Low Power
(2)
Mode
(7)
(8) (11)
-
(12)
(14)
(10)
(3)
(4)
-- ----
---
----
(5)
(18)
(18)(18)
PLL Operation
Dissipation Mode
-
Mode (2)Mode
(13)
(1) (6)
On-chip Oscillator
(3)
(15)
---
---
(NOTE 8) (11)
(10)(NOTE 8) (16)
-
(18)
On-chip Oscillator
Low Power
Dissipation Mode
-
(1)
(5)
(18)
(5)
StopWait
ModeMode
(1)
(16)
(1)
(16)
(1)
(16)
(1)
(16)
(1)
(17)
(17)
(17)
(17)
(17)
-
Wait Mode
-: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit = 1 (oscillation stop, reoscillation detection function enabled). Set the CM20 bit to “0” (oscillation
stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this
mode, the on-chip oscillator can be used as peripheral function clock. Sub
clock oscillates and stops in PLL operation mode. In this mode, sub clock
can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed
mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip
oscillator mode to high- or medium-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1”
(division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or sub
clock oscillation turned on or off) are shown in the table below.
(1) CM04=0Sub clock turned off
(2) CM04=1Sub clock oscillating
(
3) CM06=0CPU clock no division
CM17=0mode
CM16=0
(
4) CM06=0
CPU clock division by 2
CM17=0mode
CM16=1
(
5) CM06=0
CPU clock division by 4
CM17=1mode
CM16=0
(
6) CM06=0
CPU clock division by 16
CM17=1mode
CM16=1
(7) CM06=1
(8) CM07=0Main clock, PLL clock
CPU clock division by 8 mode
or on-chip oscillator
clock selected
(9) CM07=1Sub clock selected
(10)
CM05=0Main clock oscillating
(11)
CM05=1Main clock turned off
(12)
PLC07=0Main clock selected
CM11=0
(
13)
PLC07=1PLL clock selected
-
(1)
CM11=1
(14)
CM21=0Main clock or
PLL clock selected
(
15)
CM21=1On-chip oscillator clock
selected
(16)
CM10=1Transition to stop mode
(17)
WAITTransition to wait mode
instruction
(18)
HardwareExit stop mode or wait
interruptmode
CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
CM20, CM21: Bits in CM2 register
PLC07: Bit in PLC0 register
Rev.1.02 Jul 01, 2005 page 52 of 314
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.5 Oscillation Stop and Re-oscillation Detection Function
The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and
re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt request are generated. Which one is to be generated can be selected using the CM27 bit
in the CM2 register.
The oscillation stop and re-oscillation detection function can be enabled or disabled using the CM20 bit in
the CM2 register.
Table 7.8 lists a specification overview of the oscillation stop and re-oscillation detection function.
Table 7.8 Specification Overview of Oscillation Stop and Re-oscillation Detection Function
ItemSpecification
Oscillation Stop Detectable Clock andf(XIN) ≥ 2 MHz
Frequency Bandwidth
Enabling Condition for Oscillation Stop Set CM20 bit to “1” (enable)
and Re-oscillation Detection Function
Operation at Oscillation Stop,•Reset occurs (when CM27 bit = 0)
Re-oscillation Detection•
Oscillation stop, re-oscillation detection interrupt occurs (when the CM27 bit =1)
7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset)
Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR,
5. Reset).
This status is reset with hardware reset. Also, even when re-oscillation is detected, the microcomputer
can be initialized and stopped; it is, however, necessary to avoid such usage (During main clock stop, do
not set the CM20 bit to “1” and the CM27 bit to “0”).
7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop, re-oscillation
detection function enabled), the system is placed in the following state if the main clock comes to a halt:
• Oscillation stop, re-oscillation detection interrupt request is generated.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source for
CPU clock and peripheral functions in place of the main clock.
• CM21 bit = 1 (on-chip oscillator clock is the clock source for CPU clock)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop, re-oscillation detection interrupt request is generated.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from
the stop condition:
• Oscillation stop, re-oscillation detection interrupt request is generated.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
Rev.1.02 Jul 01, 2005 page 53 of 314
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Under development
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M16C/6N Group (M16C/6NL, M16C/6NN)7. Clock Generating Circuit
7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function
• The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt.
If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the
CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for CPU clock and peripheral
function must be switched to the main clock in the program. Figure 7.14 shows the procedure to switch
the clock source from the on-chip oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt request occurrence, the CM22 bit
becomes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are
disabled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscillation
detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating. In this
case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the
peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop and re-oscillation detection function, set the CM02
bit to “0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop and re-oscillation detection function is provided in preparation for main clock
stop due to external factors, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to “0”.
Switch the main clock
NO
CM06 bit: Bit in CM0 register
CM21, CM22, CM 23 bits: Bits in CM2 register
NOTE:
1. If the clock source for CPU clock is to be changed to PLL clock,
set to PLL operation mode after set to high-speed mode.
Determine several times
whether the CM23 bit is set to "0"
(main clock oscillates)
YES
Set the CM06 bit to "1" (divide-by-8)
Set the CM22 bit to "0" (main clock stop,
re-oscillation not detected)
Set the CM21 bit to "0"
(main clock for the CPU clock source)
End
(1)
Figure 7.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock
Rev.1.02 Jul 01, 2005 page 54 of 314
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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)8. Protection
8. Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the
PRCR register.
• The PRC0 bit protects the CM0, CM1, CM2, PLC0, PCLKR and CCLKR registers;
• The PRC1 bit protects the PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD7, PD9, S3C, S4C, S5C and S6C registers
NOTE:
1. The S5C and S6C registers are only in the 128-pin version.
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting
the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the
PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically set to “0” by
writing to any address. They can only be set to “0” in a program.
(1)
.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
NOTES:
1. The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing
to any address, and must therefore be set in a program.
2. The S5C and S6C registers are only in the 128-pin version.
SymbolAddressAfter Reset
PRCR000AhXX000000b
Bit NameBit SymbolFunction
Enable write to CM0, CM1, CM2,
PRC0
PRC1
PRC2
-
(b5-b3)
-
(b7-b6)
Protect Bit 0
Protect Bit 1
Protect Bit 2
Reserved BitSet to "0"
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
2. These interrupts cannot be disabled using the I flag.
3. Use the IFSR07 bit in the IFSR0 register to select.
4. Use the IFSR06 bit in the IFSR0 register to select.
5. Use the IFSR17 bit in the IFSR1 register to select. When using SI/O4, set the IFSR03 bit in the IFSR0 register to “1” (SI/O4) simultaneously.
6. Use the IFSR16 bit in the IFSR1 register to select. When using SI/O3, set the IFSR00 bit in the IFSR0 register to “1” (SI/O3) simultaneously.
7. Use the IFSR01 bit in the IFSR0 register to select.
8. During I2C mode, NACK and ACK interrupts comprise the interrupt source.
9. Bus collision detection: During IE mode, this bus collision detection constitutes the cause of an interrupt.
10. Set the IFSR02 bit in the IFSR0 register to “0”.
11. Use the IFSR04 bit in the IFSR0 register to select.
12. Use the IFSR20 bit in the IFSR2 register to select.
13. Use the IFSR21 bit in the IFSR2 register to select.
14. Use the IFSR05 bit in the IFSR0 register to select.
15. Use the IFSR22 bit in the IFSR2 register to select.
16. If the PCLK6 bit in the PCLKR register is set to “1”, software interrupt number 13 can be changed to CAN0 error or key input
________
(12)
________
(13)
(14)
________
(15)
(2)
During I2C mode, a start condition or a stop condition detection constitutes the cause of an interrupt.
SI/O5 is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to “0” (Timer B5).
________
INT7 is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to “0” (Timer A2).
________
INT6 is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to “0” (Timer A3).
SI/O6 is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to “0” (Timer B0).
________
INT8 is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to “0” (Timer B1).
interupt, and software interrupt number 14 can be changed to A/D interrupt. (The software interrupt number of key input is
changed from 14 to 13.) Use the IFSR26 bit in the IFSR2 register to select when selecting CAN0 error or key input.
Vector Address
Address (L) to Address (H)
+0 to +3 (0000h to 0003h)
+4 to +7 (0004h to 0007h)
+8 to +11 (0008h to 000Bh)
+12 to +15 (000Ch to 000Fh)
+16 to +19 (0010h to 0013h)
+20 to +23 (0014h to 0017h)
+24 to +27 (0018h to 001Bh)
+28 to +31 (001Ch to 001Fh)
+32 to +35 (0020h to 0023h)
+36 to +39 (0024h to 0027h)
+40 to +43 (0028h to 002Bh)
+44 to +47 (002Ch to 002Fh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
+84 to +87 (0054h to 0057h)
+88 to +91 (0058h to 005Bh)
+92 to +95 (005Ch to 005Fh)
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
+104 to +107 (0068h to 006Bh)
+108 to +111 (006Ch to 006Fh)
+112 to +115 (0070h to 0073h)
+116 to +119 (0074h to 0077h)
+120 to +123 (0078h to 007Bh)
+124 to +127 (007Ch to 007Fh)
+128 to +131 (0080h to 0083h)
to
+252 to + 255 (00FCh to 00FFh)
(1)
Software
Interrupt Number
0
M16C/60, M16C/20 Series
Reference
Software Manual
1
18. CAN Module
2
3
4
5
6
______
9.6 INT Interrupt
12. Timers
14. Serial I/O
7
8
9
10
11
14. Serial I/O
______
9.6 INT Interrupt
14. Serial I/O
11. DMAC
12
13
14
15
18. CAN Module
15. A/D Convertor, 9.8 Key Input Interrupt
14. Serial I/O
16
17
18
19
20
21
12. Timers
22
23
24
25
26
27
28
29
12. Timers
______
9.6 INT Interrupt
12. Timers
12. Timers, 14. Serial I/O
12. Timers, 9.6 INT Interrupt
12. Timers
______
9.6 INT Interrupt
______
30
31
32
to
M16C/60, M16C/20 Series
Software Manual
63
Rev.1.02 Jul 01, 2005 page 60 of 314
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the
each interrupt control register.
Figures 9.3 and 9.4 show the interrupt control registers.
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
RW
(4)
-
(b7-b4)
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 22.7 Interrupt.
2. Use the IFSR07 bit in the IFSR0 register to select.
3. Use the IFSR06 bit in the IFSR0 register to select.
4. This bit can only be reset by writing "0" (Do not write "1").
5. Use the IFSR04 bit in the IFSR0 register to select.
The S5IC register is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to "0" (Timer B5).
6. If the PCLK6 bit in the PCLKR register is set to "1", C01ERRIC/KUPIC register can be assigned in an address
004Dh, and the ADIC register can be assigned in an address 004Eh. (SFR location of the KUPIC register is
changed from address 004Eh to address 004Dh.)
7. Use the IFSR05 bit in the IFSR0 register to select.
The S6IC register is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to "0" (Timer B0).
Figure 9.3 Interrupt Control Registers (1)
Rev.1.02 Jul 01, 2005 page 61 of 314
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Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
Interrupt Control Register
(1)
Symbol Address After Reset
0044h
0048h
0049h
005Dh to 005Fh
0057h
0058h
005Bh
0 : Interrupt not requested
1 : Interrupt requested
0 : Selects falling edge
(3) (4) (5)
1 : Selects rising edge
Set to "0"
RW
RW
RW
RW
RW
RW
RW
-
(2)
Figure 9.4 Interrupt Control Registers (2)
Rev.1.02 Jul 01, 2005 page 62 of 314
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
9.5.2 IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set
to “0” (interrupt not requested).
The IR bit can be set to “0” in a program. Note that do not write “1” to this bit.
9.5.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 9.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits
000bLevel 0
Interrupt Priority Level
(Interrupt disabled)
Priority Order
-
001bLevel 1Low
010bLevel 2
011bLevel 3
100bLevel 4
101bLevel 5
110bLevel 6
111bLevel 7High
Table 9.4 Interrupt Priority Levels Enabled by IPL
IPLEnabled Interrupt Priority Levels
000b
001b
010b
011b
100b
101b
110b
111b
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5.4 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt request is generated during execution of an instruction, the processor determines its priority
when the execution of the instruction is completed, and transfers control to the interrupt sequence from
the next cycle. If an interrupt request is generated during execution of either the SMOVB, SMOVF, SSTR
or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers
control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.5 shows time required for
executing the interrupt sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 000000h. Then, the IR bit applicable to the interrupt information is set to “0” (interrupt
requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register
(3) The I, D and U flags in the FLG register become as follows:
• The I flag is set to “0” (interrupt disabled)
• The D flag is set to “0” (single-step interrupt disabled)
• The U flag is set to “0” (ISP selected)
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The temporary register within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
(1)
within the CPU.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
NOTE:
1. Temporary register cannot be modified by users.
123456789 101112131415161718
CPU clock
Address bus
Data bus
RD
(2)
WR
NOTES:
1. The indeterminate state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Address
0000h
Interrupt
information
Indeterminate
Indeterminate
Indeterminate
(1)
(1)
SP-2SP-4vecvec+2
(1)
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Figure 9.5 Time Required for Executing Interrupt Sequence
PC
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5.5 Interrupt Response Time
Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) on Figure 9.6) and a time during which the interrupt
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Vector AddressSP Value16-bit Bus, without Wait8-bit Bus, without Wait
Even
Odd
Even
Odd
Even
Odd
18 cycles
19 cycles
19 cycles
20 cycles
20 cycles
Figure 9.6 Interrupt response time
9.5.6 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.5 is set in the IPL. Table 9.5 shows the IPL values of software and special interrupts when they
are accepted.
Table 9.5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted
Interrupt SourcesValue that is Set to IPL
Oscillation Stop and Re-oscillation Detection, Watchdog Timer, NMI
_________
Software, Address Match, DBC, Single-Step
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5.7 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
MSBLSB
Address
m - 4
-
3
m
m
-
2
m
-
1
m
m + 1
Stack
Content of previous stack
Content of previous stack
[SP]
SP value before
interrupt request
is accepted.
Stack status before interrupt request is acknowledged
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
MSBLSB
Address
m - 4
-
3
m
m
-
2
m
-
1
m
m + 1
Stack status after interrupt request is acknowledged
Stack
PCL
PCM
FLGL
FLGHPCH
Content of previous stack
Content of previous stack
[SP]
New SP value
Figure 9.7 Stack Status Before and After Acceptance of Interrupt Request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the SP (Note) is even, the FLG register
and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 9.8
shows the operation of the saving registers.
(1)
,
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1)SP contains even number(2)SP contains odd number
Address
[SP] - 5 (Odd)
-
4 (Even)
[SP]
[SP]
-
3 (Odd)
[SP]
-
2 (Even)
-
1 (Odd)
[SP]
[SP]
(Even)
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
NOTE:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Stack
PCL
PCM
FLGL
FLGHPCH
Sequence in which order
registers are saved
(2)
Saved simultaneously,
all 16 bits
(1)
Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Address
[SP] - 5 (Even)
-
4 (Odd)
[SP]
[SP]
-
3 (Even)
[SP]
-
2 (Odd)
-
1 (Even)
[SP]
[SP]
(Odd)
Stack
PCL
PCM
FLGL
FLGHPCH
Sequence in which order
registers are saved
(3)
(4)
Saved,8 bits
at a time
(1)
(2)
Finished saving registers
in four operations.
Figure 9.8 Operation of Saving Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.5.8 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5.9 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2
to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.9
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
DBC
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
Peripheral Function
Single Step
Address Match
High
Low
Figure 9.9 Hardware Interrupt Priority
9.5.10 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.10 shows the circuit that judges the interrupt priority level.
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
Priority level of each interrupt
INT1
Timer B2
Timer B0, SI/O6
Timer A3, INT6
Timer A1
UART1 Reception, ACK1
UART0 Reception, ACK0
UART2 Reception, ACK2
Timer B1, INT8
Timer A4
Timer A2, INT7
Timer A0
UART1 Transmission, NACK1
UART0 Transmission, NACK0
A/D Conversion, Key Input
(2)
(2)
INT2
INT0
(2)
(2)
(1)
Level 0
(initial value)
Highest
DMA1
UART2 Bus Collision Detection
SI/O4, INT5
Timer B4, UART1 Bus Collision Detection
INT3
CAN0 Successful Reception
UART2 Transmission, NACK2
CAN0 Error (, Key Input)
DMA0
SI/O3, INT4
Timer B3, UART0 Bus Collision Detection
Timer B5, SI/O5
CAN0 Successful Transmission
CAN0 Wake-up
IPL
I Flag
Address Match
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
DBC
NMI
NOTES:
1. If the PCLK6 bit in the PCLKR register is set to "1", the priority level of key input interrupt can be changed.
2. The SI/O5, SI/O6 and INT6 to INT8 registers are only in the 128-pin version.
(1)
(2)
Priority of peripheral function interrupts
(if priority levels are same)
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
______
9.6 INT Interrupt
_______
INTi interrupt (i = 0 to 8)
the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register.
________________________
INT4 share the interrupt vector and interrupt control register with SI/O3, INT5 share with SI/O4, INT6 share
________________________________
with Timer A3, INT7 share with Timer A2, INT8 share with Timer B1. To use the INT4 to INT8 interrupts
set the each bits as follows.
• To use the INT4 interrupt: Set the IFSR16 bit in the IFSR1 register to “1” (INT4).
• To use the INT5 interrupt: Set the IFSR17 bit in the IFSR1 register to “1” (INT5).
• To use the INT6 interrupt: Set the IFSR21 bit in the IFSR2 register to “1” (INT6).
• To use the INT7 interrupt: Set the IFSR20 bit in the IFSR2 register to “1” (INT7).
________________
________________
________________
________________
________________
• To use the INT8 interrupt: Set the IFSR22 bit in the IFSR2 register to “1” (INT8).
(1)
is triggered by the edges of external inputs. The edge polarity is selected using
(1)
(1)
(1)
(1)
,
After modifying the IFSR16, IFSR17, IFSR20, IFSR21 and IFSR22 bits, set the corresponding IR bit to “0”
(interrupt not requested) before enabling the interrupt.
NOTE:
________________
1. INT6 to INT8 interrupts are only in the 128-pin version.
Figures 9.11 to 9.13 show the IFSR0, IFSR1 and IFSR2 registers.
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
Interrupt Request Cause Select Register 0
b7 b6 b5 b4 b3 b2 b1 b0
011
SymbolAddressAfter Reset
IFSR0 01DEh00h
Bit Symbol
IFSR00
IFSR01
IFSR02
IFSR03
IFSR04
IFSR05
IFSR06
IFSR07
Bit Name
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
(1)
(2)
(3)
(4)
(5)
0 : Do not set a value
1 : SI/O3
0 : A/D conversion
1 : Key input
0 : CAN0 wake-up or error
1 : Do not set a value
0 : Do not set a value
1 : SI/O4
0 : Timer B5
1 : SI/O5
0 : Timer B0
1 : SI/O6
0 : Timer B3
1 :
0 : Timer B4
1 :
Function
UART0 bus collision detection
UART1 bus collision detection
NOTES:
1.When the PCLK6 bit in the PCLKR register = 0, A/D conversion and key input share the vector and
interrupt control register. When using the A/D conversion interrupt, set the IFSR01 bit to "0" (A/D
conversion). When using the key input interrupt, set the IFSR01 bit to "1" (key input).
2.Timer B5 and SI/O5 share the vector and interrupt control register. When using the timer B5 interrupt,
set the IFSR04 bit to "0" (Timer B5). When using SI/O5 interrupt, set the IFSR04 bit to "1" (SI/O5).
The SI/O5 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to "0"
(Timer B5).
3.Timer B0 and SI/O6 share the vector and interrupt control register. When using the timer B0 interrupt,
set the IFSR05 bit to "0" (Timer B0). When using SI/O6 interrupt, set the IFSR05 bit to "1" (SI/O6).
The SI/O6 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to "0"
(Timer B0).
4.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
When using the timer B3 interrupt, set the IFSR06 bit to "0" (Tmer B3).
When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection).
5.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4 interrupt, set the IFSR07 bit to "0" (Timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection).
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 9.11 IFSR0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
Interrupt Request Cause Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
SymbolAddressAfter Reset
IFSR1 01DFh00h
Bit Symbol
IFSR10
IFSR11
IFSR12
IFSR13
IFSR14
IFSR15
IFSR16
IFSR17
INT0 Interrupt Polarity
Switching Bit
INT1 Interrupt Polarity
Switching Bit
INT2 Interrupt Polarity
Switching Bit
INT3 Interrupt Polarity
Switching Bit
INT4 Interrupt Polarity
Switching Bit
INT5 Interrupt Polarity
Switching Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Bit NameFunction
(2)
(4)
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(5)
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT0IC to INT5IC register is set
to "0" (falling edge).
2.SI/O3 and INT4 share the vector and interrupt control register. When using SI/O3 interrupt, set the
IFSR16 bit to "0" (SI/O3). When using INT4 interrupt, set the IFSR16 bit to "1" (INT4).
3.When setting this bit to "0" (SI/O3), make sure the IFSR00 bit in the IFSR0 register is set to "1" (SI/O3)
simultaneously. And, make sure the POL bit in the S3IC register is set to "0" (falling edge).
4.SI/O4 and INT5 share the vector and interrupt control register. When using SI/O4 interrupt, set the
IFSR17 bit to "0" (SI/O4). When using INT5 interrupt, set the IFSR17 bit to "1" (INT5).
5.When setting this bit to "0" (SI/O4), make sure the IFSR03 bit in the IFSR0 register is set to "1" (SI/O4)
simultaneously. And, make sure the POL bit in the S4IC register is set to "0" (falling edge).
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 9.12 IFSR1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
Interrupt Request Cause Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
SymbolAddressAfter Reset
IFSR2 01CFhX0000000b
Bit Symbol
IFSR20
IFSR21
IFSR22
IFSR23
IFSR24
IFSR25
IFSR26
-
(b7)
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
Interrupt Request Cause
Select Bit
INT6 Interrupt Polarity
Switching Bit
INT7 Interrupt Polarity
Switching Bit
INT8 Interrupt Polarity
Switching Bit
Interrupt Request Cause
Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit NameFunction
(2) (6)
(3) (6)
(4) (6)
(1) (6)
(1) (6)
(1) (6)
(5)
0 : Timer A2
1 : INT7
0 : Timer A3
1 : INT6
0 : Timer B1
1 : INT8
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : CAN0 error
1 : key input
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT6IC to INT8IC registers are
set to "0" (falling edge). The INT6IC to INT8IC registers are only in the 128-pin version.
In the 100-pin version, make sure the INT6 to INT8 interrupt polarity switching bitis set to "0" (falling edge).
2.Timer A2 and INT7 share the vector and interrupt control register.
When using the timer A2 interrupt, set the IFSR20 bit to "0" (Timer A2). When using INT7 interrupt,
set the IFSR20 bit to "1" (INT7).
The INT7 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to "0" (Timer A2).
3.Timer A3 and INT6 share the vector and interrupt control register.
When using the timer A3 interrupt, set the IFSR21 bit to "0" (Timer A3). When using INT6 interrupt,
set the IFSR21 bit to "1" (INT6).
The INT6 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to "0" (Timer A3).
4.Timer B1 and INT8 share the vector and interrupt control register.
When using the timer B1 interrupt, set the IFSR22 bit to "0" (Timer B1). When using INT8 interrupt,
set the IFSR22 bit to "1" (INT8).
The INT8 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to "0" (Timer B1).
5.When the PCLK6 bit in the PCLKR register = 1, CAN0 error and key input share the vector and
interrupt control register. When using the CAN0 error interrupt, set the IFSR26 bit to "0" (CAN0 error).
When using the key input interrupt, set the IFSR26 bit to "1" (key input).
6. When using the INT6 to INT8 interrupts, set these bits after settig the PU37 bit in the PUR3 register to "1".
RW
RW
RW
RW
RW
RW
RW
RW
-
Figure 9.13 IFSR2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
______
9.7 NMI Interrupt
____________________
An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI
interrupt is a non-maskable interrupt.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
This pin cannot be used as an input port.
9.8 Key Input Interrupt
Of P10_4 to P10_7, a key input interrupt request is generated when input on any of the P10_4 to P10_7
pins which has had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (input) goes low. Key input
interrupts can be used as a key-on wake up function, the function which gets the microcomputer out of wait
or stop mode. However, if you intend to use the key input interrupt, do not use P10_4 to P10_7 as analog
input ports. Figure 9.14 shows the block diagram of the key input interrupt. Note, however, that while input
on any pin which has had the PD10_4 to PD10_7 bits set to “0” (input mode) is pulled low, inputs on all other
pins of the port are not detected as interrupts.
Pull-up
transistor
KI3
KI2
KI1
KI0
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
PD10_7 bit in PD10 register
PD10_6 bit in
PD10 register
PD10_5 bit in
PD10 register
PD10_4 bit in
PD10 register
PU25 bit in PUR2 register
PD10_7 bit in PD10 register
KUPIC register
Interrupt control circuit
Key input interrupt
request
Figure 9.14 Key Input Interrupt Block Diagram
9.9 CAN0 Wake-up Interrupt
CAN0 wake-up interrupt request is generated when a falling edge is input to CRX0. The CAN0 wake-up
interrupt is enabled only when the PortEn bit = 1 (CTX/CRX function) and Sleep bit = 1 (Sleep mode
enabled) in the C0CTLR register. Figure 9.15 shows the block diagram of the CAN0 wake-up interrupt.
Please note that the wake-up message will be lost.
Sleep bit in C0CTLR register
PortEn bit in C0CTLR register
CRX0
Figure 9.15 CAN0 Wake-up Interrupt Block Diagram
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C01WKIC register
Interrupt control
circuit
CAN0 wake-up
interrupt request
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)9. Interrupt
9.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2
register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag
and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending
on the instruction being executed (refer to 9.5.7 Saving Registers). (The value of the PC that is saved to
the stack area is not the correct return address.) Therefore, follow one of the methods described below to
return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Table 9.7 shows the relationship between address match interrupt sources and associated registers.
Figure 9.16 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 9.6
• 16-bit operation code
• Instruction shown below among 8-bit operation code instructions
For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note
that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
CPU clock
HOLD
Internal RESET signal
("L" active)
CM07 : Bit in CM0 register
WDC7 : Bit in WDC register
PM12 : Bit in PM1 register
PM22 : Bit in PM2 register
Prescaler
Write to WDTS register
CM07 = 0
WDC7 = 0
1/16
CM07 = 0
WDC7 = 1
1/128
CM07 = 1
1/2
On-chip oscillator clock
PM22 = 0
PM22 = 1
Watchdog timer
Set to
"7FFFh"
PM12 = 0
Watchdog timer
Interrupt request
PM12 = 1
Watchdog timer
Reset
Figure 10.1 Watchdog Timer Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)10. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
SymbolAddressAfter Reset
WDC000Fh00XXXXXXb
Bit Name
-
(b4-b0)
-
(b6-b5)
WDC7
Watchdog Timer Start Register
b7b0
NOTE
1. Write to the WDTS register after the watchdog timer interrupt request is generated.
SymbolAddressAfter Reset
WDTS000EhIndeterminate
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFFh" regardless
of whatever value is written.
High-order Bit of Watchdog Timer
Reserved BitSet to "0"
Prescaler Select Bit
(1)
Function
0 : Divided by 16
1 : Divided by 128
FunctionBit Symbol
RW
RO
RW
RW
RW
WO
Figure 10.2 WDC Register and WDTS Register
10.1 Count Source Protective Mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of runaway.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to the PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to the PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
Watchdog timer period =
Watchdog timer count (32768)
on-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.)
• The watchdog timer does not stop when in wait mode or hold state.
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
11. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by the
CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a
cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after
a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the
DMAC specifications. Figures 11.2 to 11.4 show the DMAC related-registers.
Address bus
DMA0 source pointer SAR0
DMA0 destination pointer DAR0
DMA0 transfer counter reload register TCR0
DMA0 transfer counter TCR0
DMA1 transfer counter reload register TCR1
DMA1 transfer counter TCR1
Data bus low-order bits
Data bus high-order bits
NOTE:
1.Pointer is incremented by a DMA request.
Figure 11.1 DMAC Block Diagram
DMA0 forward address pointer
DMA1 source pointer SAR1
DMA1 destination pointer DAR1
DMA1 forward address pointer
DMA latch high-order bits
DMA latch low-order bits
(1)
(1)
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0, 1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag
and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request
can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect
interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register
= 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to 11.4 DMA Request.
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
Table 11.1 DMAC Specifications
ItemSpecification
No. of Channels2 (cycle steal method)
Transfer Memory Space• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
Maximum No. of Bytes Transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
Transfer Address Directionforward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer Mode Single TransferTransfer is completed when the DMAi transfer counter underflows
after reaching the terminal count.
Repeat Transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
DMA Interrupt RequestWhen the DMAi transfer counter underflowed
Generation Timing
DMA Start UpData transfer is initiated each time a DMA request is generated when the
The DMAE bit in the DMAiCON register = 1 (enabled).
DMA Shutdown Single Transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat Transfer When the DMAE bit is set to “0” (disabled)
Reload Timing for ForwardWhen a data transfer is started after setting the DMAE bit to “1” (enabled),
Address Pointer and Transferthe forward address pointer is reloaded with the value of the SARi or the
CounterDARi pointer whichever is specified to be in the forward direction and the
DMAi transfer counter is reloaded with the value of the DMAi transfer
counter reload register.
i = 0, 1
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
DMA0 Request Cause Select Register
b7 b6 b5 b4 b3 b2 b1 b0
SymbolAddressAfter Reset
DM0SL03B8h00h
Bit Name
FunctionBit Symbol
DSEL0
DSEL1
DSEL2
DMA Request Cause
Select Bit
See NOTE 1
DSEL3
-
(b5-b4)
DMS
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
DMA Request Cause
Expansion Select Bit
0 : Basic cause of request
1 : Extended cause of request
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
DSR
Software DMA
Request Bit
The value of this bit when read is "0".
NOTE:
1. The causes of DMA0 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
DMA1 Request Cause Select Register
b7 b6 b5 b4 b3 b2 b1 b0
SymbolAddressAfter Reset
DM1SL03BAh00h
Bit Name
FunctionBit Symbol
DSEL0
DSEL1
DSEL2
DMA Request Cause
Select Bit
See NOTE 1
DSEL3
-
(b5-b4)
DMS
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
DMA Request Cause
Expansion Select Bit
0 : Basic cause of request
1 : Extended cause of request
A DMA request is generated by setting
DSR
Software DMA
Request Bit
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
The value of this bit when read is "0".
NOTE:
1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
1. The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON and DM1CON Registers
SymbolAddressAfter Reset
DM0CON002Ch00000X00b
DM1CON003Ch00000X00b
Bit Name
DMBIT
DMASL
DMAS
DMAE
DSD
DAD
-
(b7-b6)
Transfer Unit Bit
Select Bit
Repeat Transfer Mode
Select Bit
DMA Request Bit
DMA Enable Bit
Source Address Direction
Select Bit
(2)
Destination Address
Direction Select Bit
(2)
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
FunctionBit Symbol
RW
RW
RW
(1)
RW
RW
RW
RW
-
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
DMAi Source Pointer (i = 0, 1)
(b23)
b7
(b19)(b16)
(b15)(b8)
b0 b7b0b3
Set the source address of transfer
(1)
b7b0
Function
SymbolAfter Reset
SAR0
SAR1
Address
0022h to 0020h
0032h to 0030h
Indeterminate
Indeterminate
Setting Range
00000h to FFFFFh
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
NOTE:
1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DSD bit is "1" (forward direction), this register can be written to at any time.
If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Destination Pointer (i = 0, 1)
(b23)
b7
(b19)(b16)
(b15)(b8)
b0 b7b0b3
Set the destination address of transfer
(1)
b7b0
Function
SymbolAfter Reset
DAR0
DAR1
Address
0026h to 0024h
0036h to 0034h
Indeterminate
Indeterminate
Setting Range
00000h to FFFFFh
RW
RW
-
RW
RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTE:
1. If the DAD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DAD bit is "1" (forward direction), this register can be written to at any time.
If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
Figure 11.4 SAR0 and SAR1 Registers, DAR0 and DAR1 Registers, TCR0 and TCR1 Registers
(b8)
b0 b7
b0b7
SymbolAfter Reset
TCR0
TCR1
Function
Set the transfer count minus 1.
The written value is stored in the DMAi transfer counter
reload register, and when the DMAE bit in the DMiCON
register is set to "1" (DMA enabled) or the DMAi transfer
counter underflows when the DMASL bit in the DMiCON
register is "1" (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the DMAi
transfer counter.
When read, the DMAi transfer counter is read.
Address
0029h, 0028h
0039h, 0038h
Setting Range
0000h to FFFFh
Indeterminate
Indeterminate
RW
RW
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
11.1 Transfer Cycle
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)
bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of
transfer. The bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of transfer
begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins
with an odd address, the destination write cycle consists of one more bus cycle than when the destination
address of transfer begins with an even address.
11.1.2 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus
cycles required for that access increases by an amount equal to software wait states.
Figure 11.5 shows the example of the cycles for a source read. For convenience, the destination write cycle
is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating transfer cycles, take into consideration each condition for the
source read and the destination write cycle, respectively. For example, when data is transferred in 16- bit unit
using an 8-bit bus ((2) on Figure 11.5), two source read bus cycles and two destination write bus cycles are
required.
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M16C/6N Group (M16C/6NL, M16C/6NN)11. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Destination
Dummy
cycle
CPU useSource
RD signal
WR signal
Data
bus
CPU useCPU use
Source
Destination
Dummy
cycle
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source + 1
Destination
Dummy
cycle
CPU useSource
RD signal
WR signal
Data
bus
CPU useCPU use
Source
Source + 1
Destination
Dummy
cycle
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
RD signal
WR signal
Data
bus
CPU useCPU use
Source
Destination
Dummy
cycle
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
Source
Source + 1
Source + 1
Destination
Destination
CPU use
Dummy
cycle
Dummy
cycle
CPU useSource
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.5 Transfer Cycles for Source Read
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