REALTEK RTL8308B Datasheet
REALTEK SINGLE CHIP
8-PORT 10/100 ETHERNET
SWITCH CONTROLLER
WITH EMBEDDED MEMORY
RTL8308B
1. Features ................................................................2
2. General Description ............................................3
3. Block Diagram .....................................................4
4. Pin Assignments...................................................5
5. Pin Description ....................................................6
5.1 RMII Interface ................................................6
5.2 Serial EEPROM 24LC02 Interface.................7
5.3 System Pins.....................................................7
5.4 Mode Pins (Reset-Read) .................................7
5.5 LED Pin ..........................................................8
5.6 Test Pin............................................................8
5.7 Power & Ground Pins .....................................8
6. Functional Description........................................9
6.1 Reset................................................................9
6.2 Network Interface ...........................................9
6.2.1 Medium Access Control ..........................9
6.2.2 Auto Negotiation....................................10
6.2.3 MII Interface..........................................10
6.2.4 RMII interface .......................................10
6.2.5 Illegal Frames ........................................11
6.3 EEPROM Interface .......................................11
6.4 Serial Management Interface MDC/MDIO ..12
6.5 Reversible PHYAD Order.............................13
6.6 Address Search and Learning .......................13
6.7 Address Hashing Mode.................................14
6.8 Address Direct Mapping Mode.....................14
6.9 Frame Filtering..............................................14
RTL8308B
6.10 Back off Algorithm .................................... 15
6.11 Inter-Frame Gap ......................................... 15
6.12 Buffer Management.................................... 15
6.13 Buffer Manager .......................................... 15
6.14 Data Reception ........................................... 16
6.15 Data Forwarding......................................... 16
6.16 Flow Control .............................................. 17
6.17 Cut Through ............................................... 17
6.18 Broadcast Storm Filtering Control ............. 17
6.19 Loop Detection........................................... 18
6.20 Head-Of-Line Blocking.............................. 18
6.21 24LC02 Interface........................................ 18
6.22 24LC02 Device Operation ......................... 19
6.23 Testing ........................................................ 21
6.23.1 External SRAM Test ........................... 21
6.23.2 Production Testing .............................. 21
6.23.3 Loopback............................................. 21
7. 24LC02 Serial EEPROM Format ................... 22
8. Electrical Characteristics................................. 23
8.1 Temperature Limit Ratings........................... 23
8.2 DC Characteristics........................................ 23
8.3 AC Characteristics........................................ 23
8.3.1 Reset and Clock Timing........................ 23
8.3.2 RMII Timing ......................................... 24
8.3.3 PHY Management Timing .................... 25
8.3.4 Serial EEPROM 24LC02 Timing ......... 26
9. Mechanical Information................................... 27
2002/01/23 Rev. 2.0
1
1. Features
Supports eight 10/100Mbps Ethernet ports with
RMII interface
Provides forwarding of non-blocking and
non-head-of-line-blocking
2M bit DRAM built in as a packet storage buffer
Page based buffer management to efficiently
utilize the internal packet buffer
Ultra low power consumption with less than
160mA at 3.3V operating voltage
Embedded 8K entry look-up table and 128 entry
CAM
Supports address hashing or direct mapping for
look-up table
RTL8308B
Broadcast storm control
Flow control fully supported:
Half-duplex: back pressure
Full-duplex: IEEE 802.3X
Auto-negotiated Full-duplex flow control by
writing the ability via MDIO to external PHY
Supports Store-and-forward and cut-through
operation
Provides an LED display to indicate network loop
existence
Reversible PHYAD order for diverse PHY usage
3.3V 24LC02 interface
128-entry CAM is used to eliminate the hash
collision issues
Supports full and half duplex operation
Link, speed and duplex status are auto-detected via
MDIO
Optional EEPROM 24LC02 for Loop detect
configuration
128-pin PQFP, 0.35 um, 3.3V CMOS technology
2002/01/23 Rev. 2.0
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RTL8308B
2. General Description
The RTL8308B is a 128-pin, low cost and ultra low power consumption 8-port 10/100M Ethernet switch controller.
It is integrated both with a 2M bit embedded DRAM, as a packet buffer, and an 8K entry address table. The
RTL8308B supports the reduced MII (RMII) interface. Only a single 50MHz oscillator is needed and the
EEPROM is optional, which can save BOM costs. In addition, the RTL8308B provides an LED display to indicate
a network loop existence.
The RTL8308B provides eight 10/100 Mbps RMII Ethernet ports. Each port can operate in 10 Mbps or 100 Mbps
data rate, and in full or half duplex mode. Speed, duplex, link status and flow control can be acquired by
periodically polling the status of the PHY devices via MDIO.
The address look-up table consists of an 8K entry hash table and a 128 entry CAM. The RTL8308B uses the
address hashing algorithm or direct mapping method to search destination MAC addresses from and record source
MAC addresses to the hash table. Data received from the MAC interface is stored in the external memory buffer.
The RTL8308B supports IEEE 802.3x full duplex flow control and half duplex back pressure control. The ability
of IEEE 802.3x flow control is auto-negotiated by writing the flow control ability via MDIO. The reversible
PHYAD order feature is provided to connect diverse external PHY devices for PCB layout.
The RTL8308B provides a loop detect LED for visual diagnostics when detecting the network loop. The Broadcast
storm filtering function is provided for unusual broadcast storm traffic.
The RTL8308B supports non-blocking 148800 packets/second wire speed forwarding rate and a special design to
resolve the head-of-line-blocking problem. The RTL8308B uses a 2-wire 24LC02 interface to access the external
serial EEPROM, which is not required. Only one 50MHz OSC is needed.
50MHz
OSC
Quad-PHY
Realtek
RTL8308B
Quad-PHY
10/100 Mbps x 8
EEPROM2
4LC02
2002/01/23 Rev. 2.0
Example of 8-port Switch System diagram
3
RTL8308B
3. Block Diagram
8 Ports
RMII RMII PHY EEPROM LED
Management I/F I/F
10/100 10/100 I/F
MAC MAC
EDORAM Packet
I/F Buffer
RXFIFO TXFIFO Space
FIFOs,
QUEUE, DMA
Flow Engine
TX Start Addr. Control,
Queue
RX/TX Page
RX/TX F.P.P. F.P.P. Pointer
FIFOs FIFO Switching Space
Logic
Flow control
8K-entry
Address
Table
Address-Lookup
128-entry Address CAM Engine
F.P.P Buffer
FIFO Manager
2002/01/23 Rev. 2.0
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4. Pin Assignments
84 NC
85 VCC
86 TXE[G]
87 TXD0[G]
88 TXD1[G]
89 CRSDV[G]
90 RXD0[G]
91 RXD1[G]
92 TXE[H]
93 TXD0[H]
94 TXD1[H]
95 VCC
96 CRSDVH]
97 RXD0[H]
98 RXD1[H]
99 NC
100 NC
101 GND
102 NC
103 VCC
104 NC
105 GND
106 TEST
107 ENBKPRS
108 EnBrdCtrl
109 VCC
110 NC
111 GND
112 ENFCTRL
113 VCC
114 NC
115 GND
116 GND
117 ENCUTHR
118 NC
119 SYSCLK
120 NC
121 SCLK
122 SDA
123 NC
124 VCC
125 NC
126 GND
127 NC
128 VCC
RTL8308B
RTL8308B
83 GND
82 GND
81 RXD1[F]
80 RXD0[F]
79 CRSDV[F]
78 TXD1[F]
77 TXD0[F]
76 TXE[F]
75 GND
74 RXD1[E]
73 RXD0[E]
72 CRSDV[E]
71 GND
70 TXD1[E]
69 TXD0[E]
68 TXE[E]
67 NC
66 VCC
65 NC
64 GND
63 RXD1[D]
62 RXD0[D]
61 CRSDV[D]
60 TXD1[D]
59 TXD0[D]
58 TXE[D]
57 NC
56 NC
55 NC
54 LOOPLED#
53 RST#
52 VCC
51 VCC
50 NC
49 GND
48 GND
47 REFCLK
46 NC
45 NC
44 MDIO
43 MDC
42 NC
41 NC
40 VCC
39 VCC
1 NC
2 NC
3 NC
4 NC
5 NC
6 GND
7 TXE[A]
8 TXD0[A]
9 TXD1[A]
10 CRSDV[A]
11 RXD0[A]
12 RXD1[A]
13 TXE[B]
14 TXD0[B]
15 TXD1[B]
16 VCC
17 VCC
18 CRSDV[B]
19 RXD0[B]
38 NC
37 NC
36 GND
35 GND
34 GND
33 NC
32 NC
31 RXD1[C]
30 GND
29 RXD0[C]
28 CRSDV[C]
26 TXD0[C]
25 VCC
24 TXE[C]
27 TXD1[C]
23 GND
22 GND
21 GND
20 RXD1[B]
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5. Pin Description
5.1 RMII Interface
Symbol Type Pin No Description
TXEN[A:H] O 7,13,24,58,
68,76,86,92
TXD[0:1][A],
TXD[0:1][B],
TXD[0:1][C],
TXD[0:1][D],
TXD[0:1][E],
TXD[0:1][F],
TXD[0:1][G],
TXD[0:1][H]
CRSDV[A:H] I 10,18,28,61,
RXD[0:1][A],
RXD[0:1][B],
RXD[0:1][C],
RXD[0:1][D],
RXD[0:1][E],
RXD[0:1][F],
RXD[0:1][G],
RXD[0:1][H]
REFCLK I 47
MDC O 43
O 8,9,14,15,26,
27,59,60,69,
70,77,78,87,88,
93,94
72,79,89,96
I 11,12,19,20,
29,31,62,63,
73,74,80,81,
90,91,97,98
Transmit Enable: The RTL8308B asserts high to indicate
that valid di-bit data for transmission is presented on
TXD[1:0], and transitions synchronously with respect to
REFCLK.. TXEN will be asserted synchronously with the first
nibble of the preamble and will remain asserted while all
di-bits that are to be transmitted are presented. TXEN will be
negated prior to the first REFCLK rising edge following the
final di-bit of a frame.
Transmit Data [1:0]: TXD[1:0] will transition synchronously
with respect to REFCLK. When TXEN is asserted, TXD[1:0]
is accepted for transmission by the PHY. TXD[1:0] will be
‘00’ to indicate idle when TXEN is deasserted.
CRSDV Signals: This signal will be asserted high by the
PHY when the medium is active. It is asserted asynchronously
on detection of carrier due to criteria defined in the IEEE
802.3 specifications. Loss of carrier will result in the
deassertion of this pin, synchronous to the cycle of the
reference clock, REFCLK.
Receive Data [1:0]: The RTL8308B captures the receive data
on the rising edge of REFCLK when CRSDV is asserted high.
When CRSDV is asserted high, RXD[1:0] will transition
synchronously to REFCLK. For each clock period in which
CRSDV is asserted, RXD[1:0] transfers two bits of recovered
data from the PHY. Values other than ‘00’ on RXD[1:0] while
RXDV as recovered from CRSDV is deasserted will be
ignored by the controller. Upon assertion of CRSDV, the PHY
will ensure that RXD[1:0] = ‘00’ until proper receive
decoding takes place.
RMII Reference Clock Input: A continuous clock which
provides the timing reference for CRS_DV, RXD[1:0],
TX_EN, and TXD[1:0]. It is a 50 MHz OSC, 3.3V, +/-50ppm,
0˚ C ~70˚ C, symmetry 45%~55%, Rise/Fall time 5ns, supply
40mA.
It is assumed that the PHY uses REFCLK as the network clock so no
buffering is required on the transmit data path.
Management Data Clock: A clock source common to all
ports, generated by the controller with a frequency of 312.5
kHz, it is used to synchronize the MII data stream (MDIO) for
transferring MII management data between the controller and
transceivers.
RTL8308B
This pin is Tri-state at reset.
2002/01/23 Rev. 2.0
6
RTL8308B
MDIO I/O 44
Management Data Input/Output: This pin is used during the
MII setup process. The whole setup sequence will set Register
4h, address 16-20 of the PHY to 05E1h, REGISTER 0h to
value 1200h. It also advertises 100/10 full duplex with pause
capability & enables auto-negotiation. Sending after reset
signal release about 1.6ms.
This pin is Tri-state at reset.
5.2 Serial EEPROM 24LC02 Interface
Symbol Type Pin No Description
SCLK O 121 Serial Clock: Internally pulled high, this pin is used to enable
data transfers from the EEPROM to the controller.
This output is used to clock the serial EEPROM inputs and
outputs. It operates at 1.6us or 625KHz.
SDA I/O 122 Serial Data Input/Output: Internally pulled high, this pin is
used to obtain configuration data from the external serial
EEPROM after reset. The data is synchronized by MDC.
5.3 System Pins
Symbol Type Pin No Description
RST# I 53 Reset: Active low to a known reset state. After power-on reset
(low to high), the configuration modes from Mode Pins are
determined. Then, the contents of the serial EEPROM is
auto-loaded into and the RTL8308B, which begins to access
the management data of PHY devices.
SYSCLK I 119 System clock input: The same 50 MHz clock as REFCLK is
used.
5.4 Mode Pins (Reset-Read)
Symbol Type Pin No Description
ENBrdCtrl I 108 Enable Broadcast Storm Control detection: Pulled low
internally by default, Broadcast Storm Control is disabled. When
pulled high upon reset, Broadcast Storm Control is enabled.
ENCUTHR I 117 Enable Cut-through: Pulled low internally by default,
cut-through is disabled. When pulled high upon reset,
Cut-through is enabled.
ENBKPRS I 107 Enable Half duplex back pressure function: Pulled low
internally by default, back pressure is enabled. When pulled
low upon reset, back pressure is disabled.
ENFCTRL I 112 Enable Full Duplex Flow Control: Pulled low internally by
default, Flow Control is enabled. The flow control ability will
write to management register 4 of PHY device one and only
one time after power-on reset, for advertising. When pulled
low upon reset, the flow control function will be disabled.
2002/01/23 Rev. 2.0
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RTL8308B
5.5 LED Pin
Symbol Type Pin No Description
LOOPLED# O 54 Loop Detected LED: Low active. This pin, asserted low
indicates that a network loop is detected.
DTESTOUT O 56 DRAM Test Output: For internal test use.
5.6 Test Pin
Symbol Type Pin No Description
CTEST I 106 Test pin: For internal use. Must be tied to ground for normal
operation.
5.7 Power & Ground Pins
Symbol Type Pin No Description
GND P 6,21,22,23,30,
34,35,36,48,
49,64,71,75,82,
83,101,105,111,
115,116,126
VCC P 16,17,25,39,40,
51,52,66,85,95,
103,109,113,
124,128
Please specify Analog/Digital Power & GND.
2002/01/23 Rev. 2.0
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RTL8308B
6. Functional Description
6.1 Reset
The minimum required reset duration is 1us. After power on reset, the RTL8308B will determine some features
from the ENFCTRL, ENBKPRS and ENBrdCtrl pins, auto-load the content of 24LC02 serial EEPROM, and write
abilities to connected PHY management registers via MDC/MDIO. It is recommended that the RTL8308B and
connected PHYs use the same reset signal source. The PHY reset must be completed before the RTL8308B.
6.2 Network Interface
The RTL8308B has 8 10/100 Mbps Ethernet ports (port 0 to port 7) with Reduced MII (R-MII) interfaces. It has 1
MII port in addition to the 4 R-MII ports for 10/100Mbps Ethernet transceivers. Note that an MII interface operates
at 25MHz in 100Mbps transmission and 2.5MHz for 10Mbps transmission. Reduced MII interfaces use the same
50MHz clock rate for both 10Mbps and 100Mbps operation. All MII interfaces support auto-negotiation for
transmission speeds, duplex modes and flow control options.
6.2.1 Medium Access Control
The RTL8308B implements the IEEE Std 802.3 binary exponential back-off algorithm and conforms to IEEE
802.3 specifications.
Data received from the PHY is interpreted and assembled into the external buffer memory by the RTL8308B flow
controller. Interpretation involves detection and removal of the preamble, extraction of the address and FCS
verification. Also included is a jabber-detection timer to detect frames of greater than maximum length being
received on the network. In 10Mbps mode, the raw data received from the PHY as input is converted to 8-bit width
before further processing. Similarly, in 100Mbps mode, the data received from the external PHY is converted to
8-bit data width in the shifter. The data is then synchronized to the internal clock of the RTL8308B. Once the
100Mbps data has been deserialized it is handled no differently than the 10Mbps data. By default, the RTL8308B
detects collision signals by itself, which makes normal and reverse MII connection easy. Because signals from the
PHY are not synchronized with internal clocks of the RTL8308B, the Rx FIFO adjusts timing differences between
external & internal clocks. Data transmission requires more processing and data handling than data reception. This
is due to the overhead of implementing collision detection and recovery logic. Data entering from the FIFO is
serialized for transmission at the transmit clock rate (this also requires the data to be synchronized to the transmit
clock rate from the internal clock). Because the transmit clock is asynchronous with the internal clock of the
RTL8308B, the Tx FIFO is needed for timing adjustment. The Tx FIFO will also transmit JAM pattern and
PAUSE frames to work with the flow control mechanism in the Flow Control Unit.
The Tx FIFO handles the output of data to the PHY devices, and several error states are handled. If a collision is
detected in half duplex mode, the state machine jams the output. If the collision was late (after the first 64-bytes
have been transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While
operating in full duplex mode, both carrier-sense (CRS) mode and collision-sensing modes are disabled. Internally,
frame data only is removed from buffer memory once it has been successfully transmitted without collision (for the
half-duplex ports). Transmission recovery also is handled in this state machine. If a collision is detected, frame
recovery and retransmission are initiated.
2002/01/23 Rev. 2.0
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