Rainbow Electronics W27L010 User Manual

Preliminary W27L010

CE

OE

PGM

128K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode. The W27L010 provides an electrical chip erase function.

FEATURES

• High speed access time:

90/120 nS (max.)

• Read operating current: 10 mA (max.)

• Erase/Programming operating current:

30 mA (max.)

• Standby current: 20 µA (max.)

• Low voltage power supply range, 3.0V to 3.6V

PIN CONFIGURATIONS

Vpp

1

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A 1 2

5 6

7 8 9 10 11 12

1

13

4

Q1Q

32-pin DIP

8 9 10 11 12 13 14

15 16

A

1

6

5

4 3 2 1

32-pin PLCC

151

6

G

2

N D

V p p

1 7

Q 3

V c c

3 2

18192

Q 4

A4 A3

A2 A1 A0 Q0

Q1 Q2

GND

A7 A6 A5 A4 A3 A2 A1 A0 Q0

Vcc

32

PGM

31

NC

30

A14

29

A13

28

A8

27 26

A9 A11

25 24

OE

23

A10

22

CE Q7

21 20

Q6

19

Q5

18

Q4

17

Q3

/ P

N

G

C

M

3

1

0

Q

5

6

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23 22

CE Q7

21

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 32-pin 600 mil DIP, 450

mil SOP and PLCC

BLOCK DIAGRAM

PGM

CE OE

A16

V

GND

V

A0

. .

CC

PP

CONTROL

DECODER

OUTPUT BUFFER

CORE

ARRAY

Q0

. .

Q7

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A16

Q0−Q7

VPP Program/Erase Supply Voltage VCC Power Supply

GND Ground

NC No Connection

Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable

Publication Release Date: February 1999

- 1 - Revision A1

Preliminary W27L010

CE

PGM

OE

PGM

CE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at the outputs.

is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing

the erase operation.

low starts

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low,

high.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing

low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low,

low, and

high.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the

, the W27L010 may have common inputs.

- 2 -

Preliminary W27L010

PGM

CE

OE

PGM

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE and

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (Isb), active current levels (Icc),

and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

.

TABLE OF OPERATING MODES

VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL

MODE PINS

A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X X VCC VCC DOUT Output Disable VIL VIH X X X VCC VCC High Z Standby (TTL) VIH X X X X VCC VCC High Z Standby (CMOS) Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCP VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VPE VCP VPE FF (Hex) Erase Verify VIL VIL VIH X X VCP VPE DOUT Erase Inhibit VIH X X X X VCP VPE High Z Product Identifier-

Manufacturer Product Identifier-device VIL VIL X VIH VHH VCC VCC 01 (Hex)

VCC ±0.3V

VIL VIL X VIL VHH VCC VCC DA (Hex)

X X X X VCC VCC High Z

Publication Release Date: February 1999

- 3 - Revision A1

DC CHARACTERISTICS

CE

PGM

CE

PGM

Absolute Maximum Ratings

PARAMETER RATING UNIT

Preliminary W27L010

Operation Temperature 0 to +70 Storage Temperature -65 to +125 Voltage on all Pins with Respect to Ground Except VCC, VPP

and A9 Pins Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to VCC +0.5 V

°C °C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VCC Erase Current ICP

VPP Erase Current IPP

= VIL, OE = VIH,

= VIL, A9 = VHH

= VIL, OE = VIH,

- - 30 mA

µA

= VIL, A9 = VHH Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Erase Voltage VID - 13.25 14.0 14.25 V VPP Erase Voltage VPE - 13.25 14.0 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 4 -

Preliminary W27L010

Input

CAPACITANCE

(VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 0.8V/2.0V Output Load CL = 100 pF,

IOH/IOL = -0.1 mA/1.6 mA

AC Test Load and Waveforms

D

OUT

2.4V

0.45V

+1.3V

(IN914)

3.3K ohm

100 pF (Including Jig and Scope)

Output

Test Points Test Points

2.0V

0.8V

2.0V

0.8V

Publication Release Date: February 1999

- 5 - Revision A1

Preliminary W27L010

CE

OE

READ OPERATION DC CHARACTERISTICS

(VCC = 3.0V to 3.6V, TA = 0 to 70° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VCC -5 - 5 Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 Standby VCC Current

(TTL input) Standby VCC Current

(CMOS input) VCC Operating Current ICC

VPP Operating Current IPP VPP = VCC - - 10 Input Low Voltage VIL - -0.3 - 0.6 V Input High Voltage VIH - 2.0 - VCC +0.5 V Output Low Voltage VOL IOL = 1.6 mA - - 0.4 V Output High Voltage VOH IOH = -0.1 mA 2.4 - - V VPP Operating Voltage VPP - VCC -0.7 - VCC V

ISB

ISB1

= VIH

= VCC ±0.2V

= VIL IOUT = 0 mA f = 5 MHz

- - 200

- - 20

- - 10 mA

READ OPERATION AC CHARACTERISTICS

(VCC = 3.0V to 3.6V, TA = 0 to 70° C)

µA µA µA

µA

PARAMETER SYM. W27L010-90 W27L010-12 UNIT

MAX. MIN. MAX. MIN.

Read Cycle Time TRC 90 - 120 - nS Chip Enable Access Time TCE - 90 - 120 nS Address Access Time TACC - 90 - 120 nS Output Enable Access Time TOE - 40 - 55 nS

High to High-Z Output

Output Hold from Address Change TOH 0 - 0 - nS

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TDF - 25 - 30 nS

- 6 -

Preliminary W27L010

CE

PGM

CE

PGM

OE

PGM

CE

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH - - 10 VCC Program Current ICP

VPP Program Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V

= VIL, OE = VIH,

= VIL

= VIL, OE = VIH,

= VIL

- - 30 mA

µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - Address Setup Time TAS 2.0 - Data Setup Time TDS 2.0 - -

Program Pulse Width Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time after Address Hold Time (Erase) TAHE 2.0 - -

Setup Time

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

High

TPWP 95 100 105 TPWE 95 100 105 mS

TOES 2.0 - TOEV - - 150 nS TDFP 0 - 130 nS TAH 0 - -

TCES 2.0 - -

µS µS µS µS

µS µS

µS µS µS

Publication Release Date: February 1999

- 7 - Revision A1

TIMING WAVEFORMS

V

AC Read Waveform

V

IH

Address Address Valid

V

IL

V

IH

CE

IL

IH

OE

V

IL

Outputs

High Z

Preliminary W27L010

T

CE

T

DF

T

ACC

OE

Valid Output

T

OH

High Z

Erase Waveform

V

Data

V

PGM

CE

OE

PP

14.0V

5.0V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Address

Read

Manufacturer

SID

A9 = 12.0V

Others = V

A0 = V

T

AS

DA 01

T

CE

T

OE

IL

T

OE

Device

SID

IL

A0=V

Others=V

T

AS

Read

Chip Erase

A9 = 14.0V

Others = V

IH

IL

T

AS

AHC

Data All One

T

DS

Erase Verify

IL

Address Stable

T

DFP

D

T

DH

OUT

Address

Stable

D

OUT

T

AH

Blank Check Read Verify

Address Stable

T

ACC

D

OUT

3.3V

T

VPS

T

OES

T

CES

PWE

2.7V

T

OE

T

OEV

- 8 -

Timing Waveforms, Continued

Programming Waveform

Preliminary W27L010

Address

Data

V

PGM

Program

V

IH

T

AS

T

VPS

T

Address Stable

Data In Stable

T

DS

CES

T

PWP

V

IL

12.0V

PP

5.0V

V

IH

CE

V

IL

V

IH

OE

V

IL

V

IH

V

IL

Program

Verify

Address Stable

T

DFP

D

OUT

T

DH

T

OES

T

AH

T

OEV

D

OUT

Read Verify

Address Valid

T

ACC

T

OE

D

OUT

5V

Publication Release Date: February 1999

- 9 - Revision A1

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V Vpp = 12V

X = 0

Preliminary W27L010

Increment Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

No

Verify

One Byte

Last Address?

Vcc = 3.3V

Vpp = 3.3V

Compare All Bytes to

Original Data

µ

Yes

No

Pass

Yes

Fail

Verify

One Byte

Pass

Fail

Pass Device

Pass

Fail Device

- 10 -

SMART ERASE ALGORITHM

Preliminary W27L010

Start

X = 0

Vcc = 5V Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Vcc = 2.7V Vpp = 2.7V

Erase Verify

No

Last Address?

Vcc = 3.3V Vpp = 3.3V

IL

Pass

Yes

No

Fail

X = 20?

Yes

Compare All Bytes to

FFs (HEX)

Pass

Pass Device

Fail

Fail Device

Publication Release Date: February 1999

- 11 - Revision A1

ORDERING INFORMATION

1. Dimensions D Max. & S include mold flash or tie bar burrs.

6. General appearance spec. should be based on final visual

4. Dimension B1 does not include dambar protrusion/intrusion.

Preliminary W27L010

PART NO. ACCESS

TIME

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

W27L010-90 90 8 20 600 mil DIP W27L010-12 120 8 20 600 mil DIP W27L010S-90 90 8 20 450 mil SOP W27L010S-12 120 8 20 450 mil SOP W27L010P-90 90 8 20 32-pin PLCC W27L010P-12 120 8 20 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in Inches

Symbol

A A A

B

32

1E

1

S

2

A

L

D

B

1

e

1

B

17

16

A

1

Base Plane

Seating Plane

a

E

e

A

B

c

D E E

e

L

e

S

Notes:

c

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line.

5. Controlling dimension: Inches. inspection spec.

Nom.

Min.

0.010

1

0.155

0.150

2

0.016

0.018

0.050 1.27

1

0.010

0.008

1.650 1.660

0.6000.590

0.545

0.550

1

0.120

0.130

0 15

a

0.630 16.00

0.650

A

Dimension in mm

Nom.

Max. Max.

Min.

0.210 5.33

0.25

0.160

3.81

3.94

0.41

14.99

13.84

0.20

2.29 2.54 2.790.090 0.100

3.05

0.46

0.25

41.91 42.16

15.49

15.24

14.10

13.97

3.30

17.02

16.51

0.022

0.0540.048

0.014

0.610

0.555

0.110

0.140

0.670

0.085

4.06

0.56

1.371.22

0.36

3.56 150

2.16

- 12 -

Package Dimensions, Continued

E

32-pin SO Wide Body

Preliminary W27L010

32

1

Seating Plane

32-Lead PLCC

5

13

14

L

θ

Seating Plane

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

17

E H

E

e

1

θ

L

16

b

D

Detail F

e

1

c

A

A2

S

e

y

H

E

1

324

b b

1

EG

e

A

1

30

29

D

H D

21

20

2A

A

1

A

y

See Detail F

G D

c

L

E

Notes:

A

0.004

A

1

0.106

0.101

A

2

0.014

b c D E

e H L L S

y

θ

Notes:

1. Dimensions D Max. & S include mold flash or tie bar burrs.

2. Dimension b does not include dambar protrusion/intrusion.

3. Dimensions D & E include mold mismatch and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based on final visual inspection spec.

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

1

A A

2

1

b

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

G

D

0.390

E

G

0.585

H

D

0.485

E

H

0.075

L y

θ

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual inspection sepc.

0.016

0.0080.006

0.805

0.440

0.5560.546 14.3814.1213.87

E

0.023

0.031

0.047

0.055

E

0

0.140

0.1150.105 0.110

0.0320.026

0.028

0.022

0.018

0.014

0.010

0.553

0.550

0.453

0.450

0.050

0.530

0.510

0.430

0.410

0.595

0.590

0.495

0.490

0.095

0.090

0.004

°

0

10

Dimension in mm

0.118 3.00

0.10

0.111

2.57

0.36

0.020

0.012 0.31

0.817

11.18

0.4500.445

1.12 1.27 1.420.044 0.050 0.056

0.556

0.039

0.58 0.79 0.99

0.063 1.19

0.004 10

0

.

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.12 1.420.044 0.056

1.27

12.95

12.45

9.91

10.41

14.86

14.99

12.32

12.45

1.91 2.29

°

0

20.45

11.30

2.69

2.82

0.41

0.51

0.200.15

20.75

11.43

1.40

1.60

0.910.036

0.10 10

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

Publication Release Date: February 1999

- 13 - Revision A1

Preliminary W27L010

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Feb. 1999 Initial Issued

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

- 14 -

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2730 Orchard Parkway, San Jose, CA 95134, U.S.A.

TEL: 1-408-9436666 FAX: 1-408-9436668