Rainbow Electronics W27L010 User Manual
Preliminary W27L010
CE
OE
PGM
128K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in
normal read mode. The W27L010 provides an electrical chip erase function.
FEATURES
• High speed access time:
90/120 nS (max.)
• Read operating current: 10 mA (max.)
• Erase/Programming operating current:
30 mA (max.)
• Standby current: 20 µA (max.)
• Low voltage power supply range, 3.0V to 3.6V
PIN CONFIGURATIONS
Vpp
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A
1
2
5
6
7
8
9
10
11
12
1
13
4
Q1Q
32-pin DIP
8
9
10
11
12
13
14
15
16
A
A
1
1
6
5
4 3 2 1
32-pin PLCC
151
6
G
2
N
D
V
p
p
1
7
Q
3
V
c
c
3
2
18192
Q
4
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Vcc
32
PGM
31
NC
30
A14
29
A13
28
A8
27
26
A9
A11
25
24
OE
23
A10
22
CE
Q7
21
20
Q6
19
Q5
18
Q4
17
Q3
/
P
N
G
C
M
3
3
1
0
0
Q
Q
5
6
A14
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
22
CE
Q7
21
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 32-pin 600 mil DIP, 450
mil SOP and PLCC
BLOCK DIAGRAM
PGM
CE
OE
A16
V
GND
V
A0
.
.
CC
PP
CONTROL
DECODER
OUTPUT
BUFFER
CORE
ARRAY
Q0
.
.
Q7
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A16
Q0−Q7
VPP Program/Erase Supply Voltage
VCC Power Supply
GND Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Publication Release Date: February 1999
- 1 - Revision A1
Preliminary W27L010
CE
PGM
PGM
PGM
OE
PGM
CE
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at
the outputs.
is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (TACC) is equal to the delay from CE to output
(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 =
VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing
the erase operation.
low starts
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low,
high.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP
(12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input
pins equal the desired inputs. Pulsing
low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low,
low, and
high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the
, the W27L010 may have common inputs.
- 2 -
Preliminary W27L010
PGM
CE
OE
PGM
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby
mode, all outputs are in a high impedance state, independent of OE and
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (Isb), active current levels (Icc),
and transient current peaks produced by the falling and rising edges of CE. Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1 µF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
.
TABLE OF OPERATING MODES
VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL
MODE PINS
A0 A9 VCC VPP OUTPUTS
Read VIL VIL X X X VCC VCC DOUT
Output Disable VIL VIH X X X VCC VCC High Z
Standby (TTL) VIH X X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH VIL X X VCP VPP DIN
Program Verify VIL VIL VIH X X VCP VPP DOUT
Program Inhibit VIH X X X X VCP VPP High Z
Erase VIL VIH VIL VIL VPE VCP VPE FF (Hex)
Erase Verify VIL VIL VIH X X VCP VPE DOUT
Erase Inhibit VIH X X X X VCP VPE High Z
Product Identifier-
Manufacturer
Product Identifier-device VIL VIL X VIH VHH VCC VCC 01 (Hex)
VCC ±0.3V
VIL VIL X VIL VHH VCC VCC DA (Hex)
X X X X VCC VCC High Z
Publication Release Date: February 1999
- 3 - Revision A1
DC CHARACTERISTICS
CE
PGM
CE
PGM
Absolute Maximum Ratings
PARAMETER RATING UNIT
Preliminary W27L010
Operation Temperature 0 to +70
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except VCC, VPP
and A9 Pins
Voltage on VCC Pin with Respect to Ground -0.5 to +7 V
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
-0.5 to VCC +0.5 V
°C
°C
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)
PARAMETER SYM. CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
= VIL, OE = VIH,
= VIL, A9 = VHH
= VIL, OE = VIH,
- - 30 mA
- - 30 mA
µA
= VIL, A9 = VHH
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Erase Voltage VID - 13.25 14.0 14.25 V
VPP Erase Voltage VPE - 13.25 14.0 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
- 4 -
Preliminary W27L010
Input
CAPACITANCE
(VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance COUT VOUT = 0V 12 pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0.45V to 2.4V
Input Rise and Fall Times 10 nS
Input and Output Timing Reference Level 0.8V/2.0V
Output Load CL = 100 pF,
IOH/IOL = -0.1 mA/1.6 mA
AC Test Load and Waveforms
D
OUT
2.4V
0.45V
+1.3V
(IN914)
3.3K ohm
100 pF (Including Jig and Scope)
Output
Test Points Test Points
2.0V
0.8V
2.0V
0.8V
Publication Release Date: February 1999
- 5 - Revision A1
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