W27E512
64K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.
FEATURES
• High speed access time:
45/55/70/90/120/150 nS (max.)
• Read operating current: 30 mA (max.)
• Erase/Programming operating current
30 mA (max.)
• Standby current: 1 mA (max.)
• Single 5V power supply
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 28-pin 600 mil DIP, 330 mil
SOP, TSOP and 32-pin PLCC
PIN CONFIGURATIONS
1
OE/Vpp
V
A15
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A11
A13
A14
A12
A15
2
A12
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
Q0
12
Q1
13
Q2
14
GND
A7N
4321
5
6
7
8
9
10
11
12
1
13
4
Q1Q
1
2
A9
3
A8
4
5
6
CC
7
8
9
10
A7
11
A6
12
A5
13
A4
14
A3
A
1
2
151
2
28-pin
A
1
5
32-pin
PLCC
6
G
N
D
DIP
C
1
7
N
C
28-pin
TSOP
A
V
1
C
4
C
3
3
2
1
18192
Q
3Q4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
1
3
3
029
0
Q
5
BLOCK DIAGRAM
V
CC
A14
A13
A8
A9
A11
OE/Vpp
A10
CE
Q7
Q6
Q5
Q4
Q3
OE/V
CE
A0
A15
V
CONTROL
PP
.
DECODER
.
CC
OUTPUT
BUFFER
CORE
ARRAY
GND
A8
A9
28
A11
27
NC
26
25
OE/Vpp
A10
24
23
CE
22
Q7
21
Q6
A10
28
27
CE
26
Q7
25
Q6
24
Q5
Q4
23
Q3
22
GND
21
Q2
20
19
Q1
18
Q0
17
A0
16
A1
15
A2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A15
Q0−Q7
CE
PP
OE
/V
VCC Power Supply
GND Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable, Program/Erase
Supply Voltage
Q0
Q7
.
.
Publication Release Date: November 1999
- 1 - Revision A8
W27E512
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E512 has two control functions, both of which produce data
CE
at the outputs.
is for power control and chip select. OE/V
to the output pins. When addresses are stable, the address access time (T
CE
from
if T
to output (T
ACC
and TCE timings are met.
CE
), and data are available at the outputs TOE after the falling edge of
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when
OE
is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0
/V
PP
low, and all other address pins low and data input pins high. Pulsing
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V
CE
V
(3.75V),
CE
low, and OE/V
PP
low.
PP
controls the output buffer to gate data
ACC
) is equal to the delay
OE
CE
low starts the erase
/V
CC
PP
=
,
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
OE
way to change cell data from "1" to "0." The program mode is entered when
(12V), V
desired inputs. Pulsing
CC
= VCP (5V), the address pins equal the desired addresses, and the input pins equal the
CE
low starts the programming operation.
/VPP is raised to VPP
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
PP
program margin. This mode will be entered after the program operation if
OE
/V
low and
CE
low.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
CE
data. When
CE
and OE/V
high, erasing or programming of non-target chips is inhibited, so that except for the
PP
pins, the W27E512 may have common inputs.
- 2 -
W27E512
CE OE
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby
PP
OE
/V
mode, all outputs are in a high impedance state, independent of
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E512 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I
transient current peaks produced by the falling and rising edges of
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its V
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
CC
and GND. This high frequency, low inherent-
.
SB
), active current levels (ICC), and
CE
. Transient current magnitudes
TABLE OF OPERATING MODES
(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)
MODE PINS
Read VIL V
Output Disable VIL V
/VPP
IL
X X VCC D
IH
X X VCC High Z
A0 A9 V
Standby (TTL) VIH X X X VCC High Z
Standby (CMOS)
V
CC
±0.3V
Program VIL V
Program Verify VIL V
Program Inhibit VIH V
Erase VIL V
Erase Verify VIL V
Erase Inhibit VIH V
Product Identifier-manufacturer VIL V
Product Identifier-device VIL V
X X X V
PP
X X VCP DIN
IL
X X VCC D
PP
X X VCP High Z
PE
V
IL
X X 3.75 D
PE
X X VCE High Z
IL
V
IL
V
IL
VPE VCE DIH
IL
VHH VCC DA (Hex)
IH
VHH VCC 08 (Hex)
Publication Release Date: November 1999
- 3 - Revision A8
CC OUTPUTS
OUT
CC
High Z
OUT
OUT
W27E512
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except
PP,
OE
/V
A9 and VCC Pins
Voltage on OE/VPP Pin with Respect to Ground
-0.5 to V
CC
+0.5 V
-0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage VCC Pin with Respect to Ground -0.5 to +7 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±10%)
°
C
°
C
PARAMETER SYM.
Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
µ
CE
V
CE
OE
PE
= V
= V
/V
IL,
IL,
PP
= VPE
OE
/V
PP
=
- - 30 mA
- - 30 mA
A
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - -
A9 Erase Voltage VID - 13.25 14 14.25 V
VPP Erase Voltage VPE - 13.25 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V
VCC Supply Voltage
VCE - 3.5 3.75 4.0 V
(Erase Verify)
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
- 4 -
CAPACITANCE
(VCC = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
Input Capacitance CIN V
Output Capacitance C
OUT
V
IN
= 0V 6 pF
OUT
= 0V 12 pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
45/55/70 nS 90/120/150 nS
Input Pulse Levels 0 to 3.0V 0.45V to 2.4V
Input Rise and Fall Times 5 nS 10 nS
Input and Output Timing Reference Level 1.5V/1.5V 0.8V/2.0V
Output Load CL = 30 pF,
OH/IOL
I
AC Test Load and Waveforms
= -0.4 mA/2.1 mA
L
= 100 pF,
C
OH/IOL
I
= -0.4 mA/2.1 mA
W27E512
+1.3V
(IN914)
3.3K ohm
D
OUT
100 pF for 90/120/150 nS (Including Jig and Scope
30 pF for 45/55/70 nS (Including Jig and Scope)
For 90/120/150 nS
For 45/70 nS
2.4V
0.45V
3.0V
Input
Input
0V
Test Points Test Points
Test Point Test Point
1.5V
2.0V
0.8V
Output
2.0V
0.8V
Output
1.5V
Publication Release Date: November 1999
- 5 - Revision A8
W27E512
READ OPERATION DC CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0 to 70° C)
PARAMETER SYM. CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
Input Load Current ILI VIN = 0V to VCC -5 - 5
Output Leakage
ILO V
OUT
= 0V to VCC -10 - 10
Current
Standby VCC Current
ISB
CE
= V
IH
- - 1.0 mA
(TTL input)
Standby VCC Current
SB1
I
CE
= V
CC
±0.2V
- 5 100
(CMOS input)
VCC Operating Current ICC
CE
OUT
I
IL
= V
= 0 mA
- - 30 mA
f = 5 MHz
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - V
CC
+0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
µ
A
µ
A
µ
A
READ OPERATION AC CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0 to 70° C)
PARAMETER SYM. W27E512-45 W27E512-55 W27E512-70 W27E512-90 W27E512-12 W27E512-15 UNIT
Read Cycle Time TRC 45 - 55 - 70 - 90 - 120 - 150 - nS
Chip Enable
Access Time
Address Access
Time
Output Enable
Access Time
OE /V PP High to
High-Z Output
Output Hold from
Address Change
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
TCE - 45 - 55 - 70 - 90 - 120 - 150 nS
ACC
T
- 45 - 55 - 70 - 90 - 120 - 150 nS
TOE - 20 - 25 - 30 - 40 - 55 - 60 nS
DF
- 20 - 20 - 30 - 30 - 30 - 50 nS
T
TOH 0 - 0 - 0 - 0 - 0 - 0 - nS
- 6 -
DC PROGRAMMING CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 25° C ±5° C)
PARAMETER SYM. CONDITIONS LIMITS UNIT
Input Load Current
VCC Program Current I
VPP Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Silicon I.D. Voltage
VPP Program Voltage
VCC Supply Voltage (Program)
ILI
CP
IPP
VIL
VIH
VOL IOL
VOH IOH
VID
VPP
VCP
VIN = VIL or VIH -10 - 10
CE
= VIL,
OE
PP
/V
= VPP
CE
IL
= V
,
OE
/VPP = VPP
- -0.3 - 0.8 V
- 2.4 - 5.5 V
= 2.1 mA - - 0.45 V
= -0.4 mA 2.4 - - V
- 11.5 12.0 12.5 V
- 11.75 12.0 12.25 V
- 4.5 5.0 5.5 V
MIN. TYP. MAX.
- - 30 mA
- - 30 mA
AC PROGRAMMING/ERASE CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 25° C ±5° C)
PARAMETER SYM. LIMITS UNIT
PRT
OE
/VPP Pulse Rise Time
Data Setup Time T
CE
Program Pulse Width
CE
Erase Pulse Width
Data Hold Time T
PP
OE
/V
Setup Time
OE
PP
/V
Hold Time
CE
Data Valid from
Data Valid from Address Change T
CE
High to Output High Z
Address Setup Time T
Address Hold Time T
Address Hold Time after CE High (Erase)
PP
OE
OE
/V
PP
/V
Valid after
Recovery Time
CE
High
Address Access Time during Erase Verify (VCC = 3.75V) T
Output Enable Access Time during Erase Verify (VCC = 3.75V) T
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
T
T
T
T
T
T
T
T
T
T
DS
PWP
PWE
DH
OES
OEH
DV1
DV2
DFP
AS
AH
AHC
VS
VR
ACV
OEV
MIN. TYP. MAX.
50 - - nS
2.0 - -
95 100 105
95 100 105 mS
2.0 - -
2.0 - -
2.0 - -
25 - 1
25 - 1
0 - 130 nS
2.0 - -
0 - -
2.0 - -
2.0 - -
2.0 - -
- - 250 nS
- - 150 nS
W27E512
µA
µS
µS
S
µ
µS
µS
µS
µS
µS
µS
µS
µS
µS
Publication Release Date: November 1999
- 7 - Revision A8
TIMING WAVEFORMS
d
AC Read Waveform
IH
V
Address
IL
V
VIH
CE
IL
V
IH
V
OE/Vpp
IL
V
Outputs
Erase Waveform
High Z
Address Valid
CE
T
TACC
TOE
Valid Output
W27E512
DF
T
OH
T
High Z
Read
Read
Address
Data
Vcc
OE/Vpp
CE
V
IH
V
IL
5V
14.0V
V
IH
V
IL
V
IH
V
IL
Company
SID
A9=12.0V
Others=V
A0=V
IL
T
ACC
DA 08
T
OE
T
CE T
Others=V
T
ACC
T
OE
Device
SID
IL
A0=V
Address Valid
T
ACV
=250 nS
T
OEV
Erase Verify
Address Valid Address Valid Address Vali
T
=250 nS
ACV
D
OUT
=150 nS
Always=V
3.75V
D
OUT
IL
Chip Erase
A9= 14.0V
Others=V
T
AS
T
DS
T
OES
T
PRT
IL
T
Data All One
T
T
OEH
T
PWE
AHC
DH
T
VCS
V
IH
T
VR
IH
IL
VS
V
IH
Blank Check
Read Verify
T
ACC
D
OUT
T
OE
- 8 -
Timing Waveforms, continued
Programming Waveform
W27E512
Address
Data
OE/Vpp
CE
V
IH
V
IL
V
IH
V
IL
12.0V
V
IH
V
IL
V
IH
IL
V
Address Stable
T
T
DS
T
OES
T
PRT
AS
Data In Stable
T
PWP
Program Program
Address
Stable
T
AH
T
AS
Data In
Stable
T
DS
T
DH
Address
Stable
Address
Valid
T
AH
Data
Out
T
DH
T
DV1
T
OEH
VIL
T
VR
V
IL
CE should not be toggled
during program verify period
Verify
T
DV2
T
OH
T
DFP
Address
Valid
T
ACC
T
OE
T
CE
Read
Verify
Data
Out
T
OH
Publication Release Date: November 1999
- 9 - Revision A8
SMART PROGRAMMING ALGORITHM 1
Start
Address = First Location
Vcc = 5.0V
OE/Vpp = 12V
W27E512
Increment
Address
Increment
Address
Last
Address?
Yes
No
Program One 100 S Pulse
No
Address = First Location
Pass
Program One 100 S Pulse
Last
Address?
Yes
X = 0
Verify
Byte
Vcc = 5.0V
OE/Vpp = V
Compare
All Bytes to
Original
Data
µ
Fail
µ
IL
No
Fail
Increment X
X = 25 ?
Yes
Device
Failed
Device
Passed
- 10 -
Pass
SMART PROGRAMMING ALGORITHM 2
Address = First Location
Vcc = 5.0V
W27E512
Start
X = 0
Increment
Address
Fail
Program One 100 S Pulse
OE/V = 12V
µ
PP
Increment X
X = 25?
No
Verify One Byte
OE/V = V
IL
PP
Pass
No
Last Address
?
Yes
Compare
All Bytes to
Original
Data
Pass
Device
Passed
Yes
Verify One Byte
OE/V = V
PP
Fail
IL
Pass
Fail
Device
Failed
Publication Release Date: November 1999
- 11 - Revision A8
SMART ERASE ALGORITHM
W27E512
Start
X = 0
Vcc = 5V
OE/Vpp = 14V
Increment
Address
A9 = 14V; A0 = V
Chip Erase 100 mS Pulse
Address = First Location
Increment X
Vcc = 3.75V
OE/Vpp = V
Erase
Verify
No
Last
Address?
Vcc = 5V
OE/Vpp = V
Compare
All Bytes to
FFs (HEX)
IL
IL
Pass
Yes
IL
Fail
No
X = 20 ?
Yes
Fail
Pass
Device
Pass
- 12 -
Fail
Device
ORDERING INFORMATION
W27E512
PART NO. ACCESS
TIME
(nS)
W27E512-45 45 30 100 600 mil DIP
W27E512-55 55 30 100 600 mil DIP
W27E512-70 70 30 100 600 mil DIP
W27E512-90 90 30 100 600 mil DIP
W27E512-12 120 30 100 600 mil DIP
W27E512-15 150 30 100 600 mil DIP
W27E512S-45 45 30 100 300 mil SOP
W27E512S-55 55 30 100 300 mil SOP
W27E512S-70 70 30 100 300 mil SOP
W27E512S-90 90 30 100 300 mil SOP
W27E512S-12 120 30 100 300 mil SOP
W27E512S-15 150 30 100 300 mil SOP
W27E512Q-45 45 30 100 28-pin TSOP
W27E512Q-55 55 30 100 28-pin TSOP
W27E512Q-70 70 30 100 28-pin TSOP
W27E512Q-90 90 30 100 28-pin TSOP
W27E512Q-12 120 30 100 28-pin TSOP
W27E512Q-15 150 30 100 28-pin TSOP
W27E512P-45 45 30 100 32-pin PLCC
W27E512P-55 55 30 100 32-pin PLCC
W27E512P-70 70 30 100 32-pin PLCC
W27E512P-90 90 30 100 32-pin PLCC
W27E512P-12 120 30 100 32-pin PLCC
W27E512P-15 150 30 100 32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (
µ
A)
PACKAGE
Publication Release Date: November 1999
- 13 - Revision A8
PACKAGE DIMENSIONS
3. Dimensions D & E1 include mold mismatch and
28-pin P-DIP
W27E512
28
E
1
1
S
2
A
A
L
D
B
B
1
28-pin SO Wide Body
28
1
S
Seating Plane
e
Dimension in Inches
Symbol
15
14
1
A
Base Plane
E
Seating Plane
e
1
e
A
a
Notes:
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
c
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
Symbol
15
E
EH
14
b
D
A
A
2
1
A
y
θ
L
1
e
See Detail F
Detail F
1
e
Notes:
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
c
E
L
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
Nom.
Min.
A
0.010
A
1
0.155
0.150
A
2
0.016
0.018
B
0.060 1.52
1
B
0.008
0.010
c
1.460 1.470
D
0.6000.590
E
0.540 0.5500.545
E
1
1
e
0.120
0.130
L
015
a
0.630
0.650
A
e
S
Dimension in Inches Dimension in mm
Nom.
Min.
A
0.004
A
1
0.098
0.093
2
A
0.014
0.016
b
c
0.713
D
E
e
E
H
0.028
0.036
L
0.059
0.067
E
L
S
y
0 10
θ
Dimension in mm
Nom.
Max. Max.
Min.
0.210
0.25
0.160
3.81
3.94
0.022
0.41
0.46
0.0640.058
0.20
0.014
0.25
37.08
15.24
0.610
14.99
13.72 13.9713.84
0.110
2.29 2.54 2.790.090 0.100
3.05
0.140
3.30
0.670
16.00 16.51
0.090
Nom.
Max. Max.
Min.
0.112
0.10
0.103
2.36
2.49
0.36
0.41
0.020
0.250.200.0100.008
0.014 0.36
0.733
18.11
8.28
8.41
0.3360.3310.326
1.12 1.27 1.420.044 0.050 0.056
0.4770.4650.453 12.1211.8111.51
0.044
0.91 1.12
0.71
0.075 1.50
1.70
0.004
0
.
2.85
18.62
5.33
4.06
0.56
1.631.47
0.36
37.34
15.49
3.56
150
17.02
2.29
2.62
0.51
8.53
1.91
1.190.047
0.10
10
- 14 -
Package Dimensions, continued
28-pin Standard Type One TSOP
W27E512
1
e
b
θ
L
32-pin PLCC
5
13
14
L
θ
Seating Plane
H
D
D
c
E
A
2
A
A
1
Y
L
1
H
E
E
1
324
30
29
G
D
DH
21
20
2A
A
e
b
1b
EG
1
A
y
D
c
Symbol
A
A
A
b
c
D
E
H
e
L
L
Y
θ
1
2
D
1
Dimension In Inches
Min.
Nom. Max. Min. Nom.
0.002
0.040
0.035
0.007 0.008 0.011
0.004
0.006
0.461 0.465 0.469
0.311 0.315 0.319
0.520 0.528 0.536
0.022
0.020
0.024 0.028
0.010
0.000 0.004
0
Dimension In mm
Max.
0
1.00
0.20 0.27
0.15 0.21
11.90
11.80
8.00 8.10
13.60
13.40
0.55
0.60
0.25
3
1.20
0.15
1.05
0.70
0.10
5
0.047
0.05
0.006
0.95
0.041
0.17
0.10
0.008
11.70
7.90
13.20
0.50
0.00
3
5
Controlling dimension: Millimeters
Dimension in Inches
Symbol
Notes:
1. Dimension D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final visual
Min.
A
0.020
A
1
A
2
b
1
0.016
b
0.008
c
0.547
D
0.447
E
e
0.490
G
D
0.390
G
E
0.585
H
D
0.485
H
E
0.075
L
y
010 100
θ
inspection spec.
Nom.
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.49
0.090
Dimension in mm
Nom.
Max. Max.
Min.
0.140
0.50
2.802.67 2.93
0.1150.105 0.110
0.66 0.81
0.0320.026
0.71
0.41
0.022
0.46
0.20
0.014
0.25
13.89
13.97
11.35
11.43
1.27
1.12 1.420.044 0.056
12.45 12.95 13.46
9.91
10.41
14.86
14.99
12.32
12.45
1.91 2.29
14.05
11.51
10.92
15.11
12.57
0.553
0.453
0.530
0.430
0.595
0.495
0.095
0.004
3.56
0.56
0.35
2.41
0.10
Publication Release Date: November 1999
- 15 - Revision A8
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A6 Apr. 1997 1, 13, 14 Add SOP package
A7 Feb. 1998 1, 2, 3, 5, 6, 13 Add 45/55 nS bining
A8 Nov. 1999 2, 3 Modify function description ( VIL and VIH):
IL
V
→ Low. VIH → High.
4 Modify A9 and VPP Erase Voltage (VID and VPP):
from 13.75V (min) to 13.25V (min)
6 Modify VCC description
W27E512
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
- 16 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
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