Rainbow Electronics W27E512 User Manual

W27E512

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.

FEATURES

• High speed access time:

45/55/70/90/120/150 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 1 mA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 28-pin 600 mil DIP, 330 mil

SOP, TSOP and 32-pin PLCC

PIN CONFIGURATIONS

1

OE/Vpp

V
A15

A6
A5
A4
A3
A2
A1
A0
NC
Q0

A11

A13
A14

A12

A15

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

Q0

12

Q1

13

Q2

14

GND

A7N

4321
5
6

7
8
9
10
11
12

1

13

4

Q1Q

1
2

A9

3

A8

4
5
6

CC

7
8
9
10

A7

11

A6

12

A5

13

A4

14

A3

A
1
2

151

2

28-pin

A
1
5

32-pin
PLCC

6

G
N
D

DIP

C

1
7

N
C

28-pin
TSOP

A

V

1

C

4

C

3

3

2

1

18192

Q
3Q4

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A
1
3

3
029

0

Q
5

BLOCK DIAGRAM

V

CC

A14

A13

A8

A9

A11

OE/Vpp
A10

CE
Q7

Q6

Q5

Q4

Q3

OE/V

CE

A0

A15

V

CONTROL

PP

.

DECODER

.

CC

OUTPUT
BUFFER

CORE

ARRAY

GND

A8
A9

28

A11

27

NC

26
25

OE/Vpp
A10

24
23

CE

22

Q7

21

Q6

A10

28
27

CE

26

Q7

25

Q6

24

Q5
Q4

23

Q3

22

GND

21

Q2

20
19

Q1

18

Q0

17

A0

16

A1

15

A2

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A15

Q0−Q7

CE

PP

OE

/V

VCC Power Supply

GND Ground

NC No Connection

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable, Program/Erase
Supply Voltage

Q0

Q7

.
.

Publication Release Date: November 1999

- 1 - Revision A8

W27E512

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E512 has two control functions, both of which produce data

CE

at the outputs.

is for power control and chip select. OE/V

to the output pins. When addresses are stable, the address access time (T

CE

from
if T

to output (T

ACC

and TCE timings are met.

CE

), and data are available at the outputs TOE after the falling edge of

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.

Erase mode is entered when

OE

is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0

/V

PP

low, and all other address pins low and data input pins high. Pulsing
operation.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V

CE

V

(3.75V),

CE

low, and OE/V

PP

low.

PP

controls the output buffer to gate data

ACC

) is equal to the delay

OE

CE

low starts the erase

/V

CC

PP

=

,

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

OE

way to change cell data from "1" to "0." The program mode is entered when
(12V), V

desired inputs. Pulsing

CC

= VCP (5V), the address pins equal the desired addresses, and the input pins equal the

CE

low starts the programming operation.

/VPP is raised to VPP

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial

PP

program margin. This mode will be entered after the program operation if

OE

/V

low and

CE

low.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

CE

data. When
CE

and OE/V

high, erasing or programming of non-target chips is inhibited, so that except for the

PP

pins, the W27E512 may have common inputs.

- 2 -

W27E512

CE OE

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby

PP

OE

/V

mode, all outputs are in a high impedance state, independent of

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E512 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I

transient current peaks produced by the falling and rising edges of
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its V
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between V

CC

and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace

inductances.

CC

and GND. This high frequency, low inherent-

.

SB

), active current levels (ICC), and

CE

. Transient current magnitudes

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)

MODE PINS

Read VIL V

Output Disable VIL V

/VPP

IL

X X VCC D

IH

X X VCC High Z

A0 A9 V

Standby (TTL) VIH X X X VCC High Z

Standby (CMOS)

V

CC

±0.3V

Program VIL V

Program Verify VIL V

Program Inhibit VIH V

Erase VIL V

Erase Verify VIL V

Erase Inhibit VIH V

Product Identifier-manufacturer VIL V

Product Identifier-device VIL V

X X X V

PP

X X VCP DIN

IL

X X VCC D

PP

X X VCP High Z

PE

V

IL

X X 3.75 D

PE

X X VCE High Z

IL

V

IL

V

IL

VPE VCE DIH

IL

VHH VCC DA (Hex)

IH

VHH VCC 08 (Hex)

Publication Release Date: November 1999

- 3 - Revision A8

CC OUTPUTS

OUT

CC

High Z

OUT

OUT

W27E512

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Ambient Temperature with Power Applied -55 to +125

Storage Temperature -65 to +125

Voltage on all Pins with Respect to Ground Except

PP,

OE

/V

A9 and VCC Pins

Voltage on OE/VPP Pin with Respect to Ground

-0.5 to V

CC

+0.5 V

-0.5 to +14.5 V

Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V

Voltage VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%)

°

C

°

C

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10

VCC Erase Current ICP

VPP Erase Current IPP

CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

µ

CE

V

CE

OE

PE

= V

= V

/V

IL,

IL,

PP

= VPE

OE

/V

PP

=

- - 30 mA

- - 30 mA

A

Input Low Voltage VIL - -0.3 - 0.8 V

Input High Voltage VIH - 2.4 - 5.5 V

Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V

Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - -

A9 Erase Voltage VID - 13.25 14 14.25 V

VPP Erase Voltage VPE - 13.25 14 14.25 V

VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

VCC Supply Voltage

VCE - 3.5 3.75 4.0 V

(Erase Verify)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 4 -

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN V

Output Capacitance C

OUT

V

IN

= 0V 6 pF

OUT

= 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

45/55/70 nS 90/120/150 nS

Input Pulse Levels 0 to 3.0V 0.45V to 2.4V

Input Rise and Fall Times 5 nS 10 nS

Input and Output Timing Reference Level 1.5V/1.5V 0.8V/2.0V

Output Load CL = 30 pF,

OH/IOL

I

AC Test Load and Waveforms

= -0.4 mA/2.1 mA

L

= 100 pF,

C

OH/IOL

I

= -0.4 mA/2.1 mA

W27E512

+1.3V

(IN914)

3.3K ohm

D

OUT

100 pF for 90/120/150 nS (Including Jig and Scope

30 pF for 45/55/70 nS (Including Jig and Scope)

For 90/120/150 nS

For 45/70 nS

2.4V

0.45V

3.0V

Input

Input

0V

Test Points Test Points

Test Point Test Point

1.5V

2.0V

0.8V

Output

2.0V

0.8V

Output

1.5V

Publication Release Date: November 1999

- 5 - Revision A8