Rainbow Electronics W27E040 User Manual

W27E040

1

4

678

Q2

V

CC

V

PP

CE

OE

512K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E040 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 524288 × 8 bits that operates on a single 5 volt power supply. The W27E040
provides an electrical chip erase function.

FEATURES

• High speed access time:

90/120 nS (max.)

• Read operating current: 15 mA (typ.)

• Erase/Programming operating current

15 mA (typ.)

• Standby current: 5 µA (typ.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 32-pin 600 mil DIP, 450

mil SOP, PLCC and TSOP

PIN CONFIGURATIONS

V

PP

1
2

A16

3

A15

4

A12

5

A7

6

A6

7

A5
A4
A3
A2
A1
A0
Q0
Q1
Q2

GND

A7
A6
A5
A4
A3
A2
A1
A0
Q0

A11

2

A9

3

A8

A13

5

A14
A17
A18

9
10

A16

11

A15

12

A12

13

A7

14

A6

15

A5

16

A4

32-pin

8

DIP

9
10
11
12
13
14
15
16

A
1
5

34

2

V

A
1

P

6

P

32-pin
PLCC

G

Q3Q4Q5Q
N
D

32-pin
TSOP

A

V
C

1
8

C

A
1
2

5
6
7
8

9
10
11
12
13

Q1Q

BLOCK DIAGRAM

32

V

CC

31

A18

30

A17

29

A14

28

A13

27

A8

26

A9
A11

25
24

OE
A10

23
22

CE
Q7

21

Q6

20

Q5

19

Q4

18
17

Q3

A

1
7

30313212

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

Q7

20191817161514

6

32

OE
A10

31
30

CE
Q7

29

Q6

28

Q5

27

Q4

26

Q3

25

GND

24
23

Q1

22

Q0

21

A0

20

A1

19

A2

18

A3

17

PIN DESCRIPTION

CE
OE

CONTROL

OUTPUT
BUFFER

A0

.
.

DECODER

CORE
ARRAY

A18

V

CC

GND

V

PP

SYMBOL DESCRIPTION

A0−A18

Q0−Q7

Address Inputs
Data Inputs/Outputs
Chip Enable

Output Enable
VPP Program/Erase Supply Voltage
VCC Power Supply

GND Ground

NC No Connection

Q0

.
.

Q7

Publication Release Date: May 1997

- 1 - Revision A1

W27E040

OE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E040 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to

the output pins. When addresses are stable, the address access time (TACC) is equal to the delay
from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if

TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E040 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below
but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL, and all

other address pins equal VIL and data input pins equal VIH.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIH, and OE =
VIL.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired address, and the input
pins equal the desired inputs.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIH,

= VIL and VCC = VCP (5V).

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = VIH, VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of non­target chips is inhibited, so that except for the CE and VPP, and VCC, the W27E040 may have

common inputs.

- 2 -

W27E040

CE

OE

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH, VPP = 5V,
and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E040 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its VCC and GND. This high frequency, low inherent­inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)

MODE PINS

A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X VCC VCC DOUT
Output Disable VIL VIH X X VCC VCC High Z
Standby (TTL) VIH X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH X X VCP VPP DIN
Program Verify VIH VIL X X VCP VPP DOUT
Program Inhibit VIH X X X VCP VPP High Z
Erase VIL VIH VIL VPE VCE VPE DIH
Erase Verify VIH VIL X X VCE VPE DOUT
Erase Inhibit VIH X X X VCE VPE High Z
Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC DA (Hex)
Product Identifier-device VIL VIL VIH VHH VCC VCC 86 (Hex)

VCC ±0.3V

X X X VCC VCC High Z

Publication Release Date: May 1997

- 3 - Revision A1

DC CHARACTERISTICS

CE

CE

Absolute Maximum Ratings

PARAMETER RATING UNIT

W27E040

Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all pins with Respect to Ground Except VPP, A9

and VCC pins
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage on VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to VCC +0.5 V

°C
°C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V

= VIL
= VIL

- - 30 mA

- - 30 mA

µA

Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - ­A9 Erase Voltage VID - 13.75 14 14.25 V
VPP Erase Voltage VPE - 13.75 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance COUT VOUT = 0V 12 pF

- 4 -

W27E040

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0.45V to 2.4V
Input Rise and Fall Times 10 nS
Input and Output Timing Reference Level 0.8V/2.0V
Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveform

+1.3V

(IN914)

D

OUT

Input

2.4V

0.45V

3.3K ohm

100 pF (Including Jig and Scope)

Output

Test Points Test Points

2.0V

0.8V

2.0V

0.8V

Publication Release Date: May 1997

- 5 - Revision A1

READ OPERATION DC CHARACTERISTICS

CE

CE

CE

OE

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

W27E040

Input Load Current ILI VIN = 0V to VCC -5 - 5
Output Leakage Current ILO VOUT = 0V to VCC -10 - 10
VCC Standby Current ISB

ISB1

VCC Operating Current ICC

VPP Operating Current IPP VPP = VCC - - 10
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VCC +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.4 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
VPP Operating Voltage VPP - VCC -0.7 - VCC V

= VIH
= VCC ±0.2V

= VIL
IOUT = 0 mA
f = 5 MHz

- - 1.0 mA

- 5 100

- - 30 mA

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER SYM. W27E040-90 W27E040-12 UNIT

µA
µA

µA

µA

MIN. MAX. MIN. MAX.

Read Cycle Time TRC 90 - 120 - nS
Chip Enable Access Time TCE - 90 - 120 nS
Address Access Time TACC - 90 - 120 nS
Output Enable Access Time TOE - 40 - 55 nS

High to High-Z Output

Output Hold from Address Change TOH 0 - 0 - nS

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TDF - 30 - 30 nS

- 6 -

W27E040

CE

CE

CE

CE

OE

OE

OE

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Program Current ICP
VPP Program Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V
VPP Program Voltage VPP - 11.75 12.0 12.25 V
VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V

= VIL
= VIL

- - 30 mA

- - 30 mA

µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - ­Address Setup Time TAS 2.0 - ­Data Setup Time TDS 2.0 - -

Program Pulse Width
Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time TAH 0 - ­Address Hold Time after CE High (Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TPWP 95 100 105
TPWE 95 100 105 mS

TOES 2.0 - ­TOEV - - 150 nS
TDFP 0 - 130 nS

TAHC 2.0 - -

µS
µS
µS
µS

µS
µS

µS
µS

Publication Release Date: May 1997

- 7 - Revision A1

TIMING WAVEFORMS

Address Valid

IL

AC Read Waveform

V

IH

Address

V

IL

V

IH

CE

IL

IH

OE

V

IL

Outputs

High Z

W27E040

CE

T

T

DF

T

T

ACC

OE

Valid Output

T

OH

High Z

Erase Waveform

V

Data

V

CE

OE

PP

14.0V

5.0V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Address

Read

SID

A9 = 12.0V

A0= V

IL

Read

Device

SID

IH

IL

Others = V

T

ACC

IL

Manufacturer

Others = V

A0 = V
T

ACC

DA 86 Data All One

T

CE

T

T

OE

OE

Chip Erase
A9 = 14.0V

Others = V

T

AS

T

DS

T

VPS

T

T

ARC

PWE

Erase Verify

Address
Stable

T

AHC

T

OES

Blank Check
Read Verify

Address
Stable

T

DFP

D

OUT

T

AH

D

OUT

Address
Stable

T

ACC

D

OUT

5V

T

OE

T

OEV

- 8 -

Timing Waveforms, continued

Programming Waveform

W27E040

Address

Data

V

Program

V

IH

V

IL

12.0V

PP

5.0V

V

IH

CE

V

IL

V

IH

OE

V

IL

T

T

VPS

Address Stable

AS

Data In Stable

T

DS

T

PWP

Program

Verify

Address Stable

T

DFP

D

OUT

T

DH

T

OES

T

AH

T

OEV

D

OUT

Read
Verify

Address Valid

T

ACC

T

OE

D

OUT

5V

Publication Release Date: May 1997

- 9 - Revision A1

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V

Vpp = 12V

X = 0

W27E040

Increment
Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

Verify One Byte

No

*Program whole chip
without data verification and read

Last
Address?

Vcc = 5V

Vpp = 5V

µ

Yes

No

Pass

Yes

Verify One Byte

Pass

Fail

Compare All Bytes

to Original Data

Pass

Pass
Device

*: Program the whole chip again without data verification and read.

- 10 -

Fail

Fail
Device

SMART ERASE ALGORITHM

W27E040

Start

X = 0

Vcc = 5V

Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Erase

Verify

No

Last
Address?

Vcc = 5V
Vpp = 5V

Compare
All Bytes to
FFs (HEX)

IL

Pass

Yes

No

Fail

X = 20?

Yes

Fail

Pass
Device

Pass

Fail
Device

Publication Release Date: May 1997

- 11 - Revision A1

ORDERING INFORMATION

W27E040

PART NO. ACCESS

TIME

(nS)

W27E040-90 90 30 100 600 mil DIP
W27E040-12 120 30 100 600 mil DIP
W27E040S-90 90 30 100 450 mil SOP
W27E040S-12 120 30 100 450 mil SOP
W27E040P-90 90 30 100 32-pin PLCC
W27E040P-12 120 30 100 32-pin PLCC
W27E040T-90 90 30 100 Type One TSOP
W27E040T-12 120 30 100 Type One TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

- 12 -

PACKAGE DIMENSIONS

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

6. General appearance spec. should be based on

32-pin P-DIP

W27E040

32

E

1

1

S

2

A

A

L

B
B

1

32-Lead SO Wide Body

32

1

D

S

Seating Plane

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

1

A

0.155

0.150

A

2

0.016

0.018

B

0.050 1.27

B1

0.010

D

e

1

17

16

A

1

Base Plane

Seating Plane

17

E H

E

E

e

A

a

e

1

c

L

16

b

A

A

2

e

y

A

1

See Detail F

Detail F

e

1

c

L

E

0.008

c

1.650 1.660

D

0.6000.590

E

0.545

0.550

E

1

e

1

0.120

0.130

L

0 15

a

0.6500.630 16.00 16.51

e

A

S

Notes:

1. Dimensions D Max. & S include mold flash or
tie bar burrs.

are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches
final visual inspection spec.

Dimension In Inches Dimension In mm

Symbol

A
A
A
b
c
D
E
e
HE
L
LE
S
y

θ

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

Nom.

Min.

0.004

1

0.106

0.101

2

0.014

0.016

0.805

0.047

0.055

0

Dimension in mm

0.210

0.25

0.160

3.81

3.94

0.41

0.46

0.022

0.20

0.014

0.25

41.91 42.16

15.24

0.610

14.99

13.84

13.97

0.555

0.110

2.29 2.54 2.790.090 0.100

3.05

0.140

3.30

0.670

0.085

.

Nom.

Max. Max.

Min.

0.118

0.10

0.111

2.57

0.004

2.69

0.36

0.41

0.200.150.0080.006

20.45

11.18

11.30

1.12 1.27 1.420.044 0.050

0.79 0.990.023 0.031

0.58

1.19

1.40

10

0

0.020

0.012 0.31

0.817

0.4500.4450.440

0.056

0.5560.5560.546 14.3814.1213.87

0.039

0.063

0.036

.

5.33

4.06

0.56

1.371.220.0540.048

0.36

15.49

14.10

3.56

17.02

2.16

3.00

2.82

0.51

20.75

11.43

1.60

150

0.91

0.10
10

Publication Release Date: May 1997

- 13 - Revision A1

Package Dimensions, continued

32-Lead PLCC

H

E

E

1

324

5

13

14 20

L

e

b
b

Seating Plane

1

EG

W27E040

30

29

D

H

D

21

G D

c

Dimension In Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

1

A

2

A

1

b

0.016

b

0.008

c

0.547

D

0.447

E
e

0.490

D

G

0.390

G

E

0.585

D

H

0.485

HE

0.075

L
y

θ

0.028

0.018

0.010

0.550

0.450

0.050

0.51

0.410

0.590

0.49

0.090

°

0

Notes:

2A

A

1

A

y

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on fina visual
inspection sepc.

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

14.86

0.595

12.32

0.495

0.095

0.004

°

10

Dimension In mm

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.27

1.12 1.420.044 0.056

12.45 12.9

9.91

10.41

14.99

12.45

1.91 2.29

°

0

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

32-Lead TSOP

M

e

0.10(0.004)

b

θ

L

L1

H

D

D

c

E

A

2

A

1

A

Y

Symbol

A
A
A

b

D
E

H

e
L

L

θ

Note:

1

2

c

D

1

Y

Dimension In Inches

Min. Nom.

__

0.002

0.037

0.007 0.008

0.005 0.006

0.720 0.724

0.311 0.315

0.780 0.787

__

0.016 0.020

__

0.000 0.004
1

Max.

__

0.047

__ __

0.006

0.041

0.039

0.009

0.007

0.728

0.319

0.795

0.020

0.024

0.031

__

3

Min. Nom.

0.05

0.95

0.17

0.12

18.30

7.90

19.80

__

__

5

Dimension In mm

Max.

__

__

0.20 0.23

0.15 0.17

18.40 18.50

8.00 8.10

20.00

1

20.20

0.50

0.50 0.60

0.80

__

3

__

0.40

__

0.00

1.20

0.15

1.051.00

__

__

0.10
5

Controlling dimension: Millimeters

- 14 -

W27E040

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: May 1997

- 15 - Revision A1