Rainbow Electronics W27E010 User Manual

W27E010

CE

OE

PGM

128K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E010 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 131072 × 8 bits that operates on a single 5 volt power supply. The W27E010
provides an electrical chip erase function.

FEATURES

• High speed access time:

45/55/70/90/120 nS (max.)

• Read operating current: 30 mA (typ.)

• Erase/Programming operating current:

1 mA (typ.)

• Standby current: 5 µA (typ.)

• Single 5V power supply

PIN CONFIGURATIONS

Vpp

1

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

Q0

13
14

Q1
Q2

A
1
2

5
6

7
8
9
10
11
12

1

13

4

Q1Q

15
16

A

A

1

1

6

5

4 3 2 1

32-pin PLCC

151

6

G

2

N
D

V
p
p

1
7

Q
3

V
c
c

3
2

18192

Q4Q

GND

A7
A6
A5
A4
A3
A2
A1
A0
Q0

Vcc

32

PGM

31

NC

30

A14

29

A13

28

A8

27
26

A9
A11

25
24

OE

23

A10

22

CE
Q7

21
20

Q6

19

Q5

18

Q4

17

Q3

/
P

N

G

C

M

3

3

1

0

0

Q

5

6

A14

29

A13

28

A8

27

A9

26
25

A11
OE

24

A10

23
22

CE
Q7

21

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 32-pin 600 mil DIP, 450

mil SOP and PLCC

BLOCK DIAGRAM

PGM

A16

GND

CE
OE

V

V

CONTROL

A0

.

DECODER

.

CC

PP

OUTPUT
BUFFER

CORE
ARRAY

Q0

.
.

Q7

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A16

Q0−Q7

VPP Program/Erase Supply Voltage
VCC Power Supply

GND Ground

NC No Connection

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable

FUNCTIONAL DESCRIPTION

Publication Release Date: May 1997

- 1 - Revision A5

W27E010

CE

PGM

PGM

PGM

OE

PGM

CE

Read Mode

Like conventional UVEPROMs, the W27E010 has two control functions, both of which produce data
at the outputs.

is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (TACC) is equal to the delay from CE to output
(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E010 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below
but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL, and all
other address pins equal VIL and data input pins equal VIH. Pulsing

operation.

low starts the erase

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE =
VIL,

= VIH.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the
input pins equal the desired inputs. Pulsing

low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIL,

= VIL, and

= VIH.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the

, the W27E010 may have common inputs.

- 2 -

W27E010

PGM

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In
standby mode, all outputs are in a high impedance state, independent of OE and

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E010 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (ISB), active current levels (ICC),

and transient current peaks produced by the falling and rising edges of CE. Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherent­inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.

.

TABLE OF OPERATING MODES

VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL

MODE PINS

CE OE PGM A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X X VCC VCC DOUT
Output Disable VIL VIH X X X VCC VCC High Z
Standby (TTL) VIH X X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH VIL X X VCP VPP DIN
Program Verify VIL VIL VIH X X VCP VPP DOUT
Program Inhibit VIH X X X X VCP VPP High Z
Erase VIL VIH VIL VIL VPE VCC VPE FF (Hex)
Erase Verify VIL VIL VIH X X VCC VPE DOUT
Erase Inhibit VIH X X X X VCP VPE High Z
Product Identifier-

Manufacturer
Product Identifier-Device VIL VIL X VIH VHH VCC VCC 01 (Hex)

VCC ±0.3V

VIL VIL X VIL VHH VCC VCC DA (Hex)

X X X X VCC VCC High Z

Publication Release Date: May 1997

- 3 - Revision A5

DC CHARACTERISTICS

CE

PGM

CE

PGM

Absolute Maximum Ratings

PARAMETER RATING UNIT

W27E010

Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except VCC, VPP

and A9 Pins
Voltage on VCC Pin with Respect to Ground -0.5 to +7 V
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

-0.5 to VCC +0.5 V

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNI

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP

= VIL, OE = VIH,

= VIL, A9 = VHH

- - 30 mA

°C
°C

T

µA

VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Erase Voltage VID - 13.75 14.0 14.25 V
VPP Erase Voltage VPE - 13.75 14.0 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

= VIL, OE = VIH,

= VIL, A9 = VHH

- 4 -

- - 30 mA

W27E010

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

45/55/70 nS 90/120 nS

Input Pulse Levels 0 to 3.0V 0.45V to 2.4V
Input Rise and Fall Times 5 nS 10 nS
Input and Output Timing Reference

Level
Output Load CL = 30 pF,

1.5V/1.5V 0.8V/2.0V

CL = 100 pF,

IOH/IOL = -0.4 mA/2.1 mA

IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

D

OUT

For 90/120 nS

For 45/55/70 nS

2.4V

0.45V

3.0V

+1.3V

(IN914)

3.3K ohm

100 pF for 90/120 nS (Including Jig and Scope)
30 pF for 45/55/70 nS (Including Jig and Scope)

2.0V

0.8V

Output

2.0V

0.8V

Output

1.5V

Input

Input

0V

Test Points Test Points

Test Point Test Point

1.5V

Publication Release Date: May 1997

- 5 - Revision A5

W27E010

CE

CE

CE

OE

READ OPERATION DC CHARACTERISTICS

(Vcc = 5.0V ±10%)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VCC -5 - 5
Output Leakage Current ILO VOUT = 0V to VCC -10 - 10
Standby VCC Current

ISB

= VIH

- - 1.0 mA

(TTL input)
Standby VCC Current

ISB1

= VCC ±0.2V

- 5 100

(CMOS input)
VCC Operating Current ICC

= VIL

- - 30 mA

IOUT = 0 mA

f = 5 MHz
VPP Operating Current IPP VPP = VCC - - 10
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VCC +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
VPP Operating Voltage VPP - VCC -0.7 - VCC V

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±10%, for 70, 90 and 120 nS; VCC = 5.0V ±5% for 45, 55 nS, TA = 0 to 70° C)

µA
µA

µA

µA

PARAMETER SYM. W27E010-45 W27E010-55 W27E010-70 W27E010-90 W27E010-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 45 - 55 - 70 - 90 - 120 - nS
Chip Enable Access Time TCE - 45 - 55 - 70 - 90 - 120 nS
Address Access Time TACC - 45 - 55 - 70 - 90 - 120 nS
Output Enable Access Time TOE - 20 - 25 - 30 - 40 - 55 nS

High to High-Z Output

Output Hold from Address
Change

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TDF - 20 - 20 - 25 - 25 - 30 nS

TOH 0 - 0 - 0 - 0 - 0 - nS

- 6 -

W27E010

CE

PGM

CE

PGM

PGM

PGM

OE

OE

OE

PGM

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH - - 10
VCC Program Current ICP

VPP Program Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V
VPP Program Voltage VPP - 11.75 12.0 12.25 V
VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V

= VIL, OE = VIH,

= VIL

= VIL, OE = VIH,

= VIL

- - 30 mA

- - 30 mA

µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - ­Address Setup Time TAS 2.0 - ­Data Setup Time TDS 2.0 - -

Program Pulse Width
Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time after
Address Hold Time (Erase) TAHE 2.0 - -

CE Setup Time

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

High

TPWP 95 100 105
TPWE 95 100 105 mS

TOES 2.0 - ­TOEV - - 150 nS
TDFP 0 - 130 nS
TAH 0 - -

TCES 2.0 - -

µS
µS
µS
µS

µS
µS

µS
µS
µS

Publication Release Date: May 1997

- 7 - Revision A5

TIMING WAVEFORMS

VILV

AC Read Waveform

V

IH

Address Address Valid

V

IL

V

IH

CE

IH

OE

V

IL

Outputs

High Z

W27E010

T

CE

T

DF

T

T

ACC

OE

Valid Output

T

OH

High Z

Erase Waveform

V

Data

V

PGM

IH

V

IL

14.0V

5.0V

PP

V

IH

CE

V

IL

V

IH

OE

V

IL

Address

Read

Manufacturer

SID

A9 = 12.0V

Others = V

A0 = V

T

AS

DA 01

T

CE

T

OE

IL

T

OE

Device

IL

A0=V

Others=V

T

AS

Read

SID

Chip Erase

A9 = 14.0V

Others = V

IH
IL

T

T

AS

AHC

Data All One

T

DS

Erase Verify

IL

Address
Stable

T

DFP

T

DH

Address

Stable

D

OUT D

T

AH

D

OUT

Blank Check
Read Verify

Address
Stable

T

ACC

OUT

5V

T

VPS

T

OES

T

T

T

CES

PWE

OEV

T

OE

- 8 -

Timing Waveforms, Continued

Programming Waveform

W27E010

Address

Data

V

PGM

Program

V

IH

V

IL

12.0V

PP

5.0V

V

IH

CE

V

IL

V

IH

OE

V

IL

V

IH

V

IL

T

AS

T

VPS

T

Address Stable

Data In Stable

T

DS

CES

T

PWP

Program

Verify

Address Stable

T

DFP

D

OUT

OES

T

AH

T

OEV

T

DH

T

D

OUT

Read
Verify

Address Valid

T

ACC

T

OE

D

OUT

5V

Publication Release Date: May 1997

- 9 - Revision A5

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V
Vpp = 12V

X = 0

W27E010

Increment
Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

No

Verify

One Byte

Last
Address?

Vcc = 5V

Vpp = 5V

Compare
All Bytes to

Original Data

µ

Yes

No

Pass

Yes

Fail

Verify

One Byte

Pass

Fail

Pass
Device

Pass

Fail
Device

- 10 -

SMART ERASE ALGORITHM

W27E010

Start

X = 0

Vcc = 5V

Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Erase
Verify

No

Last
Address?

Vcc = 5V

Vpp = 5V

Compare
All Bytes to

FFs (HEX)

IL

Pass

Yes

No

Fail

X = 20?

Yes

Fail

Pass
Device

Pass

Fail
Device

Publication Release Date: May 1997

- 11 - Revision A5

ORDERING INFORMATION

W27E010

PART NO. ACCESS

TIME

(nS)

W27E010-45 45 30 100 600 mil DIP
W27E010-55 55 30 100 600 mil DIP
W27E010-70 70 30 100 600 mil DIP
W27E010-90 90 30 100 600 mil DIP
W27E010-12 120 30 100 600 mil DIP
W27E010S-45 45 30 100 450 mil SOP
W27E010S-55 55 30 100 450 mil SOP
W27E010S-70 70 30 100 450 mil SOP
W27E010S-90 90 30 100 450 mil SOP
W27E010S-12 120 30 100 450 mil SOP
W27E010P-45 45 30 100 32-pin PLCC
W27E010P-55 55 30 100 32-pin PLCC
W27E010P-70 70 30 100 32-pin PLCC
W27E010P-90 90 30 100 32-pin PLCC
W27E010P-12 120 30 100 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

- 12 -

PACKAGE DIMENSIONS

1. Dimensions D Max. & S include mold flash or

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

6. General appearance spec. should be based on

32-pin P-DIP

32

1

E

1 16

S

2

A

A

L

D

B

e

1B

W27E010

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max.

A
A

1

A

2

B
B1
c
D

17

E
E1

1

e
L

a

A

e
S

0.210 5.33

0.010

0.150

0.155

0.160

0.016

0.018

0.022

0.050 1.27

0.0540.048

0.010

0.014

0.008

1.650 1.660

0.6000.590 0.610

0.540

0.5550.550

0.110

0.120

0.130

0.140

0 15

0.670

0.6500.630 16.00 16.51

0.085 2.16

Notes:

E

1

A

Base Plane

Seating Plane

1

e

a

A

tie bar burrs.

c

are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.
final visual inspection spec.

Min.

0.25

3.81

3.94

0.41

0.46

0.20

0.25

41.91

15.2414.99

13.84 14.1013.97

2.29 2.54 2.790.090 0.100

3.05

3.30

Max.Nom.

4.06

0.56

1.371.22

0.36

42.16

15.49

3.56

17.02

150

32-pin SO Wide Body

32

1

D

S

Seating Plane

y

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

17

E

E

H

e

1

L

16

b

2

A

A

1

e

A

Detail F

e

1

c

L

E

See Detail F

A

0.004

A

1

0.101

2

A

0.014

b
c
D

0.440

E
e
HE

0.023

L

0.047

L E
S

y

θ

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and are determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

0.106

0.016

0.0080.006

0.805

0.031

0.055

0

0.118

0.10

0.111

2.57

2.69

0.36

11.18

1.12 1.27 1.420.044 0.050

0.58

0

0.41

0.200.15

20.45

11.30

0.79 0.99

1.40

0.020

0.012 0.31

0.817

0.4500.445

0.056

0.5560.5560.546 14.3814.1213.87

0.039

0.063 1.19

0.036

0.004
10 10

.

20.75

11.43

3.00

2.82

0.51

1.60

0.91

0.10

Publication Release Date: May 1997

- 13 - Revision A5

Package Dimensions, Continued

2. Dimension b does not include dambar protrusion/intrusion.

32-Lead PLCC

H

E

4

5

13

14 20

L

θ

Seating Plane

E

1

32

e

b
b

1

G

E

W27E010

30

29

D

D

H

21

D

G

c

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

1

b

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

D

G

0.390

G E

0.585

H

D

0.485

HE

0.075

L
y

θ

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

°

0

Notes:

2

A

A

1

A

y

1. Dimensions D & E do not include interlead flash.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on

visual inspection sepc.

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.430

0.595

0.495

0.095

0.004

°

10

Dimension in mm

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.27

1.12 1.420.044 0.056

12.45 12.95 13.460.530

9.91

10.41

14.86

14.99

12.32

12.45

1.91 2.29

°

0

0.56

0.35

14.05

11.51

10.92

15.11

12.57

3.56

2.41

0.10

°

10

final

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

- 14 -

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.

TEL: [phone]
FAX: [phone]