Rainbow Electronics RF22 User Manual

RF22

Version: 0.1 Date: 12/23/2008

RF22 Universal ISM Band FSK Transceiver

Features

Frequency range = 240–930 MHz

z

z Sensitivity = –118dBm
z +20 dBm Max Output Power

Configurable +11 to +20 dBm

z Low Power Consumption 

18.5 mA receive
27mA @ +11dBm

z Data Rate = 1 to 128kbps
z Power Supply = 1.8 to 3.6V
z Ultra low power shutdown mode
z Digital RSSI
z Wake-on-radio
z Auto-frequency calibration (AFC)
z Antenna diversity & TR switch control
z Configurable packet structure
z Preamble detector
z TX & RX 64 byte FIFOs
z Low battery detector
z Temperature sensor and 8-bit ADC
z –40 to +85oC temperature range
z Integrated voltage regulators
z Frequency hopping capability
z On-chip crystal tuning
z 20-Pin QFN package
z FSK, GFSK, and OOK modulation
z Low BOM
z Power-on-reset (POR)

The RF22 offers advanced radio features including continuous frequency coverage from 240–930 MHz and adjustable output power
of up to +20 dBm. The RF22’s high level of integration offers reduced BOM cost while simplifying the overall system design. The
extremely low receive sensitivity (–118 dBm) coupled with industry leading +20 dBm output power ensures extended range and
improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and
enhance performance.

Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet
handling, and preamble detection reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated
temperature sensor, general purpose ADC, poweron- reset (POR), and GPIOs further reduce overall system cost and size.

The RF22’s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation,
filtering, and packet handling for increased performance. This digital architecture simplifies system design while allowing for the use
of lower-end MCUs. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and
reduced spectral spreading ensuring compliance with FCC and ETSI regulations.

Applications

z Remote control
z Home security & alarm
z Telemetry
z Personal data logging
z Toy control
z Tire Pressure monitoring
z Wireless PC peripherals
z Remote meter reading
z Remote keyless entry
z Home automation
z Industrial control
z Sensor networks
z Health monitors

z Tag readers

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1

RF22

Functional Block Diagram

Version: 0.1 Date: 12/23/2008

VDD_RF

TX

RFp

RFn

VR_IF

RF LDO

PA

PMAR_AP

LNA

IF LDO

RC 32K OSC

LPF

PLL LDO

ADC_REF

CP

N

Delta Sigma

Modulator

ADC

PFD

TXMOD

SPI, & Controller

Digital Modem

VCO LDO

LRT

C
_RWP

Mixers

BIAS

VCO

ANTDIV

TXRXSW

PA_RAMP

PWR_CTRL

AGC Control

PGA

SDN

Xin

Xout

30M XTAL

OSC

Digital Logic

GPIO_0

nSEL

VDD_DIG

LBD

Temp

Sensor

8Bit
ADC

SCLK

SDI
SDO

VDD_DIG
GND_DIG

Low Power
Digital LDO

Digital LDO

POR

GPIO_1

GPIO_2

VR_DIG

1. Electrical Specifications

Table1. DC Characteristics

Parameter Symbol Conditions Min Typ Max Units

Supply Voltage Range Vdd

I

Shutdown

Power Saving Modes

TUNE Mode Current I

I

Standby

I

Sleep

2

I

Sensor-LBD

I

Sensor-TS

I

Ready

Tune

RX Mode Current IRX — 18.5 TBD mA

I

TX_+20

I

TX_+11

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

1

RC Oscillator, Main Digital Regulator,

and Low Power Digital Regulator OFF

Low Power Digital Regulator ON (Register values retained)

and Main Digital Regulator, and RC Oscillator OFF

2

2

RC Oscillator and Low Power Digital Regulator ON

(Register values retained) and Main Digital Regulator OFF

Main Digital Regulator and Low Battery Detector ON,

Crystal Oscillator and all other blocks OFF

Main Digital Regulator and Temperature Sensor ON,

Crystal Oscillator and all other blocks OFF

2

2

Crystal Oscillator and Main Digital Regulator ON,

1.8 3.0 3.6 V

— 10 TBD nA

— 400 TBD nA

— 800 TBD nA

2

— 1 TBD A

— 1 TBD A

— 600 TBD A

all other blocks OFF. Crystal Oscillator buffer disabled

Synthesizer and regulators enabled — 9.5 TBD mA

txpow[1:0] = 11 (+20 dBm), VDD = 3.3 V — 60 TBD mA TX Mode Current
txpow[1:0] = 00 (+11 dBm), VDD = 3.3 V — 27 TBD mA

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2

RF22

Table2. Synthesizer AC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units

F

Low Band 240 — 480 MHz

2

Synthesizer Frequency Range

Reference Frequency f

Reference Frequency Input Level

Synthesizer Settling Time

Residual FM

2

2

2

Phase Noise

2

SYNTH-LB

F
F
F

f

High Band 480 — 930 MHz

SYNTH-HB

Low Band — 156.25 — Hz Synthesizer Frequency Resolution

RES-LB

High Band — 312.5 — Hz

RES-HB

f

REF

When using reference frequency instead of crystal.

REF_LV

/ 3 — 10 — MHz

crystal

Measured peak-to-peak (V

Measured from leaving Ready mode with XOSC

t

LOCK

Running to any frequency including VCO Calibration

F

Integrated over ±250 kHz bandwidth

RMS

(500 Hz lower bound of integration)

L(f

M

F = 10 kHz — –80 TBD dBc/Hz

)

F = 100 kHz — –90 TBD dBc/Hz
F = 1 MHz — –115 TBD dBc/Hz
F = 10 MHz — –130 TBD dBc/Hz

P

< 1 GHz — — –54 dBm

Spurious Emissions

2

OB-TX1

1–12.75 GHz, non-intentional radiator — — –54 dBm

P

OB-TX2

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Table3. Receiver AC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units

F

Low Band 240 — 480 MHz

RX Frequency Range

RX Sensitivity

2

SYNTH-LB

F
P
P
P
P

High Band 480 — 930 MHz

SYNTH-HB

(BER < 0.1%) (2 kbps, GFSK, BT=0.5, f = ±5 kHz)1 — –117 TBD dBm

RX_2

(BER < 0.1%) (40 kbps, GFSK, BT=0.5, f = ±20 kHz)1 — –106 TBD dBm

RX_40

(BER < 0.1%) (100 kbps, GFSK, BT=0.5, f =±50 kHz)2 — –102 TBD dBm

RX_100

(BER < 0.1%) (4.8 kbps, OOK)1 — –110 TBD dBm

RX_OOK

RX Bandwidth BW 2.6 — 620 kHz
Residual BER Performance2 P

Up to +5dBm Input Level — 0 0.1 ppm

RX_RES

Input Intercept Point, 3rd Order2 IIP3RX f1 = 915MHz, f2 = 915MHz, P1 = P2= –40dBm — –20 TBD dBm
LNA Input Impedance R
RSSI Resolution RES
±1-Ch Offset Selectivity2 (BER < 0.1%) C/I
±2-Ch Offset Selectivity2 (BER < 0.1%) C/I
±3-Ch Offset Selectivity2 (BER < 0.1%) C/I
Blocking at 1 MHz2 1M
Blocking at 4 MHz2 4M
Blocking at 8 MHz2 8M
Image Rejection Im
Spurious Emissions2 P

Unmatched, measured differentially across RX input pins — 250 — 

IN-RX

— ±0.5 — dB

RSSI

Desired Ref Signal 3 dB above sensitivity. Interferer and

— –31 TBD dB

1-CH

2-CH

3-CH

BLOCK

BLOCK

BLOCK

REJ

OB_RX1

desired modulated with 40 kbps F = 20 kHz GFSK with

— –35 TBD dB

BT = 0.5, channel spacing = 150 kHz

Desired Ref Signal 3 dB above sensitivity. Interferer and

— –52 TBD dB

desired modulated with 40 kbps F = 20 kHz GFSK with

— –56 TBD dB

BT = 0.5

IF=937 kHz — –30 — dB

Measured at RX pins (LO feed through) — — –54 dBm

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

1

)

PP

1

Version: 0.1 Date: 12/23/2008

0.7 — 1.6 V

— 200 TBD s

— 2 4 kHz

— –40 TBD dB

— –63 TBD dB

RMS

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3

RF22

Table4. Transmitter AC Electrical Characteristics1

Parameter Symbol Conditions Min Typ Max Units

F

Low Band 240 — 480 MHz

2

TX Frequency Range

FSK Modulation Data Rate2 DR
OOK Modulation Data Rate2 DR
Modulation Deviation2 f ±0.625 ±320 kHz
Modulation Deviation Resolution f
Output Power Range2 P
TX RF Output Steps2 P
TX RF Output Level Variation vs. Voltage2 P
TX RF Output Level2 Variation vs. Temperature P
TX RF Output Level Variation vs. Frequency2 P
Transmit Modulation Filtering B*T Gaussian Filtering Bandwith Time Product — 0.5 —

2

Spurious Emissions

Harmonics

2

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Table5. Auxiliary Block Specifications1

Parameter Symbol Conditions Min Typ Max Units

Temperature Sensor Accuracy2 TSA When calibrated using temp

Temperature Sensor Sensitivity2 TSS — 5 — mV/°C
Low Battery Detector Resolution2 LBD
Low Battery Detector Conversion Time2 LBDCT — 250 — s
Microcontroller Clock Output Frequency2 MC

General Purpose ADC Accuracy ADC
General Purpose ADC Resolution ADC
Temp Sensor & General Purpose ADC Conversion Time ADCCT — 305 — sec
30 MHz XTAL Start-Up time t
30 MHz XTAL Cap Resolution 30M
32 kHz XTAL Start-Up Time t
32 kHz XTAL Accuracy 32K
32 kHz RC OSC Accuracy 32KRC
POR Reset Time t
Software Reset Time t

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Table6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)

Parameter Symbol Conditions Min Typ Max Units

Rise Time T
Fall Time T

0.1 x VDD to 0.9 x VDD, CL= 5 pF — — 8 ns

RISE

0.9 x VDD to 0.1 x VDD, CL= 5 pF — — 8 ns

FALL

Input Capacitance CIN — — 1 pF
Logic High Level Input Voltage VIH V
Logic Low Level Input Voltage VIL — 0.6 V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Logic High Level Output Voltage VOH I
Logic Low Level Output Voltage VOL I
Note: All specification guaranteed by production test unless otherwise noted.

SYNTH-LB

F

SYNTH-HB

FSK

OOK

RES

Tested at 915 MHz, txpow[1:0] = 11 +11 — +20 dBm

TX

RF_OUT

RF_V

RF_TEMP

RF_FREQ

P

OB-TX1

P

OB-TX2

P

2HARM

P

3HARM

High Band 480 — 930 MHz

1 — 128 kbps

1.2 — 40 kbps

— 0.625 — kHz

TXPWR[1:0] = 00 thru 11 TBD 3 TBD dB

Measured from VDD=3.6 V to VDD=1.8 V — 2 TBD dB

–40 to +85oC — 2 TBD dB
Measured across any one frequency band — 1 TBD dB

POUT = 11 dBm, Frequencies <1 GHz — — –54 dBm
1–12.75 GHz, excluding harmonics — — –54 dBm

Using Reference Design TX Matching Network

— — –42 dBm

and Filter with Max Output Power (20 dBm).
Harmonics reduce linearly with output power

sensor offset register

— 50 — mV

RES

Configurable to 30 MHz, 15 MHz, 10 MHz,
4 MHz, 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz

— 8 — bit

ENB

— 4 — mV

RES

— 1 — ms

30M

— 97 — fF

RES

— 6 — sec

32k

— 100 — ppm

RES

— 2500 — ppm

RES

— 16 — ms

POR

— 100 — s

soft

< 1mA source, VDD=1.8 V VDD – 0.6 — — V

OH

<1 mA sink, VDD=1.8 V — — 0.6 V

OL

Version: 0.1 Date: 12/23/2008

— — –42 dBm

— 0.5 — °C

32768 — 30M Hz

– 0.6 — — V

DD

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4

RF22

Table7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)

Parameter Symbol Conditions Min Typ Max Units

Rise Time T
Fall Time T
Input Capacitance CIN — — 1 pF
Logic High Level Input Voltage VIH V
Logic Low Level Input Voltage VIL — — 0.6 V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Input Current If Pullup is Activated I

Maximum Output Current

Logic High Level Output Voltage VOH I
Logic Low Level Output Voltage VOL I
Note: All specification guaranteed by production test unless otherwise noted.

0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV<1:0>=HH — — 8 ns

RISE

0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV<1:0>=HH — — 8 ns

FALL

V

INP

I

DRV<1:0>=LL 0.1 0.5 0.8 mA

OmaxLL

I

DRV<1:0>=LH 0.9 2.3 3.5 mA

OmaxLH

I

DRV<1:0>=HL 1.5 3.1 4.8 mA

OmaxHL

I

DRV<1:0>=HH 1.8 3.6 5.4 mA

OmaxHH

=0 V 5 — 25 A

IL

< I

source, VDD=1.8 V VDD – 0.6 — — V

OH

Omax

< I

sink, VDD=1.8 V — — 0.6 V

OL

Omax

Table8. Absolute Maximum Ratings

Parameter Value Units

VDD to GND –0.3, +3.6 V
VDD to GND on TX Output Pin –0.3, +8.0 V
Voltage on Digital Control Inputs –0.3, V
Voltage on Analog Inputs –0.3, VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA –40 to +85 °C
Thermal Impedance JA 30 °C/W
Junction Temperature TJ +125 °C
Storage Temperature Range T

Note:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Caution: ESD sensitive device.

Power Amplifier may be damaged if switched on without proper load connected.

–55 to +125 °C

STG

Version: 0.1 Date: 12/23/2008

– 0.6 — V

DD

+ 0.3 V

DD

1.1. Definition of Test Conditions

Production Test Conditions:

T

A

V

DD

External reference signal (XIN) = 1.0 V
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the RF22 (not the RF module)

Extreme Test Conditions:

T

A

V

DD

External reference signal (XIN) = 0.7 to 1.6 V
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the RF22 (not the RF module)

o

= +25

= –40 to +85

C

= +3.3 VDC

o

C

= +1.8 to +3.6 VDC

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at 30 MHz, centered around 0.8 VDC

PP

at 30 MHz centered around 0.8 VDC

PP

5

RF22

Test Notes:

All electrical parameters with Min/Max values are guaranteed by one (or more) of the following test methods.
Electrical parameters shown with only typical values are not guaranteed.

 Guaranteed by design and/or simulation but not tested.
 Guaranteed by Engineering Qualification testing at Extreme Test Conditions.
 Guaranteed by 100% Production Test Screening at Production Test Conditions.

2. Functional Description

The RF22 is a 100% CMOS ISM wireless transceiver with continuous frequency tuning over the complete 240–930
MHz band. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the RF22 and ideal
solution for battery powered applications.

The RF22 operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives
data packets. The receiver uses a singleconversion, image-reject mixer to downconvert the 2-level FSK/GFSK/OOK
modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted
to the digital domain by a high performance - ADC allowing filtering, demodulation, slicing, error correction, and
packet handling to be performed in the built-in DSP increasing the receiver’s performance and flexibility versus analog
based architectures. The demodulated signal is then output to the system MCU through a programmable GPIO or via
the standard SPI bus by reading the 64-byte RX FIFO.

A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and
receiver do not operate at the same time. The LO is generated by an integrated VCO and - Fractional-N PLL
synthesizer. The synthesizer is designed to support configurable data rates, output frequency, frequency deviation,
and Gaussian filtering at any frequency between 240–930 MHz. The transmit FSK data is modulated directly into the
- data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content.

The PA output power can be configured between +11 and +20 dBm in 3 dB steps. The PA is single-ended to allow for
easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and rampdown control to reduce
unwanted spectral spreading. This RF22 supports frequency hopping, TX/RX switch control, and antenna diversity
switch control to extend the link range and improve performance. Antenna diversity is completely integrated into the
RF22 and can improve the system link budget by 8–10 dB (according to published papers on Antenna Diversity)
resulting in substantial range increases depending on the environmental conditions. The +20 dBm power amplifier can
also be used to compensate for the reduced performance of a lower cost antenna or antenna with size constraints due
to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable
performance.

The RF22 is designed to work with a microcontroller, crystal, and a few passives to create a very low cost system as
shown Figure 1. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage
conditions from +1.8 to +3.6 V. A standard 3 or 4-pin SPI bus is used to communicate with the microcontroller. Three
configurable general purpose I/Os are available for use to tailor towards the needs of the system. A more complete list
of the available GPIO functions is shown in "8. Auxiliary Functions" on page 53 but just to name a few, microcontroller
clock output, Antenna Diversity, TRSW control, POR, and specific interrupts. A limited number of passive components
are needed to match the LNA and PA; refer to "9. Reference Design" on page 70 for the required component values at
different frequency ranges.

The application shown in Figure 1 is designed for a system with Antenna Diversity. The Antenna Diversity Control
Algorithm is completely integrated into the chip and is discussed further in "8.9. Antenna-Diversity" on page 66.

For a simpler application example not using Antenna Diversity see the "9. Reference Design" on page 70.

Version: 0.1 Date: 12/23/2008

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6

RF22

supply voltage

TR & ANT-DIV

Switch

C6

100p

L3L2

C3 C2

C7

100n

C4

L4

C5

C8

1u

VDD_RF

L1

TX

C1

Programmable load capacitors for X1 are integrated.

R1, L1-L5 and C1-C4 values depend on frequency band,
antenna impedance, output power and supply voltage range.

RXp

RXn

VR_IF

C10

1u

Figure1. +20dBm Application with Antenna Diversity and FHSS

2.1. Operating Modes

The RF22 provides several modes of operation which can be used to optimize the power consumption of the device
application. Depending upon the system communication protocol, the optimal trade-off between the radio wake time
and power consumption can be achieved.

Table 9 summarizes the modes of operation of the RF22. In general, any given mode of operation may be classified as
an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each
corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the
appropriate commands over the SPI in order to optimize the average current consumption. An “X” in any cell means
that: in the given mode of operation, that block can be independently programmed to be either ON or OFF, without
noticeably affecting the current consumption. The SPI circuit block includes the SPI interface and the register space.
The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator, and wake-up timer.
AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector.

C8

X1

30MHz

TU

LE

NIX

02

91

RF22

6

7

0
O

IP
G

Q
RIn

O
X

817161

8

2

1

O

O

IP

IP

G

G

S
n

SCLK

15

SDI

14

SDO

13

VDD_D

12

GND_D

11

01

9

G
ID_RV

C9

1u

ND
S

1

2

3

4

5

FER_

C
DA

1u

Version: 0.1 Date: 12/23/2008

GP1
GP2

GP3

GP4

GP5

VDD

microcontroller

VSS

Table9. Operating Modes

Mode Name

Digital LDO SPI 32 kHz OSC AUX 30 MHz XTAL PLL PA RX I

Shutdown OFF (Register contents lost) OFF OFF OFF OFF OFF OFF OFF 10 nA
Standby ON (Register contents retained) ON OFF OFF OFF OFF OFF OFF 400 nA
Sleep ON ON X OFF OFF OFF OFF 800 nA
Sensor ON X ON OFF OFF OFF OFF 1 A
Ready ON X X ON OFF OFF OFF 600 A
Tuning ON X X ON ON OFF OFF 9.5 mA
Transmit ON X X ON ON ON OFF 27 mA*
Receive ON X X ON ON OFF ON 18.5 mA

*Note: 27 mA at +11 dBm.

Circuit Blocks

VDD

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7

RF22

NW

O
DPMARAP

XTAL Settling

Time

~1ms

LA

0TLLP

S
TLLP

C
LLP

45us, may be skiped

XTAL Settling

Time

~1ms

YALEDD

PMARAPERP

PUPMARAP

LACLLP

0TLLP

S
TLLP

O
MXT

6us, Fixed

1.5Bits@DR

45us, may be skiped

TX Packet

Version: 0.1 Date: 12/23/2008

RX Packet

Configurable 0~70us, Default=20us

Configurable 5~20us, Recommended 5us

Configurable 0~310us, Recommended 100us

Configurable 0~70us, Default=20us

Configurable 0~310us, Recommended 100us

Figure2. TX Timing. Figure3. RX Timing

3. Controller Interface

3.1. Serial Peripheral Interface (SPI)

The RF22 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU can
also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which consists of a
Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA), as demonstrated
in Figure 4. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control registers. The R/W
select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it signifies a WRITE
transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the RF22
every eight clock cycles. The timing parameters for the SPI interface are shown in Table 10. The SCLK rate is flexible
with a maximum rate of 10 MHz.

Data

LSBMSB

SDI

SCLK

nSEL

Address

RW A5 A3 RW A7A6 xxxxA4 D0A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

Figure4. SPI Timing

Table10. Serial Interface Timing Parameters

Symbol Parameter Min (nsec) Diagram

tCH Clock high time 40

SCLK

tCL Clock low time 40
tDS Data setup time 20
tDH Data hold time 20
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50

SDI

SDO

t

tSS Select setup time 20
tSH Select hold time 50

nSEL

tSW Select high period 80

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t

SS

NE

t

t

CH

CL

t

tDSt

DD

DH

tSHt

DE

t

SW

8

RF22

To read back data from the RF22, the R/W bit must be set to 0 followed by the 7-bit address of the register from which
to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight positive edge
transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected
register will be available on the SDO output pin. The READ function is shown in Figure 5. After the READ function is
completed the SDO pin will remain at either logic 1 or logic 0 state depending on the last data bit clocked out (D0).
When nSEL goes high the SDO output pin will be pulled high by internal pull-up.

SDI

SCLK

SDO

nSEL

RW

=0

A6

A5

A4

A3

A1A2D7A0

D7

Figure5. SPI Timing—READ Mode

The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write transaction
is demonstrated in Figure 6 and burst read in Figure 7. As long as nSEL is held low, input data will be latched into the
RF22 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 7.

SDI

First Bit

RW

=1

A6

A5

A4

A3 A2=XA1D7A0

D5

D4

D6

=X

=X

=X

D5

D3

D4

D6
=X

=X

D6 D5 D4 D3 D2 D1 D0

D2

D3

=X

=X

=X

=X

=X

D7

D0

D1

=X

=X

=X

Version: 0.1 Date: 12/23/2008

Last BitFirst Bit

D0

D1

D2

=X

=X

=X

Last BitFirst Bit

D5

D3

D4

D6
=X

=X

=X

=X

Last Bit

D0

D1

D2

=X

=X

=X

SCLK

nSEL

Figure6. SPI Timing—Burst Write Mode

SDI

SCLK

SDO

nSEL

First Bit

RW

A5

A6

=0

A4

A3 A2

A1D7A0

=X

First Bit

D7

D6 D5 D4 D3 D2 D1 D0

Last Bit

D0

D1

D2

D3=X4D=X5D=XD6

=X

=X

=X

=X

D7 D6 D5 D4

D1 D0D2D3

Figure7. SPI Timing—Burst Read Mode

3.2. Operating Mode Control

There are four primary states in the RF22 radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 8). The
SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different
configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs.
"Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected. The TX and
RX state may be reached automatically from any of the IDLE states by setting the txon/rxon bits in "Register 07h.
Operating Mode and Function Control 1". Table 11 shows each of the operating modes with the time required to reach
either RX or TX mode as well as the current consumption of each mode.

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9

RF22

The output of the LPLDO is internally connected in parallel to the output of the main digital regulator (and is available
externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks, including the
digital modem, crystal oscillator, and SPI and register space. The LPLDO has extremely low quiescent current
consumption but limited current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes.

SHUT DWN

IDLE*

TX RX

*Five Different Options for IDLE

Figure8. State Machine Diagram

Table11. Operating Modes

State/Mode xtal pll wt LBD or TS Response time to Current in State /Mode [μA]

TX RX
Shut Down State X X X X 16.21 ms 16.21 ms
Idle States:

Standby Mode
Sleep Mode
Sensor Mode

Ready Mode 1 0 X X 210 s 210 s 600 A
Tune Mode 1 1 X X 200 s 200 s 9.5 mA
TX State 1 1 X X NA 200 s 60 mA @ +20 dBm, 27 mA @ +11 dBm
RX State 1 1 X X 200 s NA 18.5 mA

0 0 0 0 400 nA
0 0 1 0 800 nA
0 0 X 1

1.21 ms

1.21 ms

Version: 0.1 Date: 12/23/2008

1 A

3.2.1. Shutdown State

The shutdown state is the lowest current consumption state of the device with nominally 5 nA of current consumption.
The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states
except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI
access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN.

3.2.2. Idle State

There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and
Function Control 1". All modes have a tradeoff between current consumption and response time to TX/RX mode. This
tradeoff is shown in Table 11. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will
default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP,
SENSOR, or STANDBY mode and to control the 32 kHz clock correctly.

3.2.2.1. STANDBY Mode

STANDBY mode has the lowest current consumption possible with only the LPLDO enabled to maintain the register
values. In this mode the registers can be accessed in both read and write mode. The standby mode can be entered by
writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0)
the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be
selected as an input to the GPIO in this mode as it will cause excess current consumption.

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RF22

3.2.2.2. SLEEP Mode

In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the
radio at specified intervals. See "8.6. Wake-Up Timer" on page 62 for more information on the Wake-Up-Timer. Sleep
mode is entered by setting enwt=1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has
occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also,
the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption.

3.2.2.3. SENSOR Mode

In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the
LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 and the temperature
sensor can be enabled by setting ents = 1 in "Register 07h. Operating Mode and Function Control 1". See "8.4.
Temperature Sensor" on page 59 and "8.5. Low Battery Detector" on page 61 for more information on these features. If
an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current
consumption.

3.2.2.4. READY Mode

READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode
the Crystal oscillator remains enabled reducing the time required to switch to the TX or RX mode by eliminating the
crystal start-up time. Ready mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control
1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled. This is done by
setting "Register 62h. Crystal Oscillator/Power-on-Reset Control" to a value of 02h. To exit ready mode, enamp2x (bit

2) of this register must be set back to 0.

3.2.2.5. TUNE Mode

In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the
fastest response to TX mode as the PLL will remain locked but it results in the highest current consumption. This mode
of operation is designed for Frequency Hopping Systems (FHS). Tune mode is entered by setting pllon = 1 in "Register
07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode; the internal state
machine automatically enables the crystal oscillator.

Version: 0.1 Date: 12/23/2008

3.2.3. TX State

The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating
Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states
from enabling the crystal oscillator to ramping up the PA to prevent unwanted spectral splatter. The following sequence
of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit.

1. Enable the Main Digital LDO and the Analog LDOs.

2. Start up crystal oscillator and wait until ready (controlled by timer).

3. Enable PLL.

4. Calibrate VCO (this action is skipped when the vcocal bit is “0”; default value is “1”).

5. Wait until PLL settles to required transmit frequency (controlled by timer).

6. Activate Power Amplifier and wait until power ramping is completed (controlled by timer).

7. Transmit Packet.

The first few steps may be eliminated depending on which IDLE mode the chip is configured to prior to setting the txon
bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. If the ambient temperature is constant
and the same frequency band is being used these functions may be skipped by setting the appropriate bits in "Register
55h. Calibration Control".

3.2.4. RX State

The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h. Operating
Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the

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11

RF22

IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode
when going from STANDBY mode to RX mode by setting the rxon bit:

1. Enable the Main Digital LDO and the Analog LDOs.

2. Start up crystal oscillator and wait until ready (controlled by timer).

3. Enable PLL.

4. Calibrate VCO (this action is skipped when the vcocal bit is “0”; default value is “1”).

5. Wait until PLL settles to required transmit frequency (controlled by timer).

6. Enable receive circuits: LNA, mixers, and ADC.

7. Calibrate ADC (RC calibration).

8. Enable receive mode in the digital modem.

Depending on the configuration of the radio all or some of the following functions will be performed automatically by the
digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including
sync word, header check, and CRC.

3.2.5. Device Status

Add R/W Function /Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

02 R Device Status ffovfl ffunfl rxffem headerr freqerr lockdet cps[1] cps[0] —

The operational status of the chip can be read from "Register 02h. Device Status".

3.2.6. Interrupts

The RF22 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller
that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be
generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below
occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h)
containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the next change in status is
detected. All of the interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers
(Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status
register. If the interrupt is not enabled when the event occurs inside of the chip it will not trigger the nIRQ pin, but the
status may still be read correctly at anytime in the Interrupt Status registers.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

03 R Interrupt Status 1 ifferr itxffafull itxffaem irxffafull iext ipksent ipkvalid icrcerror —
04 R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor —
05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror 00h
06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 01h

See “Register 03h. Interrupt/Status 1,” on page 94 and “Register 04h. Interrupt/Status 2,” on page 97 for a complete list
of interrupts.

Version: 0.1 Date: 12/23/2008

3.2.7. Device Code

The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. Notes

01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 00h DV

3.2.8. System Timing

The system timing for TX and RX modes is shown in Figures 2 and 3. The timing is shown transitioning from
STANDBY mode to TX mode and going automatically through the built-in sequencer of required steps. If a small range
of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial
power up of the device. The relevant system timing registers are shown below.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

53 R/W PLL Tune Time pllts[4:0] pllt0[2:0] 45h
54 R/W Reserved 1 X X X X X X X X 00h
55 R/W Calibration Control xtalstarthalf adccaldone enrcfcal rccal vcocaldp vcocal skipvco 04h

The VCO will automatically calibrate at every frequency change or power up. The VCO CAL may also be forced by

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12

RF22

(

+×=

()(

+×+

×

(

×

setting the vcocal bit. The 32.768 kHz RC oscillator is also automatically calibrated but the calibration may also be
forced. The enrcfcal will enable the RC Fine Calibration which will occur every 30 seconds. The rccal bit will force a
complete calibration of the RC oscillator which will take approximately 2 ms. The PLL T0 time is to allow for bias
settling of the VCO, the default for this should be adequate. The PLL TS time is for the settling time of the PLL, which
has a default setting of 200 s. This setting should be adequate for most applications but may be reduced if small
frequency jumps are used. For more information on the PLL register configuration options, see “Register 53h. PLL
Tune Time,” on page 139 and “Register 55h. Calibration Control,” on page 140.

3.2.9. Frequency Control

For calculating the necessary frequency register settings it is recommended that customers use the easy control
window in HopeRF’s Wireless Design Suite (WDS) or the Excel Calculator available on the product website. These
methods offer a simple method to quickly determine the correct settings based on the application requirements. The
following information can be used to calculate these values manually.

3.2.9.1. Carrier Generation

The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and
the clock of the (3
obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an
integer part (N) and a fractional part (F). In a generic sense the output frequency of the synthesizer is:

The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]),
and Frequency Modulation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK
modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further
in "3.2.9.4. Frequency Deviation" on page 28. Also, a fixed offset can be added to fine-tune the carrier frequency and
counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional
component. The equation for selection of the output frequency is shown below:

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h
74 R/W Frequency Offset 2 fo[9] fo[8] 00h
75 R/W Frequency Band Select sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h
76 R/W Nominal Carrier Frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh
77 R/W Nominal Carrier Frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h

rd order) - modulator. This modulator uses modulo 64000 accumulators. This design was made to

)

FNMHf

[]

++×+×=

240:4110

FNhbselMHzf

TX

10

OUT

= 110

TX

()

⎛

fbhbselMHzf

⎜
⎝

Version: 0.1 Date: 12/23/2008

)

)

fc

64000

]0:15[

⎞
⎟

⎠

The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2
divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency
Band Select". This effectively partitions the entire 240–930 MHz frequency range into two separate bands: High Band
(HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written
into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the
formula above. Table 12 demonstrates the selection of fb[4:0] for the corresponding frequency band.

After selection of the fb (N) the fractional component may be solved with the following equation:

64000

f

[]

fc

fb and fc are the actual numbers stored in the corresponding registers.

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=

0:15

TX

()

[]

fbhbselMHz

+×+×

240:4110

13

RF22

[][

(

××+

Table12. Frequency Band Selection

fb[4:0] Value N

0 24 240-249.9MHz 480-489.9MHz
1 25 250-259.9MHz 500-509.9MHz
2 26 260-269.9MHz 520-529.9MHz
3 27 270-279.9MHz 540-549.9MHz
4 28 280-289.9MHz 560-569.9MHz
5 29 290-299.9MHz 580-589.9MHz
6 30 300-309.9MHz 600-609.9MHz
7 31 310-319.9MHz 620-629.9MHz
8 32 320-329.9MHz 640-649.9MHz

9 33 330-339.9MHz 660-669.9MHz
10 34 340-349.9MHz 680-689.9MHz
11 35 350-359.9MHz 700-709.9MHz
12 36 360-369.9MHz 720-729.9MHz
13 37 370-379.9MHz 740-749.9MHz
14 38 380-389.9MHz 760-769.9MHz
15 39 390-399.9MHz 780-789.9MHz
16 40 400-409.9MHz 800-809.9MHz
17 41 410-419.9MHz 820-829.9MHz
18 42 420-429.9MHz 840-849.9MHz
19 43 430-439.9MHz 860-869.9MHz
20 44 440-449.9MHz 880-889.9MHz
21 45 450-459.9MHz 900-909.9MHz
22 46 460-469.9MHz 920-930MHz
23 47 470-479.9MHz 

hbsel=0 hbsel=1

The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the
correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture;
therefore, no frequency reprogramming is required when using the same TX frequency and switching between RX/TX
modes.

Frequency Band

Version: 0.1 Date: 12/23/2008

3.2.9.2. Easy Frequency Programming for FHSS

While Registers 73h–77h may be used to program the carrier frequency of the RF22, it is often easier to think in terms
of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some
timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by
programming a single register. Once the channel step size is set, the frequency may be changed by a single register
corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above.
Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting.
The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56
MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size.

]

=

TX

100:70:7

)

kHzfhchfhsFnomf

For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step size is set to 1
MHz using "Register 7Ah. Frequency Hopping Step Size". For example, if the "Register 79h. Frequency Hopping
Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and
channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to
change the frequency.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

79 R/W Frequency Hopping

Channel Select

7A R/W Frequency Hopping

Step Size

fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h

fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h

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14

RF22

[

×=Δ

Δ

(

[

×+×

=

3.2.9.3. Automatic Frequency Change

If registers 79h or 7Ah are changed in either TX or RX mode, then the state machine will automatically transition the
chip back to tune, change the frequency, and automatically go back to either TX or RX. This feature is useful to reduce
the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity,
reducing current consumption.

3.2.9.4. Frequency Deviation

The peak frequency deviation is configurable from ±1 to ±320 kHz. The Frequency Deviation (f) is controlled by the
Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When
enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will
remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviate from the nominal
center channel carrier frequency by +/- f:

[]

fd

= f=peak deviation

0:8

625

]

f

Hz

Δf

Hzfdf 6250:8

Version: 0.1 Date: 12/23/2008

f

TX

Frequency

The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation
may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1.
Modulation Type" on page 32 for further details.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h
72 R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 43h

3.2.9.5. Frequency Offset Adjustment

When the AFC is disabled the Frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The
Frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency.
This register is a signed register so in order to get a negative offset you will need to take the twos complement of the
positive offset number. The offset can be calculated by the following:

[]

0:9+×=

fo

setDesiredOff

()

hbselHz

Time

)

]

0:9125.156 fohbselHzsetDesiredOff

125.156

The adjustment range in high band is: ±160 kHz, and adjustment range in low band is: ±80 kHz. For example to
compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band

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15

RF22

mode the fo[9:0] register should be set to 360h.
When AFC is enabled the same registers can be used to read the offset value as automatically obtained by the AFC.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. Notes

73 R/W Frequency Offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 73
74 R/W Frequency Offset fo[9] fo[8] 00h

3.2.9.6. Auto Frequency Control (AFC)

The receiver supports automatic frequency control (AFC) to compensate for frequency differences between the
transmitter and receiver reference frequencies. These differences can be caused by the absolute accuracy and
temperature dependencies of the reference crystals. Due to frequency offset compensation in the modem, the receiver
is tolerant to frequency offsets up to 0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled,
the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a
wider range of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity versus carrier
offset and the impact of AFC are illustrated in Figure 9.

Sensitivity vs Carrier Frequency Offset

(Rb = 100 kHz, Fd = 50 kHz)

-86

-88

-90

-92

-94

-96

-98

-100

RX Sensitivity(dBm)

-102

-104

-100-50050100

Frequency Offset (kHz)

Figure9. Sensitivity vs. Carrier Frequency Offset

The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled, the Frequency
Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the
length needs to be long enough to settle the AFC. In general two bytes of preamble is sufficient to settle the AFC.
Disabling the AFC allows the preamble to be shortened. Note that with the AFC disabled, the preamble length must still
be long enough to settle the receiver and to detect the preamble (see "6.7. Preamble Length" on page 45). The AFC
corrects the detected frequency offset by changing the frequency of the Fractional-N PLL. At the end of the preamble
the AFC will freeze. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire the frequency
offset for the next packet. An automatic reset circuit prevents excessive drift by resetting the AFC loop when the tuning
exceeds 2 times the frequency deviation (as set by fd[8:0] in register 71h and 72h) in high band or 1 times the
frequency deviation in low band. This range can be halved by the “afcbd” bit in register 1Dh.

Version: 0.1 Date: 12/23/2008

AFC Disable

AFC Enable

In TX mode the "Register 73h. Frequency Offset 1" is used to provide an offset to the programmed transmit frequency.
This offset allows fine tuning of the transmit frequency to account for the variability of the TX reference frequency. Note
that reading this register shows the frequency offset calculated from the last AFC action not what was previously
written to the Frequency Offset register.

Frequency Correction

RX TX

AFC disabled Freq Offset Register Freq Offset Register
AFC enabled AFC Freq Offset Register

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16

RF22

[

×

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

1D R/W AFC Loop Gearshift

Override

3.2.10. TX Data Rate Generator

The data rate is configurable between 1–128 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in register 70h
should be set to 1. When higher data rates are used this bit should be set to 0.
The TX date rate is determined by the following formula:

The txdr register may be found in the following registers.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

6E R/W TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0Ah
6F R/W TX Data Rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] AAh

4. Modulation Options

4.1. Modulation Type

The RF22 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift
Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best
performance and cleanest modulation spectrum. Figure 10 demonstrates the difference between FSK and GFSK for a
Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. The frequency domain
plots demonstrate the spectral benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits
in "Register 71h. Modulation Mode Control 2". Note that it is also possible to obtain an unmodulated carrier signal by
setting modtyp[1:0] = 00.

modtyp[1:0] Modulation Source

00 Unmodulated Carrier
01 OOK
10 FSK
11 GFSK (enable TX Data CLK when direct mode is used)

afcbd enafc afcgearh[2] afcgearh[1] afcgearh[0] afcgearl[2] afcgearl[1] afcgearl[0] 40h

]

10:15

_

TXDR

[]

txdr

0:15

=

2

=

TXDR

1

⋅+

516

×

2_

MHz

MHztxdr

etxdtrtscal

516 ⋅+

Version: 0.1 Date: 12/23/2008

etxdtrtscal

TX Modulation Time Domain Waveforms -- FSK vs. GFSK

1.5

1.0

0.5

0.0

-0.5

SigData_FSK[0,: :]

-1.0

-1.5

1.0

0.5

0.0

-0.5

SigData_GFSK[0,::]

-1.0
50 100 150 200 250 300 350 400 450 500

0

time, usec

TX Modulation Spectrum -- FSK vs GFSK (Continuous PRBS)

-20

-40

-60

-80

ModSpectrum_FSK

-100

-20

-40

-60

-80

ModSpectrum_GFSK

-100

DataRate TxDev BT_Fi lter

64000.0

32000.0

0 50 100 150 200 250-50-100-150-200-250

freq, KHz

ModIndex

0.5

1.0

Figure10. FSK vs GFSK Spectrums

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17

RF22

4.2. Modulation Data Source

The RF22 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct
Mode, and from a PN9 mode. Furthermore, in Direct Mode, the TX modulation data may be obtained from several
different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2".

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 23h

dtmod[1:0] Modulation Source

00 Direct Mode using TX_Data via GPIO pin (GPIO needs programming accordingly also)
01 Direct Mode using TX_Data via SDI pin (only when nSEL is high)
10 FIFO Mode
11 PN9 (internally generated)

4.3. FIFO Mode

In FIFO mode the integrated FIFOs are used to transmit and receive the data. The FIFOs are accessed via "Register
7Fh. FIFO Access" with burst read/write capability. The FIFOs may be configured specific to the application packet size,
etc. (see "6. Data Handling and Packet Handler" on page 39 for further information). When in FIFO mode the chip will

automatically exit TX or RX State when either the ipksent or ipkvalid interrupt occurs. The chip will return to any of

other states based on the settings in "Register 07h. Operating Mode and Function Control 1". For instance if the chip is
put into TX mode and both the txon and pllon bits are set, the chip will transmit all of the contents of the FIFO and the
ipksent interrupt will occur. When this event occurs the chip will clear the txon bit and return to pllon or Tune Mode. If
no other bits are set in register 07h besides txon initially then the chip will return to the Idle state.
In RX mode the rxon bit will only be cleared if ipkvalid occurs. A CRC, Header, or Sync error will generate an interrupt
and the microcontroller will need to decide on the next action.

Version: 0.1 Date: 12/23/2008

4.4. Direct Mode

For legacy systems that have packet handling within an MCU or other baseband chip, it may not be desirable to use
the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In Direct Mode the TX
modulation data is applied to an input pin of the chip and processed in “real time” (i.e., not stored in a register for
transmission at a later time). There are various configurations for choosing which pin is used for the TX Data.
Furthermore, an additional input pin is required for the TX Data Clock if GFSK modulation is desired (only the TX Data
input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and
various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field.

trclk[1:0] TX Data Clock Configuration

00 No TX Clock (only for FSK)
01 TX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
10 TX Data Clock is available via SDO pin (only when nSEL is high)
11 TX Data Clock is available via the nIRQ pin

The eninv bit in Address 71h will invert the TX Data for testing purposes.

4.5. PN9 Mode

In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary
purpose of this mode is for use as a test mode to observe the modulated spectrum without having to load/provide data.

4.6. Synchronous vs. Asynchronous

In Asynchronous mode no clock is used to synchronize the data to the internal modulator. This mode can only be used
with FSK. The advantage of this mode that it saves a microcontroller pin because no data clock is required. The
disadvantage is that you don’t get the clean spectrum and limited BW of GFSK. If Asynchronous FSK is used the
TX_DR register should be set to its maximum value.

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18

RF22

nIRQ

Matching

VDD_RF

TX

RXp

RXn

VR_IF

DataCLK

XIN

SDN

RF22

ADC_REF

GPIO_0

nIRQ

nSEL

XOUT

SCLK

SDI

SDO

VDD_DIG

GND_DIG

GPIO_1

GPIO_2

VR_DIG

nSEL

SCK

MOSI

MISO

MOD

DATACLK

nRES

Direct synchronous modulation . Full
control over the standard SPI & using
interrupt. Bitrate clock and modulation

u

C

via GPIO's.

GPIO configuration
GP0 : power-on-reset (default)
GP1 : TX DATA clock output
GP2 : TX DATA input

Version: 0.1 Date: 12/23/2008

Matching

MOD(Data)

SDN

VDD_RF

TX

RXp

RXn

VR_IF

RF22

ADC_REF

XIN

GPIO_0

Figure11. Direct Synchronous Mode Example

nIRQ

XOUT

GPIO_1

nIRQ

GPIO_2

nSEL

SCLK

SDI

SDO

VDD_DIG

GND_DIG

VR_DIG

nSEL

SCK

MOSI

MISO

MOD

DATACLK

nRES

uC

Direct asynchronous FSK
modulation. Modulation data
via GPIO2, no data clock
needed in this mode .

GPIO configuration
GP0 : power-on-reset (default)
GP1 : TX DATA clock output
GP2 : TX DATA input

DataCLK

MOD(Data)

Figure 12. Direct Asynchronous Mode Example

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19

RF22

nIRQ

XIN

Matching

VDD_RF

TX

RXp

RXn

VR_IF

SDN

ADC_REF

GPIO_0

XOUT

GPIO_1

nIRQ

GPIO_2

nSEL

SCLK

SDI

SDO

VDD_DIG

GND_DIG

VR_DIG

Figure13. FIFO Mode Example

5. Internal Functional Blocks

This section provides an overview some of the key blocks of the internal radio architecture.

5.1. RX LNA

The input frequency range for the LNA is 240–930 MHz. The LNA provides gain with a noise figure low enough to
suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain
control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal
levels from sensitivity to +5 dBm with optimal performance.

5.2. RX I-Q Mixer

The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q
mixer that provides both I and Q channel outputs to the complex IF filter. The mixer consists of two doublebalanced
mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and
Q Intermediate Frequency (IF) outputs drive the complex filter. The receive LO signal is supplied by an integrated VCO
and PLL synthesizer operating between 240–930 MHz. The necessary quadrature LO signals are derived from the
divider at the VCO output.

nSEL

SCK

MOSI

MISO

uC

Version: 0.1 Date: 12/23/2008

FIFO mode utilizing internal
packet handler. Data loaded/
read through SPI into FIFO .

GPIO configuration
Not Utilized

5.3. Programmable Gain Amplifier

The Programmable Gain Amplifier (PGA) provides the necessary gain to boost the signal level into the Dynamic Range
of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI
range up to –30 dBm. The PGA is designed to have steps of 3 dB which are controlled by the AGC algorithm in the
digital modem.

5.4. ADC

The amplified I&Q IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current
consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of
band blockers.

5.5. Digital Modem

Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the
digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following functions:

 Channel Selection Filter
 TX Modulation

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20

RF22

 RX Demodulation
 AGC
 Preamble Detector
 Invalid Preamble Detector
 Radio Signal Strength Indicator (RSSI)
 Automatic Frequency Compensation (AFC)
 Packet Handling including EZMacTM features
 Cyclic Redundancy Check (CRC)

The digital Channel Filter and Demodulator are optimized for ultra low power consumption and are highly configurable.
Supported modulation types are GFSK, FSK, and OOK. The Channel Filter can be configured to support a large choice
of bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 1 up to
128 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time.

The configurable Preamble Detector is used to improve the reliability of the Sync-word detection. The Sync-word
detector is only enabled when a valid preamble is detected, significantly reducing the probability of false Sync-word
detection.

The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled,
the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow the receiver to
settle. The Invalid Preamble Detect interrupt can be used to save power and speed-up search in receive mode. It is
advised to mask the invalid preamble interrupt when Antenna Diversity is enabled.

The Received Signal Strength Indicator (RSSI) provides a measure of the signal strength received on the tuned
channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power
measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital Automatic Frequency
Control (AFC) in receive mode.

A comprehensive programmable Packet Handler including key features of HopeRFs’ EZMac
variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive
programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast,
group, and point-to-point communication.

A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if
the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in
each packet. A CRC is computed and appended at the tail of each transmitted packet and verified by the receiver to
confirm that no errors have occurred. The Packet Handler and CRC are extremely valuable features which can
significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller.

Version: 0.1 Date: 12/23/2008

TM

is integrated to create a

The digital modem includes the TX Modulator which converts the TX Data bits into the corresponding stream of digital
modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach
results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK,
considerably reducing the energy in the adjacent channels. The bandwidth-time product (BT) is 0.5 for all programmed
data rates.

5.6. Synthesizer

An integrated Sigma-Delta (-) Fractional-N PLL synthesizer capable of operating from 240–930 MHz is provided
on-chip. Using a - synthesizer has many advantages; it provides large amounts of flexibility in choosing data rate,
deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital
domain through the fractional divider which results in very precise accuracy and control over the transmit deviation.

The PLL and -modulator scheme is designed to support any desired frequency and channel spacing in the range
from 240–930 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The transmit data

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21

RF22

rate can be programmed between 1–128 kbps, and the frequency deviation can be programmed between ±1–160 kHz.
These parameters may be adjusted via registers as shown in "3.2.9. Frequency Control" on page 26.

Version: 0.1 Date: 12/23/2008

TX

RX

Fref=10M

PFD

CP

TX

Modulation

LPF

Selectable

Divider

VCO

N

Delta-

Sigma

Figure14. PLL Synthesizer Block Diagram

The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip spiral
inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired
output frequency band. The modulus of this divider stage is controlled dynamically by the output from the -
modulator. The tuning resolution of the - modulator is determined largely by the over-sampling rate and the number
of bits carried internally. The tuning resolution is sufficient to tune to the commanded frequency with a maximum
accuracy of 312.5 Hz anywhere in the range between 240–930 MHz.

5.6.1. VCO

The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0]
fields in "Register 75h. Frequency Band Select". A 2X VCO is utilized to help avoid problems due to frequency pulling,
especially when turning on the integrated Power Amplifier. In receive mode, the LO frequency is automatically shifted
downwards (without reprogramming) by the IF frequency of 937.5 kHz, allowing transmit and receive operation on the
same frequency. The VCO integrates the resonator inductor, tuning varactor, so no external VCO components are
required.

The VCO uses capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically
be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so
the VCO calibration may be skipped by setting the appropriate register.

5.7. Power Amplifier

The RF22 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between +11 to
+20 dBm. The output power is programmable in 3 dB steps through the txpow[1:0] field in "Register 6Dh. TX Power".

The PA design is single-ended and is implemented as a two stage class CE amplifier with efficiency in the range of
45–50% while transmitting at +20 dBm. The efficiency drops to approximately 20% when operating at +11 dBm. Due to
the high efficiency a simple filter is required on the board to filter the harmonics. The PA output is ramped up and down
to prevent unwanted spectral splatter.

5.7.1. Output Power Selection

The output power is configurable in 3 dB steps from +11 dBm to +20 dBm with the txpow[1:0] field in "Register 6Dh. TX
Power". Note that Frequency Hopping (FHSS) is required by the FCC when using an output power level of +20 dBm.
See "8.12. Analog and Digital Test Bus" on page 68 for further information on FHSS. The PA output is ramped up and

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22

RF22

down to prevent unwanted spectral splatter.

The extra output power can allow use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The higher
power setting of the chip achieves maximum possible range, but of course comes at the cost of higher TX current
consumption. However, depending on the duty cycle of the system the effect on battery life may be insignificant.
Contact HopeRF’s Support for help in evaluating this tradeoff.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

6D R/W TX Power txpow[1] txpow[0] 07h

txpow[1:0] Output Power

00 +11 dBm
01 +14 dBm
10 +17 dBm
11 +20 dBm

5.8. Crystal Oscillator

The RF22 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 1 ms. The design is
differential with the required crystal load capacitance integrated on-chip to minimize external components. All that is
required off-chip is the 30 MHz crystal blank.

The crystal load capacitance may be tuned to slightly adjust the frequency of the crystal oscillator. The tuning of the
crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load
Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The
xtalshift bit is a course shift in frequency but is not binary with xlc[6:0]. If AFC is disabled then the synthesizer
frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequency
Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.2.9. Frequency Control" on page 26.

The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the
GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system and
the BOM cost is reduced. The available clock frequencies (i.e., internal division ratios) and the GPIO configuration are
discussed further in "8.2. Microcontroller Clock " on page 54.
The RF22 may also be driven with an external 30 MHz clock signal through the XIN pin.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

09 R/W Crystal Oscillator Load

Capacitance

xtalshift xlc[6] xlc[5 xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 40h

Version: 0.1 Date: 12/23/2008

5.9. Regulators

There are a total of six regulators integrated onto the RF22. With the exception of the IF and Digital all regulators are
designed to operate with only internal decoupling. The IF and Digital regulators both require an external 1 F
decoupling capacitor. All of the regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V,
and produce a nominal regulated output voltage of +1.7 V ±5%. The internal circuitry nominally operates from this
regulated +1.7 V supply. The output stage of the PA is not connected internally to a regulator and is connected directly
to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the IF or DIG regulator
outputs.

6. Data Handling and Packet Handler

6.1. RX and TX FIFOs

Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 15. "Register 7Fh. FIFO
Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)" on page 20,

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23

RF22

to address 7Fh will write data to the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO.

TX FIFORX FIFO

TX FIFO Almost Full

Threshold

TX FIFO Almost Empty

Threshold

Figure15. FIFO Thresholds

The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches
these thresholds. The first threshold is the FIFO Almost Full threshold, txafthr[5:0]. The value in this register
corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO reaches
this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the
contents of the TX FIFO. The second threshold for TX is the FIFO Almost Empty Threshold, txaethr[5:0]. When the
data being shifted out of the TX FIFO reaches the Almost Empty threshold an interrupt will be generated. The
microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The Transceiver may be
configured so that when the TX FIFO is empty the chip will automatically move to the Ready state. In this mode the TX
FIFO Almost Empty Threshold may not be useful. This functionality is set by the ffidle bit in "Register 08h. Operating
Mode and Function Control 2".

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR

08 R/W Operating & Function Control 2 antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h
7C R/W TX FIFO Control 1 txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h
7D R/W TX FIFO Control 2 txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h

Version: 0.1 Date: 12/23/2008

RX FIFO Almost Full

Threshold

Def.

The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming
RX data reaches the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The
microcontroller will then need to read the data from the RX FIFO.

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR ef.

7E R/W RX FIFO Control X X rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h

Both the TX and RX FIFO’s may be cleared or reset with the ffclrtx and ffclrrx bits in "Register 08h. Operating Mode
and Function Control 2". All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt
Enable 1" and "Register 06h. Interrupt Enable 2". If the interrupts are not enabled the function will not generate an
interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.

6.2. Packet Configuration

When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Register 71h.
Modulation Mode Control 2" and "Register 30h. Data Access Control" through "Register 49h. Received Header 1"
control the configuration for Packet Handling. The usual fields for network communication (such as preamble,
synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data
payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers.

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24

RF22

"Register 30h. Data Access Control" through "Register 49h. Received Header 1" are used to set the different fields in
the packet structure. Automatically adding these fields to the data payload greatly reduces the amount of
communication between the microcontroller and the RF22 and therefore also reduces the required computational
power of the microcontroller.

The general packet structure is shown in Figure 16. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a one. All the fields have programmable lengths
to accommodate different applications. The most common CRC polynominals are available for selection.

Version: 0.1 Date: 12/23/2008

Preamble

1-512 Bytes 1-4 Bytes

Sync Word

TX Header

0-4Byte

Data

Packet Length

0 or 1 Byte

CRC

0 or 2

Bytes

Figure16. Packet Structure

An overview of the packet handler configuration registers is shown in Table 14. A complete register description can be
found in “12.1. Complete Register Table and Descriptions”.

6.3. Packet Handler TX Mode

If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning
to ready mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller
needs to command the chip to re-enter TX mode. Figure 17 provides an example transaction where the packet length
is set to three bytes.

1

data

⎫
⎪

This will be send in the first transmission

2

data

⎬
⎪

3

data

⎭

4

data

⎫

data
data

data
data
data

⎪

This will be send in the second transmission

5

⎬
⎪

6

⎭

7

⎫
⎪

This will be send in the third transmission

8

⎬
⎪

9

⎭

Figure17. Multiple Packets in TX Packet Handler

6.4. Packet Handler RX Mode

6.4.1. Packet Handler Disabled

When the packet handler is disabled certain portions of the packet handler are still required. Proper modem operation
requires preamble and sync, as shown in Figure 18. Bits after sync will be treated as raw data with no qualification.
This mode allows for the creation of a custom packet handler when the automatic qualification parameters are not
sufficient. Manchester encoding is supported but the use of data whitening, CRC, or header checks is not.

Preamble

SYNC

DATA

Figure18. Required RX Packet Structure with Packet Handler Disabled

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25

RF22

6.4.2. Packet Handler Enabled

When the packet handler is enabled, all the fields of the packet structure need to be configured. If multiple packets are
desired to be stored in the FIFO, then there are options available for the different fields that will be stored into the FIFO.
Figure 19 demonstrates the options and settings available when multiple packets are enabled. Figure 20 demonstrates
the operation of fixed packet length and correct/incorrect packets.

Transmission:

Register

Data

Register

Data

rx_multi_pk_en = 0

Header(s)

Length

RX FIFO Contents:

rx_multi_pk_en = 1

txhdlen = 0 txhdlen > 0

Version: 0.1 Date: 12/23/2008

fixpklenfixpklen

0

10 1

Data

FIFO

Data

LL

Data DataData Data

H

H

Figure19. Multiple Packets in RX Packet Handler

Initial state PK 1 OK

RX FIFO Addr.

0

63

Write

Pointer

RX FIFO Addr.

PK 2 OK

Write

Pointer

RX FIFO Addr.

0

H
L

Data

H

L

Data

63

Write

Pointer

0

H
L

Data

63

PK 3

ERROR

RX FIFO Addr.

0

H

L

Data

H
L

Data

H

L

Data

63

Write

Pointer

CRC
error

PK 4 OK

RX FIFO Addr.

0

H
L

Data

H

L

Data

H

L

Data

63

Write

Pointer

Figure20. Multiple Packets in RX with CRC or Header Error

Table13. RX Packet Handler Configuration

Data modes

FIFO_PH 10 1 option set option set option

dtmod[1:0]

FIFO 10 0 option

Direct 0X X set

enpacrx

Direct Data and

CLK IO

Preamble & Sync

word detection

Header Handling

set

—

set

— —

Data Storage in

set

FIFO

CRC Handling

—

Manchester and

option

option

Whitening

Manchester optional for sync-detection

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26

RF22

Table14. Packet Handler Registers

Addr R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

30 R/W Data Access Control enpacrx lsbfrst crcdonly * enpactx encrc crc[1] crc[0] 1Dh

31 R EzMAC status 0 rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent -

32 R/W Header Control 1 enbcast[3] enbcast[2] enbcast[1] enbcast[0] hdch[3] hdch[2] hdch[1] hdch[0] 0Ch

33 R/W Header Control 2

34 R/W Preamble Length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 07h

35 R/W Preamble Detection Control preath[4] preath[3] preath[2] preath[1] preath[0] spare spare spare 20h

36 R/W Sync Word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2Dh

37 R/W Sync Word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] D4h

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h

3A R/W Transmit Header 3 txhd[31] txhd[30] txhd[29] txhd[28] txhd[27] txhd[26] txhd[25] txhd[24] 00h

3B R/W Transmit Header 2 txhd[23] txhd[22] txhd[21] txhd[20] txhd[19] txhd[18] txhd[17] txhd[16] 00h

3C R/W Transmit Header 1 txhd[15] txhd[14] txhd[13] txhd[12] txhd[11] txhd[10] txhd[9] txhd[8] 00h

3D R/W Transmit Header 0 txhd[7] txhd[6] txhd[5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h

3E R/W Transmit Packet Length pklen[7] pklen[6] pklen[5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h

3F R/W Check Header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h

40 R/W Check Header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h

41 R/W Check Header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h

42 R/W Check Header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h

43 R/W Header Enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] FFh

44 R/W Header Enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] FFh

45 R/W Header Enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] FFh

46 R/W Header Enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] FFh

47 R Received Header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] —

48 R Received Header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] —

49 R Received Header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] —

4A R Received Header 0 rxhd[7] rxhd[6] rxhd[5] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] —

4B R Received Packet Length rxplen[7] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] —

hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h

Version: 0.1 Date: 12/23/2008

6.5. Data Whitening, Manchester Encoding, and CRC

Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more
uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output from the
built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers the original
data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission and good
synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but the actual
datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate when using
Manchester encoding is limited to 64 kbps. Data Whitening and Manchester encoding can be selected with "Register
70h. Modulation Mode Control 1". The CRC is configured via "Register 30h. Data Access Control".

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RF22

Manchester

Whitening

Version: 0.1 Date: 12/23/2008

CRC (data only = 1)

DATA CRC

Preamble SYNC

HEADER/
ADDRESS

CRC

PK

Length

6.6. Preamble Detector

The RF22 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using
the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2.
Packet Configuration”. The preamble detection threshold, preath[4:0] as set in "Register 35h. Preamble Detection
Control 1” is in units of 4 bits. The preamble detector searches for a preamble pattern with a length of preath[4:0].

When a false preamble detect occurs, the receiver will continuing searching for the preamble when no sync word is
detected.

The Preamble Detector output may be programmed onto one of the GPIOs or read in the Interrupt Status registers.

6.7. Preamble Length

The required preamble length threshold will depend on when the receive mode is entered in relation to the transmitted
packet. When the receiver is enabled long before the arrival of the packet, then a short preamble detection threshold
might result in false detects on the received noise before the actual preamble arrives. In this case, it is recommended
to program a 16 or 20 bit detection threshold. When antenna diversity is enabled, it is advised to use the default
preamble detection threshold (16 bit). When the receiver is synchronously enabled just before the start of the packet,
then a shorter preamble detection threshold might be chosen (e.g., 8 bit).

The required preamble length is determined from the sum of the receiver settling time and the preamble detection
threshold. The receiver settling time is listed in Table 15.

Table15. Minimum Receiver Settling Time

Mode

(G)FSK AFC Disabled 1 byte 2 byte 3 byte

(G)FSK AFC Enabled 2 byte 3 byte 4 byte

(G)FSK AFC Disabled +Antenna Diversity

Enabled

(G)FSK AFC Enabled +Antenna Diversity

Enabled

OOK 2 byte 3 byte 4 byte

OOK + Antenna Diversity Enabled 8 byte — 8 byte

Note: The recommended preamble length may be shortened when occasional packet errors are allowed.

Approximate receiver

settling time

1 byte — 7 byte

2 byte — 8 byte

Recommended preamble

length with 8-bit detection

threshold

Recommended preamble

length with 16-bit detection

threshold

6.8. Invalid Preamble Detector

When scanning channels in a Frequency Hopping System, it is desirable to determine if a channel is valid in the
minimum amount of time. The preamble detector can output an invalid preamble detect signal. When an error is
detected in the preamble, the Invalid Preamble Detect signal (nPQD) is asserted, indicating an invalid channel. The
signal can be used to qualify the channel without requiring the full preamble to be received. The Preamble Detect and
Invalid Preamble Detect signals are available in "Register 03h. Interrupt/Status 1" and "Register 04h. Interrupt/ Status
2".

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