Rainbow Electronics RF12B User Manual

RF12B

RF12B Universal ISM Band
FSK Transceiver

DESCRIPTION

Hope’s RF12B is a single chip, low power,

multi-channel FSK transceiver designed for use in

applications requiring FCC or ETSI conformance for

unlicensed use in the 433, 868 and 915 MHz bands. The

RF12B transceiver produces a flexible, low cost, and highly

integrated solution that does not require production

alignments. The chip is a complete analog RF and baseband

transceiver including a multi-band PLL synthesizer with PA,

LNA, I/Q down converter mixers, baseband filters and

amplifiers, and an I/Q demodulator. All required RF functions

are integrated. Only an external crystal and bypass filtering

are needed for operation.

The RF12B features a completely integrated PLL for easy RF design, and its rapid settling time

allows for fast frequency-hopping, bypassing multi-path fading and interference to achieve robust

wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The

receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and

crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation.

Consequently, no external components (except crystal and decoupling) are needed in most applications.

The RF12B dramatically reduces the load on the microcontroller with the integrated digital data

processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data

register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost)

crystal. To minimize the system cost, the RF12B can provide a clock signal for the microcontroller,

avoiding the need for two crystals.

For low power applications, the RF12B supports low duty cycle operation based on the internal

wake-up timer.

FUNCTIONAL BLOCK DIAGRAM

RF12B

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RF12B

FEATURES

z Fully integrated (low BOM, easy design-in)

z No alignment required in production

z Fast-settling, programmable, high-resolution PLL synthesizer

z Fast frequency-hopping capability

z High bit rate (up to 115.2 kbps in digital mode and 256 kbps

z in analog mode)

z Direct differential antenna input/output

z Integrated power amplifier

z Programmable TX frequency deviation (15 to 240 kHz)

z Programmable RX baseband bandwidth (67 to 400 kHz)

z Analog and digital RSSI outputs

z Automatic frequency control (AFC)

z Data quality detection (DQD)

z Internal data filtering and clock recovery

z RX synchron pattern recognition

z SPI compatible serial control interface

z Clock and reset signals for microcontroller

z 16 bit RX Data FIFO

z Two 8 bit TX data registers

z Low power duty cycle mode

z Standard 10 MHz crystal reference

z Wake-up timer

z 2.2 to 3.8 V supply voltage

z Low power consumption

z Low standby current (0.3 µA)

z Supports very short packets (down to 3 bytes)

z Excellent temperature stability of the RF parameters

TYPICAL APPLICATIONS

z Remote control

z Home security and alarm

z Wireless keyboard/mouse and other PC peripherals

z Toy controls

z Remote keyless entry

z Tire pressure monitoring

z Tel e me t ry

z Personal/patient data logging

z Remote automatic meter reading

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RF12B

DETAILED FEATURE-LEVEL DESCRIPTION

The RF12B FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and

915 MHz. The device facilitates compliance with FCC and ETSI requirements.

The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a

minimal number of external components in a typical application. The RF12B incorporates a fully

integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switch-able gain, I/Q down

converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter.

PLL

The programmable PLL synthesizer determines the operating frequency, while preserving accuracy

based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of

multiple channels in any of the bands.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and can directly drive a loop antenna

with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly

trimming procedures and the so-called “hand effect”.

LNA

The LNA has approximately 250 Ohm input impedance, which functions well with the proposed

antennas.

If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to

provide the correct matching and to minimize the noise figure of the receiver.

The LNA gain can be selected in four steps (between 0 and -20dB relative to the highest gain)

according to RF signal strength. It can be useful in an environment with strong interferers.

Baseband Filters

The receiver bandwidth is selectable by

programming the bandwidth (BW) of the

baseband filters. This allows setting up the

receiver according to the characteristics of

the signal to be received.

An appropriate bandwidth can be

chosen to accommodate various FSK

deviation, data rate and crystal tolerance

requirements. The filter structure is 7th order

Butterworth low-pass with 40 dB suppression

at 2*BW frequency. Offset cancellation is

done by using a high-pass filter with a cut-off

frequency below 7 kHz.

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RF12B

Data Filtering and Clock Recovery

Output data filtering can be completed by an external capacitor or by using digital filtering according

to the final application.

Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The

resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen

according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO

can not be used in this mode and clock is not provided for the demodulated data.

Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode

there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock

the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow

mode, its noise immunity is very high, but it has slower settling time and requires more accurate data

timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode.

The CR starts in fast mode, then after locking it automatically switches to slow mode.

(Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there

is no need for setting the correct bit rate.)

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal

strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI

settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital

RSSI can be monitored by reading the status register.

Analog RSSI Voltage vs. RF Input Power

P1 -65 dBm 1300 mV

P2 -65 dBm 1000 mV

P3 -100 dBm 600 mV

P4 -100 dBm 300 mV

DQD

The operation of the Data Quality Detector is based on counting the spikes on the unfiltered received

data. High output signal indicates an operating FSK transmitter within baseband filter bandwidth from the

local oscillator. DQD threshold parameter can be set by using the Data Filter Command.

AFC

By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the

TX/RX offset in discrete steps, allowing the use of:

z Narrower receiver bandwidth (i.e. increased sensitivity)

z Higher data rate

z Inexpensive crystals

Crystal Oscillator

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RF12B

The RF12B has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for

the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and

programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.

The transceiver can supply a clock signal for the microcontroller; so accurate timing is possible

without the need for a second crystal.

When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the

Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses (“clock

tail”) for the microcontroller to let it go to idle or sleep mode. If this clock output is not used, turn the output

buffer off by the Power Management Command.

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below

a programmable threshold level. The detector circuit has 50mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA typical) and can be programmed

from 1 ms to several days with an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When

the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a

quick calibration (a few milliseconds) to facilitate accurate wake-up timing even in case of changing

ambient temperature and supply voltage.

Event Handling

In order to minimize current consumption, the transceiver supports different power saving modes.

Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up

timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the

serial interface).

If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used

to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The

source of the interrupt can be read out from the transceiver by the microcontroller through the SDO

pin.

Interface and Controller

An SPI compatible serial interface lets the user select the frequency band, center frequency of the

synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock,

wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these

auxiliary functions can be disabled when not needed. All parameters are set to default after power-on;

the programmed values are retained during sleep mode. The interface supports the read-out of a

status register, providing detailed information about the status of the transceiver and the received data.

The transmitter block is equipped with two 8 bit wide TX data registers. It is possible to write 8 bits

into the register in burst mode and the internal bit rate generator transmits the bits out with the

predefined rate. For further details, see the TX Register Buffered Data Transmission section.

It is also possible to store the received data bits into a FIFO register and read them out in a

buffered mode.

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RF12B

)

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)

)

)

)

)

A

r

A

)

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin Name Type Function

1 SDI DI Data input of the serial control interface (SPI compatible
2 SCK DI Clock input of the serial control interface
3 nSEL DI Chip select input of the serial control interface (active low
4 SDO DO Serial data output with bus hold
5 nIRQ DO Interrupt request output (active low

FSK DI Transmit FSK data input (internal pull up resistor 133 k
DATA DO Received data output (FIFO not used

6

nFFS DI

DLCK DO Received data clock output (Digital filter used, FIFO not used
CFIL AIO External data filter capacitor connection (Analog filter used

7

FFIT DO

8 CLK DO Microcontroller clock output

XTL AIO Crystal connection (the other terminal of crystal to VSS) or external reference input

9

REF
10 nRES DIO Open drain reset output with internal pull-up and input buffer (active low)
11 VSS S Ground reference voltage
12 RF2 AIO RF differential signal input/output
13 RF1 AIO RF differential signal input/output
14 VDD S Positive supply voltage
15

16

Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O
settings of the transceiver.

RSSI AO Analog RSSI output
nINT DI Interrupt input (active low
VDI DO Valid data indicator output

FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration

FIFO interrupt (active high) Number of the bits in the RX FIFO has reached the

IO External reference input. Use 33 pF series coupling capacito

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RF12B

PIN6(FSK/DATA/nFFS) internal structure PIN10(nRES) internal structure

T ypical Application

Typical application with FIFO usage

Transmit mode

el=0 in Configuration Setting Command

Transmit mode

el=1 in Configuration Setting Command

Receive mode

ef=0 in Configuration Setting Command

Receive mode

ef=1 in Configuration Setting Command

Pin 6

TX Data input

nFFS input (TX Data register can be accessed)

RX Data output RX Data clock output

nFFS input (RX Data FIFO can be accessed) FFIT output

Pin 7

-

-

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RF12B

V

(

GENERAL DEVICE SPECIFICATION

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units

V

dd

V

V

oc

I

in

ESD Electrostatic discharge with human body model 1000 V

T

st

Recommended Operating Range

Symbol Parameter Min

V

dd

V

ocDC

V

ocAC

T

op

Positive supply voltage -0.5 6 V

Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V

in

Voltage on open collector outputs (RF1, RF2) -0.5

+1.5

dd

Note 1)

Input current into any pin except VDD and VSS -25 25 mA

Storage temperature -55 125

Positive supply voltage 2.2

DC voltage on open collector outputs (RF1, RF2) V

AC peak voltage on open collector outputs (RF1, RF2)

Vdd-1.5

(Note 2)

Ambient operating temperature -40

V

℃

Max Units

3.8 V

+1.5

dd

V

+1 .5

dd

85

V

V

℃

Note 1: Cannot be higher than 7 V.
Note 2: Cannot be lower than 1.2 V.

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range. Typical conditions: Top= 27℃; Vdd=Voc=2.7V)

DC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units

433 MHz band 15 17

868 MHz band 16 18

915 MHz band

17 19

mA

433 MHz band 22 24

868 MHz band 23 25 I

mA

915 MHz band 24 26

433 MHz band 11 13

868 MHz band 12 14 I

915 MHz band

13 15

mA

0.5 µA

Crystal oscillator on

(Note 3)

0.62 1.2 mA

I

dd_TX_0

dd_TX_PMAX

dd_RX

I

pd

I

lb

I

wt

I

x

Supply current

(TX mode, P

= 0 dBm)

out

Supply current

(TX mode, P

out

= P

max

)

Supply current

(RX mode)

Standby current (Sleep mode) All blocks disabled 0.3 µA

Low battery voltage detector current

consumption

Wake-up timer current consumption 1.5 µA

Idle current

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RF12B

A

V

lb

V

lba

V

il

V

ih

I

il

I

ih

V

ol

V

oh

Low battery detect threshold

Low battery detection accuracy 0 5 %

Digital input low level voltage 0.3*V

Digital input high level voltage 0.7*Vdd V

Digital input current Vil = 0 V -1 1 µA

Digital input current Vih = Vdd, Vdd = 3.8 V -1 1 µA

Digital output low level Iol = 2 mA 0.4 V

Digital output high level Ioh = -2 mA Vdd-0.4 V

Programmable in 0.1V

steps

2.2 3.7 V

dd

V

AC Characteristics (PLL parameters)

Symbol Parameter Conditions/Notes Min Typ Max Units

f

PLL reference frequency (Note 1) 9 10 11 MHz

ref

Receiver LO/Transmitter

f

o

carrier frequency

PLL lock time

t

lock

t

PLL startup time With a running crystal oscillator 200 300 us

st, P

433 MHz band, 2.5 kHz resolution 430.24 439.75

868 MHz band, 5.0 kHz resolution 860.48 879.51

915 MHz band, 7.5 kHz resolution 900.72

Frequency error < 1kHz

30 us

929.27

MHz

AC Characteristics (Receiver)

Symbol Parameter Conditions/Notes Min Typ Max Units

mode 0 60 67 75

mode 1 120 134 150

BW Receiver bandwidth

BR

BRA

FC

IIP3

IIP3

IIP3

IIP3

FSK bit rate With internal digital filters 0.6 115.2 kbps

RX

FSK bit rate With analog filter 256 kbps

RX

Receiver Sensitivity BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 2) -109 -103 dBm

P

min

AFC locking range

range

Input IP3 In band interferers in high bands (868, 915 MHz) -21 dBm

inh

Input IP3

outh

IIP3 (LNA –6 dB

inl

gain)

IIP3 (LNA –6 dB

outl

gain)

Maximum input

P

max

power

RF input

C

in

capacitance

RSSI accuracy +/-5 dB

RS

a

RSSI range 46 dB

RS

r

mode 2 180 200 225

mode 3 240 270 300

mode 4 300 340 380

mode 5 360 400 450

df

: FSK deviation in the received signal

FSK

Out of band interferers

l f-fo l > 4 MHz

In band interferers in low band (433 MHz) -15 dBm

Out of band interferers

l f-fo l > 4 MHz

LNA: high gain 0 dBm

1 pF

0.8*df

FSK

-18 dBm

-12 dBm

kHz

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RF12B

C

RS

RS

P

Filter capacitor for

ARSSI

ARSSI

RSSI programmable

step

level steps

DRSSI response

resp

time

Receiver spurious

sp_rx

emission

1 nF

6 dB

Until the RSSI signal goes high after the input signal

exceeds the preprogrammed limit

-60 dBm

AC Characteristics (Transmitter)

Symbol

I

OUT

P

max_50

P

max_ant

P

P

P

C

Q

L

BR

BRA

df

Parameter

Open collector output DC current Programmable

Max. output power delivered to 50

Ohm load over a suitable matching

network (Note 4)

Max. EIRP with suitable selected

PCB antenna. (Note 6, 7)

Typical output power Selectable in 3 dB steps (Note 8)

out

Spurious emission

sp

l f-f

l > 1 MHz

sp

Harmonic suppression

harm

Output capacitance (set by the

o

automatic antenna tuning circuit)

Quality factor of the output

o

capacitance

Output phase noise

out

FSK bit rate Via internal TX data register

TX

FSK bit rate TX data connected to the FSK input

TX

FSK frequency deviation Programmable in 15 kHz steps

fsk

Conditions/Notes Min Typ Max Units

In 433 MHz band

In 868 / 915 MHz bands

In 433 MHz band with monopole

antenna with matching network (Note 4)

In 868 / 915 MHz bands (Note 5)

At max power 50 Ohm load (Note 4)

With PCB antenna (Note 5)

At max power 50 Ohm load (Note 4)

With PCB antenna (Note 5)

In 433 MHz band

In 868 / 915 MHz bands

In 433 MHz band

In 868 / 915 MHz bands

100 kHz from carrier, in 868 MHz band

1 MHz from carrier, in 868 MHz band

C

ARRSI

= 4.7 nF

500 us

0.5 6 mA

7

dBm

5

7

dBm

7

P

-21 P

max

max

dBm

-55 dBc

-60 dBc

-35 dBc

-42 dBc

2 2.6 3.2

pF

2.1 2.7 3.3

13 15 17

8 10 12

-80
dBc/Hz

-103

172 kbps

256 kbps

15 240 kHz

AC Characteristics (Turn-on/Turnaround timings)

Symbol Parameter Conditions/Notes Min Typ MaxUnits

t

sx

Crystal oscillator startup time

Transmitter turn-on time

T

tx_XTAL_ON

Receiver turn-on time

T

rx_XTAL_ON

Transmitter – Receiver turnover time

T

tx_rx_SYNT_ON

Receiver – Transmitter turnover time

T

rx_tx_SYNT_ON

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Crystal ESR < 100 Ohm

Synthesizer off, crystal oscillator on with

10 MHz step

Synthesizer off, crystal oscillator on with

10 MHz step

Synthesizer and crystal oscillator on

during TX/RX change with 10 MHz step

Synthesizer and crystal oscillator on

during RX/TX change with 10 MHz step

1 5 ms

250 us

250 us

150 us

150 us

RF12B

A

AC Characteristics (Others)

Symbol Parameter Conditions/Notes Min Typ Max Units

Programmable in 0.5 pF steps, tolerance

+/- 10%

fter Vdd has reached 90% of final value

(Note 9)

8.5 16 pF

100 ms

C

t

Crystal load capacitance,

xl

see crystal selection guide

Internal POR timeout

POR

t

Wake-up timer clock period

PBt

C

Digital input capacitance

in, D

t

Digital output rise/fall time

r, f

Calibrated every 30 seconds

15 pF pure capacitive load

0.95 1.05 ms

2 pF

10 ns

AC Characteristics (continued)

Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing

and frequency parameters will change accordingly.

Note 2: See the BER diagrams in the measurement results section for detailed information.

Note 3: Measured with disabled clock output buffer. This current can be decreased by enabling the low

power mode of the crystal oscillator. See PLL Setting Command and Power Management Command for

details.

Note 4: See Reference design with 50 Ohm matching network for details.

Note 5: See Reference design with resonant PCB antenna (BIFA) for details.

Note 6: Supposing identical antenna with RF12B in RX mode, the outdoor RF link range will be

approximately 120 meters indoor and 450 meters outdoor.

Note 7: Optimal antenna admittance/impedance:

RF12B Yantenna [S] Zantenna [Ohm] Lantenna [nH]

433 MHz 1.4E-3 - j7.1E-3 27 + j136 52.00

868 MHz 2E-3 - j1.5E-2 8.7 + j66 12.50

915 MHz 2.2E-3 - j1.55E-2 9 + j63 11.20

Note 8: Adjustable in 8 steps.

Note 9: During this period, commands are not accepted by the chip.

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