Rainbow Electronics RF12B User Manual

RF12B

RF12B Universal ISM Band
FSK Transceiver

DESCRIPTION

Hope’s RF12B is a single chip, low power,

multi-channel FSK transceiver designed for use in

applications requiring FCC or ETSI conformance for

unlicensed use in the 433, 868 and 915 MHz bands. The

RF12B transceiver produces a flexible, low cost, and highly

integrated solution that does not require production

alignments. The chip is a complete analog RF and baseband

transceiver including a multi-band PLL synthesizer with PA,

LNA, I/Q down converter mixers, baseband filters and

amplifiers, and an I/Q demodulator. All required RF functions

are integrated. Only an external crystal and bypass filtering

are needed for operation.

The RF12B features a completely integrated PLL for easy RF design, and its rapid settling time

allows for fast frequency-hopping, bypassing multi-path fading and interference to achieve robust

wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The

receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and

crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation.

Consequently, no external components (except crystal and decoupling) are needed in most applications.

The RF12B dramatically reduces the load on the microcontroller with the integrated digital data

processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data

register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost)

crystal. To minimize the system cost, the RF12B can provide a clock signal for the microcontroller,

avoiding the need for two crystals.

For low power applications, the RF12B supports low duty cycle operation based on the internal

wake-up timer.

FUNCTIONAL BLOCK DIAGRAM

RF12B

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RF12B

FEATURES

z Fully integrated (low BOM, easy design-in)

z No alignment required in production

z Fast-settling, programmable, high-resolution PLL synthesizer

z Fast frequency-hopping capability

z High bit rate (up to 115.2 kbps in digital mode and 256 kbps

z in analog mode)

z Direct differential antenna input/output

z Integrated power amplifier

z Programmable TX frequency deviation (15 to 240 kHz)

z Programmable RX baseband bandwidth (67 to 400 kHz)

z Analog and digital RSSI outputs

z Automatic frequency control (AFC)

z Data quality detection (DQD)

z Internal data filtering and clock recovery

z RX synchron pattern recognition

z SPI compatible serial control interface

z Clock and reset signals for microcontroller

z 16 bit RX Data FIFO

z Two 8 bit TX data registers

z Low power duty cycle mode

z Standard 10 MHz crystal reference

z Wake-up timer

z 2.2 to 3.8 V supply voltage

z Low power consumption

z Low standby current (0.3 µA)

z Supports very short packets (down to 3 bytes)

z Excellent temperature stability of the RF parameters

TYPICAL APPLICATIONS

z Remote control

z Home security and alarm

z Wireless keyboard/mouse and other PC peripherals

z Toy controls

z Remote keyless entry

z Tire pressure monitoring

z Tel e me t ry

z Personal/patient data logging

z Remote automatic meter reading

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RF12B

DETAILED FEATURE-LEVEL DESCRIPTION

The RF12B FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and

915 MHz. The device facilitates compliance with FCC and ETSI requirements.

The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a

minimal number of external components in a typical application. The RF12B incorporates a fully

integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switch-able gain, I/Q down

converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter.

PLL

The programmable PLL synthesizer determines the operating frequency, while preserving accuracy

based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of

multiple channels in any of the bands.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and can directly drive a loop antenna

with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly

trimming procedures and the so-called “hand effect”.

LNA

The LNA has approximately 250 Ohm input impedance, which functions well with the proposed

antennas.

If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to

provide the correct matching and to minimize the noise figure of the receiver.

The LNA gain can be selected in four steps (between 0 and -20dB relative to the highest gain)

according to RF signal strength. It can be useful in an environment with strong interferers.

Baseband Filters

The receiver bandwidth is selectable by

programming the bandwidth (BW) of the

baseband filters. This allows setting up the

receiver according to the characteristics of

the signal to be received.

An appropriate bandwidth can be

chosen to accommodate various FSK

deviation, data rate and crystal tolerance

requirements. The filter structure is 7th order

Butterworth low-pass with 40 dB suppression

at 2*BW frequency. Offset cancellation is

done by using a high-pass filter with a cut-off

frequency below 7 kHz.

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RF12B

Data Filtering and Clock Recovery

Output data filtering can be completed by an external capacitor or by using digital filtering according

to the final application.

Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The

resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen

according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO

can not be used in this mode and clock is not provided for the demodulated data.

Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode

there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock

the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow

mode, its noise immunity is very high, but it has slower settling time and requires more accurate data

timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode.

The CR starts in fast mode, then after locking it automatically switches to slow mode.

(Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there

is no need for setting the correct bit rate.)

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal

strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI

settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital

RSSI can be monitored by reading the status register.

Analog RSSI Voltage vs. RF Input Power

P1 -65 dBm 1300 mV

P2 -65 dBm 1000 mV

P3 -100 dBm 600 mV

P4 -100 dBm 300 mV

DQD

The operation of the Data Quality Detector is based on counting the spikes on the unfiltered received

data. High output signal indicates an operating FSK transmitter within baseband filter bandwidth from the

local oscillator. DQD threshold parameter can be set by using the Data Filter Command.

AFC

By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the

TX/RX offset in discrete steps, allowing the use of:

z Narrower receiver bandwidth (i.e. increased sensitivity)

z Higher data rate

z Inexpensive crystals

Crystal Oscillator

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RF12B

The RF12B has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for

the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and

programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.

The transceiver can supply a clock signal for the microcontroller; so accurate timing is possible

without the need for a second crystal.

When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the

Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses (“clock

tail”) for the microcontroller to let it go to idle or sleep mode. If this clock output is not used, turn the output

buffer off by the Power Management Command.

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below

a programmable threshold level. The detector circuit has 50mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA typical) and can be programmed

from 1 ms to several days with an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When

the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a

quick calibration (a few milliseconds) to facilitate accurate wake-up timing even in case of changing

ambient temperature and supply voltage.

Event Handling

In order to minimize current consumption, the transceiver supports different power saving modes.

Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up

timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the

serial interface).

If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used

to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The

source of the interrupt can be read out from the transceiver by the microcontroller through the SDO

pin.

Interface and Controller

An SPI compatible serial interface lets the user select the frequency band, center frequency of the

synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock,

wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these

auxiliary functions can be disabled when not needed. All parameters are set to default after power-on;

the programmed values are retained during sleep mode. The interface supports the read-out of a

status register, providing detailed information about the status of the transceiver and the received data.

The transmitter block is equipped with two 8 bit wide TX data registers. It is possible to write 8 bits

into the register in burst mode and the internal bit rate generator transmits the bits out with the

predefined rate. For further details, see the TX Register Buffered Data Transmission section.

It is also possible to store the received data bits into a FIFO register and read them out in a

buffered mode.

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RF12B

)

)

)

)

)

)

)

A

r

A

)

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin Name Type Function

1 SDI DI Data input of the serial control interface (SPI compatible
2 SCK DI Clock input of the serial control interface
3 nSEL DI Chip select input of the serial control interface (active low
4 SDO DO Serial data output with bus hold
5 nIRQ DO Interrupt request output (active low

FSK DI Transmit FSK data input (internal pull up resistor 133 k
DATA DO Received data output (FIFO not used

6

nFFS DI

DLCK DO Received data clock output (Digital filter used, FIFO not used
CFIL AIO External data filter capacitor connection (Analog filter used

7

FFIT DO

8 CLK DO Microcontroller clock output

XTL AIO Crystal connection (the other terminal of crystal to VSS) or external reference input

9

REF
10 nRES DIO Open drain reset output with internal pull-up and input buffer (active low)
11 VSS S Ground reference voltage
12 RF2 AIO RF differential signal input/output
13 RF1 AIO RF differential signal input/output
14 VDD S Positive supply voltage
15

16

Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O
settings of the transceiver.

RSSI AO Analog RSSI output
nINT DI Interrupt input (active low
VDI DO Valid data indicator output

FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration

FIFO interrupt (active high) Number of the bits in the RX FIFO has reached the

IO External reference input. Use 33 pF series coupling capacito

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RF12B

PIN6(FSK/DATA/nFFS) internal structure PIN10(nRES) internal structure

T ypical Application

Typical application with FIFO usage

Transmit mode

el=0 in Configuration Setting Command

Transmit mode

el=1 in Configuration Setting Command

Receive mode

ef=0 in Configuration Setting Command

Receive mode

ef=1 in Configuration Setting Command

Pin 6

TX Data input

nFFS input (TX Data register can be accessed)

RX Data output RX Data clock output

nFFS input (RX Data FIFO can be accessed) FFIT output

Pin 7

-

-

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RF12B

V

(

GENERAL DEVICE SPECIFICATION

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units

V

dd

V

V

oc

I

in

ESD Electrostatic discharge with human body model 1000 V

T

st

Recommended Operating Range

Symbol Parameter Min

V

dd

V

ocDC

V

ocAC

T

op

Positive supply voltage -0.5 6 V

Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V

in

Voltage on open collector outputs (RF1, RF2) -0.5

+1.5

dd

Note 1)

Input current into any pin except VDD and VSS -25 25 mA

Storage temperature -55 125

Positive supply voltage 2.2

DC voltage on open collector outputs (RF1, RF2) V

AC peak voltage on open collector outputs (RF1, RF2)

Vdd-1.5

(Note 2)

Ambient operating temperature -40

V

℃

Max Units

3.8 V

+1.5

dd

V

+1 .5

dd

85

V

V

℃

Note 1: Cannot be higher than 7 V.
Note 2: Cannot be lower than 1.2 V.

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range. Typical conditions: Top= 27℃; Vdd=Voc=2.7V)

DC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units

433 MHz band 15 17

868 MHz band 16 18

915 MHz band

17 19

mA

433 MHz band 22 24

868 MHz band 23 25 I

mA

915 MHz band 24 26

433 MHz band 11 13

868 MHz band 12 14 I

915 MHz band

13 15

mA

0.5 µA

Crystal oscillator on

(Note 3)

0.62 1.2 mA

I

dd_TX_0

dd_TX_PMAX

dd_RX

I

pd

I

lb

I

wt

I

x

Supply current

(TX mode, P

= 0 dBm)

out

Supply current

(TX mode, P

out

= P

max

)

Supply current

(RX mode)

Standby current (Sleep mode) All blocks disabled 0.3 µA

Low battery voltage detector current

consumption

Wake-up timer current consumption 1.5 µA

Idle current

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RF12B

A

V

lb

V

lba

V

il

V

ih

I

il

I

ih

V

ol

V

oh

Low battery detect threshold

Low battery detection accuracy 0 5 %

Digital input low level voltage 0.3*V

Digital input high level voltage 0.7*Vdd V

Digital input current Vil = 0 V -1 1 µA

Digital input current Vih = Vdd, Vdd = 3.8 V -1 1 µA

Digital output low level Iol = 2 mA 0.4 V

Digital output high level Ioh = -2 mA Vdd-0.4 V

Programmable in 0.1V

steps

2.2 3.7 V

dd

V

AC Characteristics (PLL parameters)

Symbol Parameter Conditions/Notes Min Typ Max Units

f

PLL reference frequency (Note 1) 9 10 11 MHz

ref

Receiver LO/Transmitter

f

o

carrier frequency

PLL lock time

t

lock

t

PLL startup time With a running crystal oscillator 200 300 us

st, P

433 MHz band, 2.5 kHz resolution 430.24 439.75

868 MHz band, 5.0 kHz resolution 860.48 879.51

915 MHz band, 7.5 kHz resolution 900.72

Frequency error < 1kHz

30 us

929.27

MHz

AC Characteristics (Receiver)

Symbol Parameter Conditions/Notes Min Typ Max Units

mode 0 60 67 75

mode 1 120 134 150

BW Receiver bandwidth

BR

BRA

FC

IIP3

IIP3

IIP3

IIP3

FSK bit rate With internal digital filters 0.6 115.2 kbps

RX

FSK bit rate With analog filter 256 kbps

RX

Receiver Sensitivity BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 2) -109 -103 dBm

P

min

AFC locking range

range

Input IP3 In band interferers in high bands (868, 915 MHz) -21 dBm

inh

Input IP3

outh

IIP3 (LNA –6 dB

inl

gain)

IIP3 (LNA –6 dB

outl

gain)

Maximum input

P

max

power

RF input

C

in

capacitance

RSSI accuracy +/-5 dB

RS

a

RSSI range 46 dB

RS

r

mode 2 180 200 225

mode 3 240 270 300

mode 4 300 340 380

mode 5 360 400 450

df

: FSK deviation in the received signal

FSK

Out of band interferers

l f-fo l > 4 MHz

In band interferers in low band (433 MHz) -15 dBm

Out of band interferers

l f-fo l > 4 MHz

LNA: high gain 0 dBm

1 pF

0.8*df

FSK

-18 dBm

-12 dBm

kHz

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RF12B

C

RS

RS

P

Filter capacitor for

ARSSI

ARSSI

RSSI programmable

step

level steps

DRSSI response

resp

time

Receiver spurious

sp_rx

emission

1 nF

6 dB

Until the RSSI signal goes high after the input signal

exceeds the preprogrammed limit

-60 dBm

AC Characteristics (Transmitter)

Symbol

I

OUT

P

max_50

P

max_ant

P

P

P

C

Q

L

BR

BRA

df

Parameter

Open collector output DC current Programmable

Max. output power delivered to 50

Ohm load over a suitable matching

network (Note 4)

Max. EIRP with suitable selected

PCB antenna. (Note 6, 7)

Typical output power Selectable in 3 dB steps (Note 8)

out

Spurious emission

sp

l f-f

l > 1 MHz

sp

Harmonic suppression

harm

Output capacitance (set by the

o

automatic antenna tuning circuit)

Quality factor of the output

o

capacitance

Output phase noise

out

FSK bit rate Via internal TX data register

TX

FSK bit rate TX data connected to the FSK input

TX

FSK frequency deviation Programmable in 15 kHz steps

fsk

Conditions/Notes Min Typ Max Units

In 433 MHz band

In 868 / 915 MHz bands

In 433 MHz band with monopole

antenna with matching network (Note 4)

In 868 / 915 MHz bands (Note 5)

At max power 50 Ohm load (Note 4)

With PCB antenna (Note 5)

At max power 50 Ohm load (Note 4)

With PCB antenna (Note 5)

In 433 MHz band

In 868 / 915 MHz bands

In 433 MHz band

In 868 / 915 MHz bands

100 kHz from carrier, in 868 MHz band

1 MHz from carrier, in 868 MHz band

C

ARRSI

= 4.7 nF

500 us

0.5 6 mA

7

dBm

5

7

dBm

7

P

-21 P

max

max

dBm

-55 dBc

-60 dBc

-35 dBc

-42 dBc

2 2.6 3.2

pF

2.1 2.7 3.3

13 15 17

8 10 12

-80
dBc/Hz

-103

172 kbps

256 kbps

15 240 kHz

AC Characteristics (Turn-on/Turnaround timings)

Symbol Parameter Conditions/Notes Min Typ MaxUnits

t

sx

Crystal oscillator startup time

Transmitter turn-on time

T

tx_XTAL_ON

Receiver turn-on time

T

rx_XTAL_ON

Transmitter – Receiver turnover time

T

tx_rx_SYNT_ON

Receiver – Transmitter turnover time

T

rx_tx_SYNT_ON

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Crystal ESR < 100 Ohm

Synthesizer off, crystal oscillator on with

10 MHz step

Synthesizer off, crystal oscillator on with

10 MHz step

Synthesizer and crystal oscillator on

during TX/RX change with 10 MHz step

Synthesizer and crystal oscillator on

during RX/TX change with 10 MHz step

1 5 ms

250 us

250 us

150 us

150 us

RF12B

A

AC Characteristics (Others)

Symbol Parameter Conditions/Notes Min Typ Max Units

Programmable in 0.5 pF steps, tolerance

+/- 10%

fter Vdd has reached 90% of final value

(Note 9)

8.5 16 pF

100 ms

C

t

Crystal load capacitance,

xl

see crystal selection guide

Internal POR timeout

POR

t

Wake-up timer clock period

PBt

C

Digital input capacitance

in, D

t

Digital output rise/fall time

r, f

Calibrated every 30 seconds

15 pF pure capacitive load

0.95 1.05 ms

2 pF

10 ns

AC Characteristics (continued)

Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing

and frequency parameters will change accordingly.

Note 2: See the BER diagrams in the measurement results section for detailed information.

Note 3: Measured with disabled clock output buffer. This current can be decreased by enabling the low

power mode of the crystal oscillator. See PLL Setting Command and Power Management Command for

details.

Note 4: See Reference design with 50 Ohm matching network for details.

Note 5: See Reference design with resonant PCB antenna (BIFA) for details.

Note 6: Supposing identical antenna with RF12B in RX mode, the outdoor RF link range will be

approximately 120 meters indoor and 450 meters outdoor.

Note 7: Optimal antenna admittance/impedance:

RF12B Yantenna [S] Zantenna [Ohm] Lantenna [nH]

433 MHz 1.4E-3 - j7.1E-3 27 + j136 52.00

868 MHz 2E-3 - j1.5E-2 8.7 + j66 12.50

915 MHz 2.2E-3 - j1.55E-2 9 + j63 11.20

Note 8: Adjustable in 8 steps.

Note 9: During this period, commands are not accepted by the chip.

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RF12B

CONTROL INTERFACE

Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon

the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal

is high, it initializes the serial interface. All commands consist of a command code, followed by a varying

number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits

having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default

values in all control and command registers.

The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin

low - on the following events:

z The TX register is ready to receive the next byte (RGIT)

z The FIFO has received the preprogrammed amount of bits (FFIT)

z Power-on reset (POR)

z FIFO overflow (FFOV) / TX register underrun (RGUR)

z Wake-up timer timeout (WKUP)

z Negative pulse on the interrupt input pin nINT (EXT)

z Supply voltage below the preprogrammed value is detected (LBD)

FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only

when the TX register is enabled. To identify the source of the IT, the status bits should be read out.

Timing Specification

Symbol Parameter Minimum value [ns]

t

t

t

t

t

t

t

t

Clock high time 25

CH

Clock low time 25

CL

Select setup time (nSEL falling edge to SCK rising edge) 10

SS

Select hold time (SCK falling edge to nSEL rising edge) 10

SH

Select high time 25

SHI

Data setup time (SDI transition to SCK rising edge) 5

DS

Data hold time (SCK rising edge to SDI transition) 5

DH

Data delay time 10

OD

Timing Diagram

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RF12B

Control Commands

Control Command Related Parameters/Functions Related control bits

1 Configuration Setting Command

2 Power Management Command

3 Frequency Setting Command Data frequency of the local oscillator/carrier signal f11 to f0

4 Data Rate Command Bit rate cs, r6 to r0

5 Receiver Control Command

6 Data Filter Command Data filter type, clock recovery parameters al, ml, s1 to s0, f2 to f0

7 FIFO and Reset Mode Command

8 Receiver FIFO Read Command RX FIFO can be read with this command

9 Synchron Pattern Command Synchron pattern b7 to b0

10 AFC Command A F C pa r a m e t e r s

11 TX Configuration Control Command Modulation parameters, output power, ea mp, m3 to m0, p2 to p0

12 PLL Setting Command

Transmitter Register Write

13

Command

14 Wake-Up Timer Command Wake-up time period r4 to r0, m7 to m0

15 Low Duty-Cycle Command Enable low duty-cycle mode. Set duty-cycle. d6 to d0, en

Low Battery Detector and

16

Microcontroller Clock Divider

Command

17 Status Read Command Status bits can be read out

In general, setting the given bit to one will activate the related function. In the following tables, the

POR column shows the default values of the command registers after power-on.

Frequency band, crystal oscillator load capacitance,

baseband filter bandwidth, etc.

Receiver/Transmitter mode change, synthesizer, xtal osc,

PA, wake-up timer, clock output can be enabled here

Function of pin 16, Valid Data Indicator, baseband bw, LNA

gain, digital RSSI threshold

Data FIFO IT level, FIFO start control, FIFO enable and

FIFO fill enable

CLK out buffer speed, low power mode of the crystal

oscillator, dithering, PLL loop delay, bandwidth

TX data register can be written with this command t7 to t0

LBD voltage and microcontroller clock division ratio d2 to d0, v4 to v0

el, ef, b1 to b0, x3 to x0

er, ebb, et, es, ex, eb,

ew, dc

p16, d1 to d0, i2 to i0,

g1 to g0, r2 to r0

f3 to f0, s1 to s0, ff, fe

a1 to a0, rl1 to rl0, st, fi,

oe, en

ob1 to ob0, lpx, ddit,

ddy, bw1 to bw0

Description of the Control Commands

1. Configuration Setting Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h

Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.

Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.

b1 b0 Frequency Band [MHz]

0 0 Reserved

0 1 433

1 0 868

1 1 915

x3 x2 x1 x0 Crystal Load Capacitance [pF]

0 0 0 0 8.5

0 0 0 1 9.0

0 0 1 0 9.5

0 0 1 1 10.0

…

1 1 1 0 15.5

1 1 1 1 16.0

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RF12B

2. Power Management Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 0 0 0 0 0 1 0 er ebb et es ex eb ew dc 8208h

Bit Function of the control bit Related blocks

er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator

ebb The receiver baseband circuit can be separately switched on Baseband

Switches on the PLL, the power amplifier, and starts the

et

transmission (If TX register is enabled)

es Turns on the synthesizer Synthesizer

ex Turns on the crystal oscillator Crystal oscillator

eb Enables the low battery detector Low battery detector

ew Enables the wake-up timer Wake-up timer

dc Disables the clock output (pin 8) Clock output buffer

Power amplifier, synthesizer, oscillator

The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.

Logic connections between power control bits:

Note:

• If both et and er bits are set the chip goes to receive mode.

• FSK / nFFSEL input are equipped with internal pull-up resistor. To achieve minimum current

consumption do not pull this input to logic low in sleep mode.

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RF12B

3. Frequency Setting Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 0 f11 f10f9f8f7f6f5f4f3f2f1 f0 A680h

The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of

range, the previous value is kept. The synthesizer band center frequency f

f

= 10 * C1 * (C2 + F/4000) [MHz]

0

can be calculated as:

0

The constants C1 and C2 are determined by the selected band as:

Band [MHz] C1 C2

433 1 43

868 2 43

915 3 30

4. Data Rate Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h

The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive

mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs.

BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]

In the receiver set R according to the next function:

R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.

Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated

with small error.

Data rate accuracy requirements:

z Clock recovery in slow mode: ΔBR/BR < 1/(29*N

z Clock recovery in fast mode: ΔBR/BR < 3/(29*N

)

bit

)

bit

BR is the bit rate set in the receiver and ΔBR is the bit rate difference between the transmitter and the

receiver. N

is the maximum number of consecutive ones or zeros in the data stream. It is recommended

bit

for long data packets to include enough 1/0 and 0/1 transitions, and to be careful to use the same division

ratio in the receiver and in the transmitter.

5. Receiver Control Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h

Bit 10 (p16): pin16 function select

P16 Function of pin 16

0 Interrupt input

1 VDI output

Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:

d1 d0 Response

0 0 Fast

0 1 Medium

1 0 Slow

1 1 Always on

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RF12B

Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:

i2 i1 i0 BW [kHz]

0 0 0 reserved

0 0 1 400

0 1 0 340

0 1 1 270

1 0 0 200

1 0 1 134

1 1 0 67

1 1 1 reserved

Bits 4-3 (g1 to g0): LNA gain select:

g1 g0

relative to maximum [dB]

0 0 0

0 1 -6

1 0 -14

1 1 -20

Bits 2-0 (r2 to r0): RSSI detector threshold:

r2 r1 r0 RSSI

setth

[dBm]

0 0 0 -103

0 0 1 -97

0 1 0 -91

0 1 1 -85

1 0 0 -79

1 0 1 -73

1 1 0

1 0 1

Reserved

Reserved

The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:

RSSI

= RSSI

th

setth

+ G

LNA

7.Data Filter Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 0 0 1 0 al ml 1 s 1 f2 f1 f0 C22Ch

Bit 7 (al): Clock recovery (CR) auto lock control, if set.

CR will start in fast mode, then after locking it will automatically switch to slow mode.

Bit 6 (ml): Clock recovery lock control

1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended)

0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)

Using the slow mode requires more accurate bit timing (see Data Rate Command).

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RF12B

Bits 4 (s): Select the type of the data filter:

s Filter Type

0 Digital filter

1 Analog RC filter

Digital: This is a digital realization of an analog RC filter followed by a comparator with

hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate
Command.
Note: Bit rate can not exceed 115 kbps in this mode.

Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter

cut-off frequency is set by the external capacitor connected to this pin and VSS.

Bits 2-0 (f2 to f0): DQD threshold parameter.

Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where

the bit-rate is close to the deviation. At higher deviation/bit-rate settings, a higher threshold parameter

can report "good signal quality" as well.

The table shows the optimal filter capacitor values for different data rates

1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps 256 kbps

12 nF 8.2 nF 6.8 nF 3.3 nF 1.5 nF 680 pF 270 pF 150 pF 100 pF

Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used.

7. FIFO and Reset Mode Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 1 0 1 0 f3 f2 f1 f0 sp al ff dr CA80h

Bits 7-4 (f4 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches

this level.

Bit 3 (sp): Select the length of the synchron pattern:

sp Byte1 Byte0 (POR) Synchron Pattern (Byte1+Byte0)

0 2Dh D4h 2DD4h
1 Not used D4h D4h

Note: Byte0 can be programmed by the Synchron Pattern Command.

Bit 2 (al): Set the input of the FIFO fill start condition:

al

0 Synchron pattern

1 Always fill

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RF12B

Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is

cleared.

Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 500 mV glitch in the power

supply may cause a system reset.

Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.

8. Synchron pattern Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 1 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 CED4h

The Byte0 used for synchron pattern detection can be reprogrammed by B <b7:b0>.

9.Receiver FIFO Read Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h

With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in

Configuration Setting Command.

Note: During FIFO access f

cannot be higher than f /4, where f

SCK ref ref

is the crystal oscillator frequency.

When the duty-cycle of the clock signal is not 50 % the shorter period of the clk pulse should be at least

2/f

second.

ref

10.AFC Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 0 1 0 0 a1 a0 rl1 rl0 st fi oe en C4F7h

Bit 7-6 (a1 to a0): Automatic operation mode selector:

a1 a0

0 0 Auto mode off (Strobe is controlled by microcontroller)

0 1 Runs only once after each power-up

1 0 Keep the foffset only during receiving (VDI=high)

1 1 Keep the foffset value independently from the state of the VDI signal

Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:

rl1 rl0 Max deviation

0 0 No restriction

0 1 +15 f

1 0 +7 f

1 1 +3 f

res

to -8 f

res

to -4 f

res

to -16 f

res

res

res

f :

res

315, 433 MHz bands: 2.5 kHz

868 MHz band: 5 kHz

915 MHz band: 7.5 kHz

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RF12B

Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the

offset register of the AFC block.

Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice

longer, but the measurement uncertainty is about the half.

Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the

frequency control word of the PLL.

Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.

Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring

results are the same, toggle bit changes state in every measurement cycle.

In automatic operation mode (no strobe signal is needed from the microcontroller to update the

output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming

signal during the whole measurement cycle and the circuit measures the same result in two subsequent

cycles.

There are three operation modes, examples from the possible application:

1, (a1=0, a0=1) the circuit measures the frequency offset only once after power up. This way, extended

TX-RX maximum distance can be achieved.

Possible application:

In the final application, when the user inserts the battery, the circuit measures and compensates for

the frequency offset caused by the crystal tolerances. This method allows for the use of a cheaper quartz

in the application and provides protection against tracking an interferer.

2a, (a1=1, a0=0) the circuit automatically measures the frequency offset during an initial effective low

data rate pattern –easier to receive- (i.e.: 00110011) of the package and changes the receiving frequency

accordingly. The further part of the package can be received by the corrected frequency settings.

2b, (a1=1, a0=0) the transmitter must transmit the first part of the packet with a step higher deviation and

later there is a possibility of reducing it.

In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the

output register is automatically cleared. Use these settings when receiving signals from different

transmitters transmitting in the same nominal frequencies.

3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with

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RF12B

only one transmitter. After a complete measuring cycle, the measured value is kept independently of the

state of the VDI signal.

11. TX Configuration Control Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 0 0 1 1 0 0 mp m3 m2 m1 m0 0 p2 p1 p0 9800h

Bits 8-4 (mp, m3 to m0):FSK modulation

parameters:

The resulting output frequency can be

calculated as:

f

= f + (-1)

out

SIGN

0

* (M + 1) * (15 kHz)

Where:

f0 is the channel center frequency (see the
Frequency Setting Command)
M is the four bit binary number <m3: m0>

SIGN = (mp) XOR (Data bit)

Bits 2-0 (p2 to p0): Output power:

p2 p1 p0 Relative Output Power [dB]

0 0 0 0

0 0 1 -3

0 1 0 -6

0 1 1 -9

1 0 0 -12

1 0 1 -15

1 1 0 -18

1 1 1 -21

The output power given in the table is relative to the maximum available power, which depends on the

actual antenna impedance.

12. PLL Setting Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 1 1 0 0 0 ob1 ob0 lpx ddy ddit 1 bw0 CC67h

Note: POR default setting of the register carefully selected to cover almost all typical applications.

Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control.

ob1 ob0 Selected uC CLK frequency

0 0 5 or 10 MHz (recommended)

0 1 3.3 MHz

1 X 2.5 MHz or less

Note: Needed for optimization of the RF performace. Optimal settings can vary by the actual external

parasitic capacitances.

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RF12B

Bit 4 (lpx): When this bit is set, low power mode of the crystal oscillator is selected.

lpx Crystal start-up time (typ) Power consumption (typ)

0 1 ms 620 uA

1 2 ms 460 uA

(Typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V, Crystal ESR = 30 Ohm)

We have test that the default value(0) of bit lpx in PLL setting command will lead to
part of RF12B/RFM12B's oscillator fail. it should be set 1 in software manually. for
example, use 0xCC77 instead of 0xCC67 as PLL setting command.

Bit 3 (ddy): Switches on the delay in the phase detector when this bit is set.

Bit 2 (ddit): When set, disables the dithering in the PLL loop.
Bit 1-0 (bw1-bw0): PLL bandwidth can be set for optimal TX RF performance.

bw0 Max bit rate [kbps] Phase noise at 1MHz offset [dBc/Hz]

0 86.2 -107

1 256 -102

13. Transmitter Register Write Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 0 1 1 1 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 B8AAh

With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must

be set in Configuration Setting Command.

Multiple byte write with Transmit Register Write Command:

Note: Alternately the transmit register can be directly accessed by nFFSEL (pin6).

14. Wake-Up Timer Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h

The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):

T

= M * 2R [ms]

wake-up

Note:

• For continual operation the et bit should be cleared and set at the end of every cycle.

• For future compatibility, use R in a range of 0 and 29.

15. Low Duty-Cycle Command

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RF12B

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 1 0 0 r0 d6 d5 d4 d3 d2 d1 d0 en C80Eh

With this command, Low Duty-Cycle operation can be set in order to decrease the average power

consumption in receiver mode. The time cycle is determined by the Wake-Up Timer Command. The

Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer

Command.)

Duty-Cycle= (D * 2 +1) / M *100%

Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.

Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management
Command.

Application proposal for LPDM(Low Power Duty-cycle Mode) Receivers:

Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.

Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management
Command.

16. Lo w Battery Detector and Microcontroller Clock Divider Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR

1 1 0 0 0 0 0 0 d2 d1 d0 0 v3 v2 v1 v0 C000h

The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage Vlb of the

detector:

V

= 2.2 + V * 0.1 [V]

lb

Clock divider configuration:

d2 d1 d0 Clock Output Frequency [ MHz]

0 0 0 1

0 0 1 1.25

0 1 0 1.66

0 1 1 2

1 0 0 2.5

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RF12B

r

d

1 0 1 3.33

1 1 0 5

1 1 1 10

The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively,

using the Power Management Command.

17. Status Read Command

The read command starts with a zero, whereas all other control commands start with a one. If a read

command is identified, the status bits will be clocked out on the SDO pin as follows:

Status Register Read Sequence with FIFO Read Example:

RGIT

FFIT

POR Power-on reset (Cleared after Status Read Command)

RGUR TX register under run, register over write (Cleared after Status Read Command)

FFOV RX FIFO overflow (Cleared after Status Read Command)

WKUP Wake-up timer overflow (Cleared after Status Read Command)

EXT

LBD Low battery detect, the power supply voltage is below the pre-programmed limit

FFEM FIFO is empty

ATS Antenna tuning circuit detected strong enough RF signal

RSSI The strength of the incoming signal is above the pre-programmed limit

DQD Data quality detector output

CRL Clock recovery locked

ATGL Toggling in each AFC cycle

OFFS(6) MSB of the measured frequency offset (sign of the offset value)

OFFS(3)

-OFFS(0)

Note: In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit

TX register is ready to receive the next byte (Can be cleared by Transmitter Registe

Write Command)

The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be

cleared by any of the FIFO read methods)

Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Rea

Command)

Offset value to be added to the value of the frequency control parameter (Four LSB bits)

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RF12B

in the AFC Control Command (bit 0).

TX REGISTER BUFFERED DATA TRANSMISSION

In this operating mode (enabled by bit el, in the Configuration Control Command) the TX data is clocked

into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register

(with the given bit rate) when bit et is set with the Power Management Command. The initial value of the

data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored

to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.

TX register simplified block diagram (before transmit)

TX register simplified block diagram (during transmit)

Typical TX register usage

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RF12B

Note: The content of the data registers are initialized by clearing bit et.

RX FIFO BUFFERED DATA READ

In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill

up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates

potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the

external microcontroller.

Interrupt Controlled Mode:

The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT

when exceeded. The status bits report the changed FIFO status in this case.

FIFO Read Example with FFIT Polling

Note: During FIFO access f

When the duty-cycle of the clock signal is not 50% the shorter period of the clk pulse should be at least

2/f

second.

ref

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cannot be higher than f /4, where f

SCK ref ref

is the crystal oscillator frequency.

RF12B

Polling Mode:

When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be

clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in

the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be

taken. An SPI read command is also available to read out the content of the FIFO.

RECOMMENDED PACKET STRUCTURES

Minimum length

Recommended

length

Preamble

4 - 8 bit (1010b or 0101b) D4h (programmable) ? 4 bit - 1 byte

8 -12 bit (e.g. AAh or 55h) 2DD4h (D4 is

Synchron word
(Can be network ID)

programmable)

Payload CRC

? 2 byte

CRYSTAL SELECTION GUIDELINES

The crystal oscillator of the RF12B requires a 10 MHz parallel mode crystal. The circuit contains an

integrated load capacitor in order to minimize the external component count. The internal load

capacitance value is programmable from 8.5 pF to 16 pF in 0.5pF steps. With appropriate PCB layout,

the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.

When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C

value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300

ohms ESR (equivalent series loss resistance). However, lower C

and ESR values guarantee faster

0

oscillator startup.

The crystal frequency is used as the reference of the PLL, which generates the local oscillator

frequency (f

). Therefore fLO is directly proportional to the crystal frequency. The accuracy requirements

LO

for production tolerance, temperature drift and aging can thus be determined from the maximum

allowable local oscillator frequency error.

Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to

the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if

the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The

“pull-ability” of the crystal is defined by its motional capacitance and C

.

0

Maximum XTAL Tolerances Including Temperature and Aging [ppm]

Bit Rate:

2.4 kbps

315 MHz
433 MHz

868 MHz
915 MHz

30 45 60 75 90 105 120

25 50 75 100 100 100 100

20 30 50 70 90 100 100

10 20 25 30 40 50 60

10 15 25 30 40 50 50

Deviation [+/- kHz]

Bit Rate:

9.6 kbps

315 MHz

30 45 60 75 90 105 120

20 50 70 75 100 100 100

Deviation [+/- kHz]

)

0

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RF12B

433 MHz
868 MHz
915 MHz

Bit Rate:

Bit Rate:

315 MHz
433 MHz
868 MHz
915 MHz

38.4 kbps

315 MHz
433 MHz

868 MHz
915 MHz

115.2 kbps

15 30 50 70 80 100 100

8 15 25 30 40 50 60

8 15 25 30 40 50 50

30 45 60 75 90 105 120

don't use 7 30 50 75 100 100

don't use 5 20 30 50 75 75

don't use 3 10 20 25 30 40

don't use 3 10 15 25 30 40

105 120 135 150 165 180 195

don't use 4 30 50 70 100 100

don't use 3 20 30 50 70 80

don't use don't use 10 20 25 35 45

don't use don't use 10 15 25 30 40

RX-TX ALIGNMENT PROCEDURES

Deviation [+/- kHz]

Deviation [+/- kHz]

RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To
minimize these errors it is suggested to use the same crystal type and the same PCB layout for the
crystal placement on the RX and TX PCBs.

To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a
high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself
will change the reference frequency. Since the carrier frequencies are derived from the reference
frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side
there should be no offset if the CLK signals have identical frequencies.

It is possible to monitor the actual RX-TX offset using the AFC status report included in the status
byte of the receiver. By reading out the status byte from the receiver the actual measured offset
frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by
clearing the "en" bit in the AFC Control Command (bit 0).

TYPICAL PERFORMANCE CHARACTERISTICS

Channel Selectivity and Blocking:

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RF12B

Note:

• LNA gain maximum, filter bandwidth 67 kHz, data rate to 9.6 kbps, AFC switched off, FSK

deviation +/- 45 kHz, V

• Measured according to the descriptions in the ETSI Standard EN 300 220-1 v2.1.1 (2006-01 Final

Draft), section 9

• The ETSI limit in the figure is drawn by taking 109dBm typical sensitivity into account

= 2.7 V

dd

Phase Noise Performance in the 915 MHz (Green) 868 MHz (Red) and 433
MHz (Blue) Bands:

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RF12B

(Measured under typical conditions: Top = 27 oC; Vdd = V

BER Curves in 433 MHz Band:

= 2.7 V)

oc

BER Curves in 868 MHz Band:

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RF12B

The table shows the optimal receiver baseband bandwidth (BW) and transmitter deviation frequency (
f

) selection for different data rates.

FSK

1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 57.6 kbps 19.2 kbps 38.4 kbps 115.2 kbps

BW=67 kHz

=45 kHz δf

δf

FSK

BW=67 kHz BW=67 kHz BW=67 kHz BW=67 kHz BW=134 kHz BW=134 kHz BW=200 kHz

=45 kHz δf

FSK

=45kHz δf

FSK

=45 kHz δf

FSK

=45 kHz δf =90 kHz δf

FSK

FSK FSK

=90 kHz δf

=120 kHz

FSK

Receiver Sensitivity over Ambient Temperature

(433 MHz, 9.6 kbps,

δ

f

: 45 kHz, BW: 67 kHz):

FSK

δ

Receiver Sensitivity over Ambient Temperature

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RF12B

(868 MHz, 9.6 kbps, δ fFSK: 45 kHz, BW: 67 kHz):

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RF12B

REFERENCE DESIGNS

Schematic

PCB layout

Top view

Bottom view

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SGS Reports

RF12B

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RF12B

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RF12B

RF12B BONDING DIAGRAM

Pad Opening: 85um square, except 76um octagon pads (AN1, AN2)
Die Size: 2750 X 3315 um

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RF12B

HOPE MICROELECTRONICS CO.,LTD

4/F, Block B3, East Industrial Area,

Huaqiaocheng, Shenzhen, Guangdong,

China

Tel: [phone]

Fax: [phone]

Email:

Website:

http://www.hoperf.cn

http://hoperf.en.alibaba.com

[e-mail]

http://www.hoperf.com

This document may contain preliminary information and is subject to

change by Hope Microelectronics without notice. Hope Microelectronics

assumes no responsibility or liability for any use of the information

contained herein. Nothing in this document shall operate as an express

or implied license or indemnity under the intellectual property rights of

Hope Microelectronics or third parties. The products described in this

document are not intended for use in implantation or other direct life

support applications where malfunction may result in the direct physical

harm or injury to persons. NO WARRANTIES OF ANY KIND,

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