Rainbow Electronics RF12 User Manual

RF12

RF12 Universal ISM Band
FSK Transceiver

DESCRIPTION

Hope’s RF12 is a single chip, low power, multi-channel

FSK transceiver designed for use in applications requiring

FCC or ETSI conformance for unlicensed use in the 315, 433,

868 and 915 MHz bands. The RF12 transceiver produces a

flexible, low cost, and highly integrated solution that does not

require production alignments. The chip is a complete analog

RF and baseband transceiver including a multi-band PLL

synthesizer with PA, LNA, I/Q down converter mixers,

baseband filters and amplifiers, and an I/Q demodulator. All

required RF functions are integrated. Only an external crystal and bypass filtering are needed for

operation.

The RF12 features a completely integrated PLL for easy RF design, and its rapid settling time allows

for fast frequency-hopping, bypassing multi-path fading and interference to achieve robust wireless links.

The PLL’s high resolution allows the usage of multiple channels in any of the bands. The receiver

baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal

tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation.

Consequently, no external components (except crystal and decoupling) are needed in most applications.

The RF12 dramatically reduces the load on the microcontroller with the integrated digital data

processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data

register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost)

crystal. To minimize the system cost, the RF12 can provide a clock signal for the microcontroller, avoiding

the need for two crystals.

For low power applications, the RF12 supports low duty cycle operation based on the internal

wake-up timer.

RF12

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RF12

FEATURES

 Fully integrated (low BOM, easy design-in)

 No alignment required in production

 Fast-settling, programmable, high-resolution PLL synthesizer

 Fast frequency-hopping capability

 High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode)

 Direct differential antenna input/output

 Integrated power amplifier

 Programmable TX frequency deviation (15 to 240 KHz)

 Programmable RX baseband bandwidth (67 to 400 kHz)

 Analog and digital RSSI outputs

 Automatic frequency control (AFC)

 Data quality detection (DQD)

 Internal data filtering and clock recovery

 RX synchron pattern recognition

 SPI compatible serial control interface

 Clock and reset signals for microcontroller

 16 bit RX Data FIFO

 Two 8 bit TX data registers

 Low power duty cycle mode

 Standard 10 MHz crystal reference

 Wake-up timer

 Low power consumption

 Low standby current (0.3 µA)

TYPICAL APPLICATIONS

 Remote control

 Home security and alarm

 Wireless keyboard/mouse and other PC peripherals

 Toy controls

 Remote keyless entry

 Tire pressure monitoring

 Tel e m etr y

 Personal/patient data logging

 Remote automatic meter reading

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RF12

DETAILED FEATURE-LEVEL DESCRIPTION

The RF12 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868

and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements.

The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a

minimal number of external components in a typical application. The RF12 incorporates a fully integrated

multi-band PLL synthesizer, PA with antenna tuning, an LNA with switch-able gain, I/Q down converter

mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter.

PLL

The programmable PLL synthesizer determines the operating frequency, while preserving accuracy

based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of

multiple channels in any of the bands.

The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds.

Calibration always occurs when the synthesizer starts. If temperature or supply voltage changes

significantly, VCO recalibration can be invoked easily. Recalibration can be initiated at any time by

switching the synthesizer off and back on again.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and can directly drive a loop antenna

with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly

trimming procedures and the so-called “hand effect.”

LNA

The LNA has 250 Ohm input impedance, which functions well with the proposed antennas. If the

RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide

the correct matching and to minimize the noise figure of the receiver.

The LNA gain can be selected (0, –6, –14, –20 dB relative to the highest gain) according to RF signal

strength. It can be useful in an environment with strong interferers.

Baseband Filters

The receiver bandwidth is s

by programming the bandwidth (

the baseband filters. This allows setting

up the receiver according to the

characteristics of the signal to be

received.

An appropriate bandwidth can be

chosen to accommodate various FSK

deviation, data rate and crystal tolerance

requirements. The filter structure is 7th

order Butterworth low-pass with 40 dB

suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off

frequency below 7 kHz.

electable

BW) of

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RF12

Data Filtering and Clock Recovery

Output data filtering can be completed by an external capacitor or by using digital filtering according

to the final application.

Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The

resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen

according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO

can not be used in this mode and clock is not provided for the demodulated data.

Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode

there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock

the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow

mode, its noise immunity is very high, but it has slower settling time and requires more accurate data

timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode.

The CR starts in fast mode, then after locking it automatically switches to slow mode (Only the digital data

filter and the clock recovery use the bit rate clock. For analog operation, there is no need for setting the

correct bit rate.)

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal

strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI

settling time depends on the external filter capacitor. Pin 19 is used as analog RSSI output. The digital

RSSI can be monitored by reading the status register.

P1 -65 dBm 1300 mV

P2 -65 dBm 1000 mV

P3 -100 dBm 600 mV

P4 -100 dBm 300 mV

DQD

The Data Quality Detector is based on counting the spikes on the unfiltered received data. For

correct operation, the “DQD threshold” parameter must be filled in by using the Data Filter Command.

AFC

By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the

TX/RX offset in discrete steps, allowing the use of:

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RF12

1, Inexpensive, low accuracy crystals

2, Narrower receiver bandwidth (i.e. increased sensitivity)

3, Higher data rate

Crystal Oscillator

The RF12 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the

PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and

programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.

The transceiver can supply the clock signal for the microcontroller; so accurate timing is possible

without the need for a second crystal.

When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the

Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses (“clock

tail”) for the microcontroller to let it go to idle or sleep mode.

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below

a programmable threshold level. The detector circuit has 50mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5μA typical) and can be programmed from

1 ms to several days with an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When the

crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick

calibration (a few milliseconds) to facilitate accurate wake-up timing.

Event Handling

In order to minimize current consumption, the transceiver supports different power saving modes.

Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up

timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the

serial interface).

If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to

wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The

source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin.

Interface and Controller

An SPI compatible serial interface lets the user select the frequency band, center frequency of the

synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock,

wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these

auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the

programmed values are retained during sleep mode. The interface supports the read-out of a status

register, providing detailed information about the status of the transceiver and the received data.

The transmitter block is equipped with an 8 bit wide TX data register. It is possible to write 8 bits into

the register in burst mode and the internal bit rate generator transmits the bits out with the predefined

rate.

It is also possible to store the received data bits into a FIFO register and read them out in a buffered

mode.

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RF12

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin Name Type Function

1 SDI DI Data input of the serial control interface (SPI compatible)

2 SCK DI Clock input of the serial control interface

3 nSEL DI Chip select input of the serial control interface (active low)

4 SDO DO Serial data output with bus hold

5 nIRQ DO Interrupt request output (active low)

FSK DI Transmit FSK data input

6 DATA DO Received data output (FIFO not used)

nFFS DI FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration

Setting Command

DLCK DO Received data clock output (Digital filter used, FIFO not used)

CFIL AIO External data filter capacitor connection (Analog filter used) 7

FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the

FFIT DO

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preprogrammed limit In FIFO mode, when bit ef is set in Configuration Setting

Command

RF12

8 CLK DO Microcontroller clock output

XTL AIO

9

REF AIO External reference input. Use 33 pF series coupling capacitor

10 nRES DIO Open drain reset output with internal pull-up and input buffer (active low)

11 VSS_D S Digital VSS(Connect to VSS)

12 VSS_A S Analog VSS(Connect to VSS)

13 VSS_RF S RF VSS(Connect to VSS)

14 RF2 AIO RF differential signal input/output

15 RF1 AIO RF differential signal input/output

16 VDD_RF S RF VDD(Connect to VDD)

17 VDD_A S Analog VDD(Connect to VDD)

18 VDD_D S Digital VDD(Connect to VDD)

19 ARSSI AO Analog RSSI output

nINT DI Interrupt input (active low)

20

VDI DO Valid data indicator output

Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O

settings of the transceiver.

Crystal connection (the other terminal of crystal to VSS) or external reference

input

T ypical Application

Typical application with FIFO usage

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RF12

Pin 6 Pin 7

Transmit mode el=0 in Configuration Setting Command TX Data input -

Transmit mode el=1 in Configuration Setting Command Connect to logic high -

Receive mode ef=0 in Configuration Setting Command RX Data output RX Data clock output

Receive mode ef=1 in Configuration Setting Command nFFS input FFIT output

GENERAL DEVICE SPECIFICATION

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units

Vdd Positive supply voltage -0.5 6 V

Vin Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V

Voc Voltage on open collector outputs (RF1, RF2) -0.5 Vdd+1.5 (Note 1) V

Iin Input current into any pin except VDD and VSS -25 25 mA

ESD Electrostatic discharge with human body model 1000 V

Tst Storage temperature -55 125 oC

Recommended Operating Range

Symbol Parameter Min Max Units

Vdd Positive supply voltage 2.2 5.4 V

V

ocDC

V

ocAC

Top Ambient operating temperature -40 85

Note 1: At maximum, V
Note 2: At maximum, V

DC voltage on open collector outputs (RF1,RF2) Vdd+1.5(Note2) V

AC peak voltage on open collector outputs (RF1,RF2) Vdd-1.5(Note1) Vdd+1.5 V

℃

+1.5V cannot be higher than 7V. At minimum, Vdd-1.5V cannot be lower than 1.2V.

dd

+1.5V cannot be higher than 5.5V.

dd

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range. Typical conditions: Top= 27℃; Vdd=Voc=2.7V)

DC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units

I

dd_TX_0

I

dd_TX_PMAX

Supply current (TX mode,

Pout = 0 dBm)

Supply current (TX mode,

Pout = Pmax)

315/433 MHz bands

868 MHz band

915 MHz band

315/433 MHz bands

868 MHz band

915 MHz band

13

21

16

17

23

24

14

18

19

22

25

26

mA

mA

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RF12

I

dd_RX

I

pd

I

lb

I

wt

I

x

V

lb

V

lba

V

il

V

ih

I

il

I

ih

V

ol

V

oh

Supply current (RX mode)

Standby current (Sleep

mode)

Low battery voltage

detector current

315/433 MHz bands

11

868 MHz band

915 MHz band

All blocks disabled

12

13

0.3

0.5

13

14

15

mA

µA

µA

consumption

Wake-up timer current

consumption

Idle current

Low battery detect

threshold

Low battery detection

accuracy

Digital input low level

voltage

Digital input high level

voltage

Crystal oscillator and

baseband parts are on

Programmable in 0.1 V

steps

2.2

0.7*V

dd

1.5

µA

3 3.5 mA

5.3 V

±75

0.3*V

V

dd

mV

V

Digital input current Vil = 0 V -1 1 µA

Digital input current Vih = Vdd, Vdd = 5.4 V -1 1 µA

Digital output low level Iol = 2 mA 0.4 V

Digital output high level Ioh = -2 mA Vdd-0.4 V

AC Characteristics (PLL parameters)

Symbol Parameter Conditions/Notes Min Typ Max Units

ref

PLL reference

frequency

f

Receiver LO /

Transmitter carrier

f

o

frequency

t

t

st, P

PLL lock time

lock

PLL startup time With a running crystal oscillator 250 us

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(Note 1) 8 10 12 MHz

315MHz band,2.5kHz resolution

433MHz band,2.5kHz resolution

868MHz band,5.0kHz resolution

915MHz band,7.5kHz resolution

Frequency error < 1kHz after

10MHz step

310.24

430.24

860.48

900.72

20 us

319.75

439.75

879.51

MHz

929.27

RF12

AC Characteristics (Receiver)

Symbol Parameter Conditions/Notes Min Typ Max Units

FSK

75

150

225

300

375

450

kHz

dBm

dBm

dBm

dBm

dBm

dBm

pF

nF

dB

us

67

60

120

180

240

300

360

134

200

270

350

400

BW

Receiver

bandwidth

mode 0

mode 1

mode 2

mode 3

mode 4

mode 5

BR FSK bit rate With internal digital filters 0.6 115.2 kbps

BRA FSK bit rate With analog filter 256 kbps

P

AFC

IIP3

IIP3

IIP3

IIP3

P

RS

RS

C

RS

min

range

inh

outh

outl

max

C

in

a

ARSSI

step

Receiver

Sensitivity

AFC locking range df

Input IP3 In band interferers in high bands(868,

Input IP3 Out of band interferers l f-fo l > 4 MHz -18

IIP3 (LNA –6 dB

inl

gain)

IIP3 (LNA –6 dB

gain)

Maximum input

power

RF input

capacitance

RSSI accuracy +/-5 dB

RSSI range 46 dB

r

Filter capacitor for

ARSSI

RSSI

programmable

BER 10-3, BW=67kHz, BR=1.2kbps

-109 -100

(Note 2)

: FSK deviation in the received

FSK

0.8*df

signal

-21

915 MHz)

In band interferers in low bands (315,

-15

433 MHz)

Out of band interferers l f-fo l > 4 MHz -12

LNA: high gain 0

1

1

6

level steps

500

RS

DRSSI response

time

resp

Until the RSSI signal goes high after

the input signal exceeds the

preprogrammed limit C

ARRSI

= 5 nF

AC Characteristics (Transmitter)

Symbol Parameter Conditions/Notes Min Typ Max Units

I

OUT

Open collector output DC

current

Available output power with

P

max

optimal antenna impedance

(Note 3, 4)

P

Typical output power

out

Psp Spurious emission

Programmable 0.5

In low bands

In high bands

Selectable in 3 dB steps

(Note 5)

At max power with loop

P

max

antenna (Note 6)

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8

4

-21

6 mA

dBm

P

dBm

max

-50 dBc