Rainbow Electronics RF01 User Manual

RF01

Universal ISM Band FSK Receiver RF01

DESCRIPTION:

RF01

Hope’s RF01 is a single chip, low power, multi-channel

FSK receiver designed for use in applications requiring

FCC or ETSI conformance for unlicensed use in the 315,

433, 868, and 915 MHz bands. Used in conjunction with

Hope's FSK transmitters, the RF01 is a flexible, low cost,

and highly integrated solution that does not require

production alignments. All required RF functions are

integrated. Only an external crystal and bypass filtering are

needed for operation.

The RF01 has a completely integrated PLL for easy RF design, and its rapid settling time allows for

fast frequency hopping, bypassing multi-path fading, and interference to achieve robust wireless links.

The PLL’s high resolution allows the usage of multiple channels in any of the bands. The baseband

bandwidth (BW) is programmable to accommodate various deviation, data rate, and crystal tolerance

requirements. The receiver employs the Zero-IF approach with I/Q demodulation, therefore no external

components (except crystal and decoupling) are needed in a typical application. The RF01 is a complete

analog RF and baseband receiver including a multi-band PLL synthesizer with an LNA, I/Q down

converter mixers, baseband filters and amplifiers, and I/Q demodulator.

The chip dramatically reduces the load on the microcontroller with integrated digital data processing:

data filtering, clock recovery, data pattern recognition and integrated FIFO. The automatic frequency

control (AFC) feature allows using a low accuracy (low cost) crystal. To minimize the system cost, the

chip can provide a clock signal for the microcontroller, avoiding the need for two crystals.

For low power applications, the device supports low duty-cycle operation based on the internal

wake-up timer.

BLOCK DIAGRAM

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RF01

FEATURES:

z Fully integrated (low BOM, easy design-in)

z No alignment required in production

z Fast settling, programmable, high-resolution PLL

z Fast frequency hopping capability

z High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode)

z Direct differential antenna input

z Programmable baseband bandwidth (67 to 400 kHz)

z Analog and digital RSSI outputs

z Automatic frequency control (AFC)

z Data quality detection (DQD)

z Internal data filtering and clock recovery

z RX pattern recognition

z SPI compatible serial control interface

z Clock and reset signals for microcontroller

z 16 bit RX data FIFO

z Low power duty-cycle mode (less than 0.5 mA average supply current)

z Standard 10 MHz crystal reference

z Wake-up timer

z Low battery detector

z 2.2 to 5.4 V supply voltage

z Low power consumption (~9 mA in low bands)

z Low standby current (0.3 µA)

TYPICAL APPLICATIONS

z Remote control

z Home security and alarm

z Wireless keyboard/mouse and other PC peripherals

z Toy control

z Remote keyless entry

z Tire pressure monitoring

z Tel e m etr y

z Personal/patient data logging

z Remote automatic meter reading

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RF01

DETAILED DESCRIPTION

General

The RF01 FSK receiver is the counterpart of the Hope’s FSK transmitter. It covers the unlicensed

frequency bands at 315, 433, 868, and 915 MHz. The device facilitates compliance with FCC and ETSI

requirements.

The programmable PLL synthesizer determines the operating frequency, while preserving accuracy

based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows for the use

of multiple channels in any of the bands.

The receiver employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal

number of external components in a typical application. The RF01 consists of a fully integrated

multi-band PLL synthesizer, an LNA with switchable gain, I/Q down converter mixers, baseband filters

and amplifiers, and an I/Q demodulator followed by a data filter.

The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds.

Calibration always occurs when the synthesizer begins. If temperature or supply voltage changes

significantly, VCO recalibration can be invoked easily. Recalibration can be initiated at any time by

switching the synthesizer off and back on again.

LNA

The LNA has 250 Ohm input impedance, which works well with the recommended antennas.

If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to

provide the correct matching and to minimize the noise figure of the receiver.

The LNA gain (and linearity) can be selected (0, –6, –14, –20 dB relative to the highest gain)

according to RF signal strength. This is useful in an environment with strong interferers.

Baseband Filters

The receiver bandwidth is selectable

by programming the bandwidth (BW) of the

baseband filters. This allows setting up the

receiver according to the characteristics of

the signal to be received. An appropriate

bandwidth can be selected to

accommodate various FSK deviation, data

rate, and crystal tolerance requirements.

The filter structure is a 7-th order

Butterworth low-pass with 40 dB

suppression at 2*BW frequency. Offset

cancellation is accomplished by using a

high-pass filter with a cut-off frequency

below 7 kHz.

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RF01

Data Filtering and Clock Recovery

The output data filtering can be completed by an external capacitor or by using digital filtering

according to the final application.

Analog operation:

The filter is an RC type low-pass filter and a Schmitt-trigger (St). The resistor (10k) and the St is

integrated on the chip. An (external) capacitor can be chosen according to the actual bit-rate. In this

mode the receiver can handle up to 256 kbps data rate.

Digital operation:

The data filter is a digital realization of an analog RC filter followed by a comparator with hysteresis.

In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. With

this clock the received data can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and

automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more

accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast

and slow modes. The CR starts in fast mode, then automatically switches to slow mode after locking.

(Only the data filter and the clock recovery use the bit-rate clock. Therefore, in analog mode, there is

no need for setting the correct bit-rate.)

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal

strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI

settling time depends on the filter capacitor used.

P1 -65 dBm 1300 mV

P2 -65 dBm 1000 mV

P3 -100 dBm 600 mV

P4 -100 dBm 300 mV

DQD

The Data Quality Detector monitors the I/Q output of the baseband amplifier chain by counting the

consecutive correct 0->1, 1->0 transitions. The DQD output indicates the quality of the signal to be

demodulated. Using this method it is possible to "forecast" the probability of BER degradation. The

programmable DQD parameter defines the threshold for signaling the good/bad data quality by the digital

one-bit DQD output. In cases when the deviation is close to the bit rate, there should be four transitions

during a single one bit period in the I/Q signals. As the bit rate decreases in comparison to the deviation,

more and more transitions will happen during a bit period.

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RF01

AFC

By using an integrated Automatic Frequency Control (AFC) feature, the receiver can synchronize its

local oscillator to the received signal, allowing the use of:

z inexpensive, low accuracy crystals

z narrower receiver bandwidth (i.e. increased sensitivity)

z higher data rate

Crystal Oscillator

The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the

PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and

programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The

receiver can supply the clock signal for the microcontroller, so accurate timing is possible without the

need for a second crystal.

When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the

Configuration Setting Command, the chip provides a fixed number (128) of further clock pulses (“clock

tail”) for the microcontroller to let it go to idle or sleep mode.

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below

a programmable threshold level.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA typical) and can be programmed from

1 ms to several days with an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When the

crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick

calibration (a few milliseconds) to facilitate accurate wake-up timing.

Event Handling

In order to minimize current consumption, the receiver supports the sleep mode. Active mode can be

initiated by several wake-up events (wake-up timer timeout, low supply voltage detection, on-chip FIFO

filled up or receiving a request through the serial interface).

If any wake-up event occurs, the wake-up logic generates an interrupt signal which can be used to

wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The

cause of the interrupt can be read out from the receiver by the microcontroller through the SDO pin.

Interface and Controller

An SPI compatible serial interface lets the user select the frequency band, center frequency of the

synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock,

wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these

auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the

programmed values are retained during sleep mode. The interface supports the read-out of a status

register, providing detailed information about the status of the receiver and the received data. It is also

possible to store the received data bits into the 16bit RX FIFO register and read them out in a buffered

mode. FIFO mode can be enabled through the SPI compatible interface by setting the fe bit to 1 in the

Output and FIFO Mode Command.

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RF01

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin Name Type Function

1 SDI DI Data input of serial control interface

2 SCK DI Clock input of serial control interface

3 nSEL DI Chip select input of three-wire control interface (active low)

4 FFIT/SDODO

5 nIRQ DO Interrupt request output, (active low)

DATA DO Received data output (FIFO not used)

6

nFFS DI FIFO select input

DCLK DO Received data clock output (Digital filter used, FIFO not used)

CFIL AIO External data filter capacitor connection (Analog filter used)

7

FFIT DO

8 CLK DO Clock output for the microcontroller

9 XTL/REFAIO Crystal connection (other terminal of crystal to VSS) / External reference input

10 nRES DO Reset output (active low)

11 VSS_D S Digital VSS(connect to VSS)

12 VSS_A S Analog VSS(connect to VSS)

13 VSS_LNAS LNA VSS(connect to VSS)

14 IN2 AI RF differential signal input

15 IN1 AI RF differential signal input

FIFO IT (active low) or serial data out for Status Read Command.

Tristate with bushold cell if nSEL=H

FIFO IT (active high) FIFO empty function can be achieved when FIFO IT level is

set to one

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RF01

16 VDD_LN S Positive supply voltage

17 VDD _A S Analog VDD(connect to VDD)

18 VDD_D S Digital VDD(connect to VDD)

19 ARSSI AO Analog RSSI output

20 VDI DO Valid Data Indicator output

T ypical Application

GENERAL DEVICE SPECIFICATION

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units

Vdd Positive supply voltage -0.5 6.0 V

Vin Voltage on any pin -0.5 Vdd+0.5 V

I

in

ESD Electrostatic discharge with human body model 1000 V

Tst Storage temperature -55 125

Recommended Operating Range

Symbol Parameter Min Max Units

Vdd Positive supply voltage 2.2 5.4 V

Top Ambient operating temperature -40 85

Input current into any pin except VDD and VSS -25 25 mA

℃

℃

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RF01

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range, typ conditions: Top = 27 ℃;

= 2.7 V)

V

dd

DC Characteristics

Symbol

I

dd

I

pd

I

lb

I

wt

I

x

V

lb

V

lba

V

il

V

ih

I

il

I

ih

V

ol

V

oh

Note: Using the internal wake-up timer and counter reduces the overall current consumption, which

should permit approximately 6 months operation from a 1500mAh battery.

AC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units

f

LO

BW

BR FSK bit rate With internal digital filters 115.2 kbps
BRA FSK bit rate With analog filter 256 kbps
P

Receiver Sensitivity BER 10-3, BW=67 kHz,

min

AFC

IIP3

inh

IIP3

outh

IIP3

inl

Parameter Conditions/Notes

Supply current

315 and 433 MHz bands
868 MHz band 915 MHz
band

Min Typ Max Units

9

10.5
12

11

12.5
14

mA

Standby current All blocks disabled 0.3 µA
Low battery voltage

detector current

0.5 µA

consumption

Wake-up timer current
consumption (Note 1)

Idle current Crystal oscillator and

Low battery detect
threshold

Low battery detection
accuracy

Digital input low level 0.3*V
Digital input high level 0.7*V

base-band parts are ON
Programmable in 0.1 V

steps

1.5 µA

3.0 3.5 mA

2.2 5.3 V

75 mV

V

dd

V

dd

Digital input current Vil = 0 V -1 1 µA
Digital input current Vih = Vdd, Vdd = 5.4 V -1 1 µA
Digital output low level Iol = 2 mA 0.4 V

Digital output high level Ioh = -2 mA Vdd-0.4 V

Receiver frequency

Receiver bandwidth

315 MHz band, 2.5 kHz resolution

433 MHz band, 2.5 kHz resolution

868 MHz band, 5.0 kHz resolution
915 MHz band, 7.5 kHz resolution

mode 0
mode 1
mode 2
mode 3
mode 4
mode 5

310.24

430.24

860.48

900.72
60
120
180
240
300
360

319.75

439.75

879.51

929.27
67
134
200
270
350
400

75
150
225
300
375
450

MHz

kHz

-109 -100 dBm

BR=1.2 kbps (Note 1)

AFC locking range δf

range

: FSK deviation in the

FSK

0.8*δf

FSK

received signal

Input IP3 In band interferers in high

-21 dBm

bands

Input IP3 Out of band interferers

f-f

> 4MHz

LO

-18 dBm

IIP3 (LNA –6 dB gain) In band interferers in low -15 dBm

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