QUICK LOGIC QL5732-33BPS484C, QL5732-33BPS484I, QL5732-33BPS484M Datasheet

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Device Highlights

High Performance PCI Controller

• 32-bit / 33 MHz PCI Master/Target

• Zero-wait state PCI Master provides

132 MBps transfer rates

• Zero-wait-state PCI Target Write/One-wait-state

PCI Target Read interface

• Supports all PCI commands, including

configuration and MWI

• Supports fully-customizable byte enable for

master channels

• Target interface supports retry, disconn ect

with/without data transfer, and target abort

• Fully programmable back-end interface

• Independent PCI bus (33 MHz) and local bus (up

to 160 MHz) clocks

• Fully customizable PCI Configuration Space

• Configurable FIFOs with depths up to 256 words

• Reference design with driver code (Win

95/98/Win 2000/NT4.0) available

• PCI v2.3 compliant

• Supports Type 0 Configuration Cycles in Target

mode

• 3.3 V PCI signaling

• 2.5 V Supply Voltage

• 484 and 516-pin PBGA

• Supports Extendable PCI functionality

• Unlimited/Continuous Burst Transfers supported

Extendable PCI Functionality

• Support for PCI host-bridge function

• Support for Configuration Space from

0 × 40 to 0 × 3FF

• Multi-Function, Expanded Capabilities, and

Expansion ROM capable

• PCI v2.3 Power Management Spec compatible

• PCI v2.3 Vital Product Data (VPD) configuration

support

• Programmable Interrupt Generator

• I

O support with local processor

• Mailbox register support

Flexible Programmable Logic

• 1,348 Logic Cells

• 50,688 RAM bits

• Up to 268 I/O pins

• All back-end interface and glue-logic can be

implemented on chip

• Six 32-bit busses interface between the PCI

Controller and the Programmable Logic

• Twenty-two 2,304 bit Dual Port High

Performance SRAM Blocks

• 3,500 flip-flops available

Figure 1: 5732 Block Diagram

PCI Bus

PCI Bus 33 MHz/32 bits (data and

address)

Tar ge t Controller

160 MHz FIFOs

Config space

DMA Controller

Master Controller

High Speed Logic Cells

High Speed Data Path

Programmable Logic

32 bit Interface

268 User I/O

QL5732 Enhanced QuickPCI Device Data Sheet

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Architecture Overview

The QL5732 device in the QuickLogic QuickPCI Embedded Standard Product (ESP) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps).

The programmable logic portion of the device contains 1,348 QuickLogic Logic Cells and 22 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs.

The QL5732 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. This device also supports the Win'98 and PC'98 standards. The QL5732 device features 2.5 V operation with multi-volt compatible I/Os. The device can easily operate in 3 V embedded systems and is fully compatible with 3.3 V applications.

PCI Controller

The PCI Controller is a 32-bit/33 MHz PCI 2.3 Compliant Master/T arget Controller capable of infinite length Master Write and Read transactions at zero wait states (132 MBps).

The Master will never insert wait states during transfers, so data is supplied or received by FIFOs that can be configured in the programmable region of the device. The Master is capable of initiating any type of PCI commands, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL5732 device to act as a PCI host. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. DMA Controller reference design is available and will be included in the QuickWorks



design software.

The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-state target Write and one-wait-state target Read operations. It also supports retry, disconnect with/without data transfer, and target abort requested by the back end. Any number of 32-bit BARs may be configured as either memory or I/O space. All required and optional PCI 2.3 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is available and will be included in the QuickWorks design software.

The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. These functions are not timing critical, so leaving these elements in the programmable region allows the greatest degree of flexibility to the designer . Reference DMA controller, Configuration Space, and Address Decoding blocks are readily available so that the design cycle can be minimized.

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Configuration Space and Address Decode

The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the

device. This allows support for any size of memory or I/O space for back end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5732. QuickLogic provides a reference Address Register/Counter and Command Decode block.

DMA Master Target Controller

The customizable DMA controller included with the QuickWorks design software contains the following features:

• Configurable DMA count size for Reads and Writes (up to 30-bits)

• Configurable DMA burst size for PCI (including unlimited/continuous burst)

• Customizable PCI command to use by core

• Customizable Byte Enable signal

• Programmable Arbitration between DMA Read & Write transactions

• DMA Registers may be mapped to any area of Target Memory Space, including:

• Read Address (32-bit register)

• Write Address (32-bit register)

• Read Length (16-bit register) / Write Length

(16-bit register)

• Control and Status (32-bit register, includes 8 bit

Burst Length)

• DMA Registers are available to the local design or the PCI bus

• Programmable Interrupt Control to signal end of transfer or other event

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Configurable FIFOs

FIFOs may be created with the RAM/FIFO wizard in the QuickWorks tools. Figure 2 shows the graphical interface used to create these FIFOs. FIFOs may be designed up to 1,024 words deep. The 22 RAM cells available in the QL5732 allow for up to:

• 11 FIFOs at 128 words deep (36 wide)

• 5 FIFOs at 256 words deep (36 wide)

• 2 FIFOs at 512 words deep (44 wide)

• 1 FIFO at 1,024 words deep (44 wide)

Figure 2: Graphical Interface to create FIFO

PCI Interface Symbol

Figure 2 shows the graphical interface symbol numbers you have to use in your schematic design

in order to attach the local interface programmable logic design to the PCI core. If you are designing with a top-level Verilog or VHDL file you must use a structural instantiation of this PCI32_25µm block (Figure 3) instead of a graphical symbol.

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Figure 3: PCI Interface Symbol

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

PCI Master Interface

The internal signals used to interface with the PCI controller in the QL5732 are listed in Table 1 along with a description of each signal. The direction of the signal indicates if the signal is an input provided by the local interface (I) or an output provided by the PCI controller (O).

NOTE: Signals that end with the character ‘N’ should be considered active-low (for example,

Mst_IRDYN).

Table 1: PCI Master Interface

Signal I/O Description

PCI_cmd[3:0] I PCI command to be used for the master transaction This signal must remain unchanged

throughout the period when Mst_Burst_Req is active. PCI commands considered as Reads include Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple, and Memory Read Line. PCI commands considered as Writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write, and Invalidate.Users should make sure that only valid PCI commands are supplied.

mst_burst_req I Request use of the PCI bus When it is active, the core requests the PCI bus and then generates

a Master transaction. This signal should be held active until all requested data is transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new transaction).

mst_wrAd[31:0] I Address for master DMA writes This address must be treated as valid from the beginning of a

DMA Write until the DMA Write operation is complete. It should be incremented by four bytes each time data is transferred on the PCI bus.

mst_rdAd[31:0] I Address for master DMA reads This address must be treated as valid from the beginning of a

DMA read until the DMA Read operation is complete. It should be incremented by four bytes each

time data is transferred on the PCI bus. Mst_WrData[31:0] I Data for master DMA Writes (to PCI bus) Mst_BE[3:0] I Byte enables for master DMA Reads and writes Active-low. Mst_WrData_Valid I Data and byte enable valid on Mst_W rData[31:0] (for master Write only) and Mst_BE[3:0] (for both

master Read and Write) Mst_WrData_Rdy O Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and

Mst_BE[3:0] (for both) This serves as the PUSH control for the internal FIFO and the POP

control for the external FIFO (in FPGA region) which provides data and byte enables to the PCI32

core. Mst_BE_Sel I Byte enable select for master transactions When low, Mst_BE[3:0] should remain constant

throughout the entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of

the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case

of master Write) is used. Should be held constant throughout the transaction. Mst_WrBurst_Done O Master Write transaction is completed Active for only one clock cycle. Mst_Rd_Term_Sel I Master Read termination mode select when Mst_BE_Sel is high When both Mst_BE_Sel

and Mst_Rd_Term_Sel are high, Master Read termination happens when the internal FIFO is

empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low,

Mst_Two_Reads and Mst_One_Read are used to signal the end of Master Read. Should be held

constant throughout the transaction. Mst_One_Read I Signals to the PCI32 core that only one data transfer remains to be read in the burst Read.

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Mst_Two_Reads I Two data transfers remain to be read in the burst Read It is not used for single-data-phase

Master Read transactions. Mst_RdData_Valid O Master Read data valid on Usr_Addr_WrData[31:0 ] This serves as the PUSH control for the

external FIFO (in FPGA region) that receives data from the PCI32 core. Mst_RdBurst_Done O Master Read transaction is completed Active for only one clock cycle. Flush_FIFO I Internal FIFO flush FIFO flushed immediately after it is active (synchronized with PCI clock). Mst_LatCntEn I Enable Latency Counter Set to 0 to ignore the Latency Timer in the PCI configuration space

(offset 0Ch).

For full PCI compliance, this port should be always set to 1. Mst_Xfer_D1 O Data was transferred on the previous PCI clock Useful for updating DMA transfer counts on

DMA Read operations Mst_Last_Cycle O Active during the last data transfer of a master transaction Mst_REQN O Copy of the PCI REQN signal generated by QL5732 as PCI master Not usually used in

the back-end design. Mst_IRDYN O Copy of the PCI IRDYN signal generated by QL5732 as PCI master

Valid only when

QL5

732 is the PCI master. Kept low otherwise. Not usually used in the back-end design.

Mst_Tabort_Det O Target abort detected during master transaction This is normally an error condition handled

in the DMA controller. Mst_TTO_Det O Target timeout detected (no response from target) This is normally an error condition

handled in the DMA controller.

Table 1: PCI Master Interface

Signal I/O Description

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

PCI Target Interface

Table 2: PCI Target Interface

Signal I/O Description

Usr_Addr_WrData[31:0] O Target address, and target Write data

During all target accesses, the address is presented

on Usr_Addr_WrData[31:0]; at the same time, Usr_Adr_Valid is active. During target Write transactions, this port also presents valid Write data to the PCI configuration space or user logic when Usr_Adr_Inc is active.

Usr_CBE[3:0] O PCI command and byte enables During target accesses, the PCI command is presented on

Usr_CBE[3:0]; at the same time, Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI configuration space or user logic.

Usr_Adr_Valid O Indicates the beginning of a PCI transaction, and that a target address is valid on

Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory or I/O space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal is low, indicating that address is NOT present on Usr_Addr_WrData[31:0].

Usr_Adr_Inc O Indicates that the target address should be incremented, because the pr evious data transfer has

completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_V alid is active), and must therefore be latched and incremented by four for subsequent data transfers. Note that during target Write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the state of Usr_Rdy). During Read transactions, Usr_Adr_Inc signals to the backend that the PCI core has presented the read data on the PCI bus (TRDYN asserted).

Usr_RdDecode I This signal should be the combinatorial decode of the "user read" command from

Usr_CBE[3:0]. This command may be mapped from any of the PCI Read commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It is internally gated with Usr_Adr_Valid.

Usr_WrDecode I This signal should be the combinatorial decode of the "user write" command from

Usr_CBE[3:0]. This command may be mapped from any of the PCI Write comma nds, such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid.

Usr_Select I This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been

decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid.

Usr_Write O This signal is active throughout a "user write" transaction, which has been decoded by

Usr_WrDecode at the beginning of the transaction. The Write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a user Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.

Cfg_Write O This signal is active throughout a "configuration write" transaction. The Write strobe for

individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.

Usr_Read O This signal is active throughout a "user read" transaction, which has been decoded by

Usr_RdDecode at the beginning of the transaction.

Cfg_Read O This signal is active throughout a "configuration read" transaction.

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

Cfg_RdData[31:0] I Data from the PCI configuration registers, required to be presented during PCI configuration

reads. Usr_RdData[31:0] I Data from the back-end user logic required to be presented during PCI user reads. Cfg_CmdReg3 I Bit 3 from the Command Register in the PCI configuration space (offset 04h). Enable Special

Cycle monitoring. If high, the core reports data parity error in Special Cycles through SERRN

if Cfg_CmdReg8 is active. Cfg_CmdReg4 I Bit 4 from the Command Register in the PCI configuration space (offset 04h). Memory Write

and Invalidate (MWI) Enable. If high, the core generates MWI transactions as requested by the

backend. Otherwise it uses Memory Write instead even if MWI is requested. Cfg_CmdReg6 I Bit 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error

Response. If high, the core uses PERRN to report data parity errors. Otherwise it never drives

it. Cfg_CmdReg8 I Bit 8 from the Command Register in the PCI configuration space (offset 04h). SERRN En able.

If high, the cores uses SERRN to report address parity errors if Cfg_CmdReg6 is high. Cfg_LatCnt[7:0] I 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Usr_MstRdAd_Sel I Used when a target Read operation should return the value set on the Mst_RdAd[31:0] pins.

This select pin saves on logic which would otherwise need to be used to multiplex

Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored. Usr_MstWrAd_Sel I Used when a target read operation should return the value set on the Mst_WrAd[31:0] pins.

This select pin saves on logic which would otherwise need to be used to multiplex

Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored. Cfg_PERR_Det O Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register

must be set in the PCI configuration space (offset 04h). Cfg_SERR_Sig O System error asserted on the PCI bus. When this signal is active, the Signalled System Error

bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Cfg_MstPERR_Det O Data parity error detected on the PCI bus by the master . When this signal is active, bit 8 of the

Status Register must be set in the PCI configuration space (offset 04h). Usr_TRDY O Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within a

target access. Usr_STOPO O Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only within a

target access. Usr_DEVSEL O Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within a

target access. Usr_Last_Cycle_D1 O Active one clock cycle after the last data phase (may not with data transfer) occurs on PCI a nd

inactive one clock cycle afterwards. Usr_Rdy I Used to delay (add wait states to) a target PCI transaction when the backend needs additional

time to provide data (read) or accept data (write). Subject to PCI latency restrictions. Usr_Stop I Used to prematurely stop a PCI target access on the next PCI clock. Usr_Abort I Used to signal Target Abort on PCI when the backend has fatal errors and is unable to

complete a transaction. Rarely used.

Table 2: PCI Target Interface

Signal I/O Description

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

PCI Internal Signals

RAM Module Features

The QL5732 device has twenty-two 2,304-bit RAM modules, for a total of 50,668 RAM bits. Using two “mode” pins, designers can configure each module into 128 × 18, 256 × 9, 512 × 4, or 1024 × 2 blocks (see Figure 1). The blocks are also easily cascadable to increase their effective width or depth.

The RAM modules are “dual-ported” with completely independent Read and Write ports and separate Read and Write clocks. The Read ports support asynchronous and synchronous operation, while the Write ports support synchronous operation. Each port has 18 data lines and ten address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous Write operation. The Read Enable (RE) acts as a clock enable for synchronous Read operation (ASYNCRD input low), or as a flow-through enable for asynchronous Read operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 1,024-deep configurations as large as 44 bits wide in the QL5732 device.

A similar technique can be used to create depths greater than 1,024 words. In this case, address signals higher than the eighth bit are encoded onto the write enable (WE) input for Write operations. The Read data outputs are multiplexed together using encoded higher Read address bits for the multiplexer SELECT signals.

Table 3: PCI Internal Signals

Signal Description

PCI_clock O PCI clock. PCI_reset O PCI reset signal. PCI_IRDYN_D1 O Copy of the IRDYN signal from the PCI bus, delayed by one clock. PCI_FRAMEN_D1 O Copy of the FRAMEN signal from the PCI bus, delayed by one clock. PCI_DEVSELN_D1 O Copy of the DEVSELN signal from the PCI bus, delayed by one

clock. PCI_TRDYN_D1 O Copy of the TRDYN signal from the PCI bus, delayed by one clock. PCI_STOPN_D1 O Copy of the STOPN signal from the PCI bus, delayed by one clock. PCI_IDSEL_D1 O Copy of the IDSEL signal from the PCI bus, delayed by one clock.

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QL5732 Enhanced QuickPCI Device Data Sheet Rev C

QL5732 Embedded Computational Unit (ECU)

T raditional Programmable Logic architectures do not implement arithmetic functions efficiently— these functions require high logic cell usage while achieving only moderate performance results.

The QL5732 architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL5732 device can address various arithmetic functions efficiently—this approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 5.

Figure 5: ECU Block Diagram

The 12 QL5632 ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.

WCLK

RCLK

RAM

Module

[9:0]

[17:0]

[9:0]

[17:0]

MODE ASYNCRD

[1:0]

Figure 4: RAM Module

[0:15]

SIGN2

SIGN1

CIN

S1 S2

3-4

decoder

8-bit

Multiplier

17 inc. COUT

16-bit Adder

17-bit

2-1

mux

2-1

mux

3-1

mux

Q[0:1

CLK

RESET

00 01

10A[0:7]

A[8:15]

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