QUICK LOGIC QL5130-33APB256C, QL5130-33APB256I, QL5130-33APF144C, QL5130-33APF144I, QL5130-33APQ208C Datasheet

Rev B

33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM

QL5130 - QuickPCI

TM

last updated 12/1099

Device Highlights

High Performance PCI Controller

■ 32-bit / 33 MHz PCI Target

■ Zero-wait state PCI Target provides 132 MB/s transfer rates

■ Programmable back-end interface to optional local processor

■ Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

■ Fully customizable PCI Configuration Space

■ Configurable FIFOs with depths up to 128

■ Reference design with driver code (Win 95/98/Win 2000/

NT4.0)
available

■ PCI v2.2 compliant

■ Supports Type 0 Configuration Cycles

■ 3.3V, 5V Tolerant PCI signaling supports Universal PCI

Adapter designs

■ 3.3V CMOS in 144-pin TQFP, 208-pin PQFP and 256-PBGA

■ Supports endian conversions

■ Unlimited/Continuous Burst Transfers Supported

Extendable PCI Functionality

■ Support for Configuration Space from 0x40 to 0x3FF

■ Multi-Function, Expanded Capabilities, & Expansion ROM

capable

■ Power management, Compact PCI, hot-swap/hot-plug

compatible

■ PCI v2.2 Power Management Spec compatible

■ PCI v2.2 Vital Product Data (VPD) configuration support

■ Programmable Interrupt Generator

■ I

2

O support with local processor

■ Mailbox register support

Programmable Logic

■ 57K System gates / 619 Logic Cells

■ 13,824 RAM bits, up to 157 I/O pins

■ 250 MHz 16-bit counters, 275 MHz Datapaths,

160 MHz FIFOs

■ All back-end interface and glue-logic can be implemented

on chip

■ 6 64-deep FIFOs (2 RAMs each) or 3 128-deep FIFOs

(4 RAMs each) or a combination that requires 12 or less
QuickLogic RAM Modules

■ (2) 32-bit busses interface between the PCI Controller and the

Programmable Logic

FIGURE 1. QL5130 Diagram

Architecture Overview

The QL5130 device in the QuickLogic QuickPCI ESP
(Embedded Standard Product) family provides a com­plete and customizable PCI interface solution com­bined with 57,000 System gates of programmable
logic. This device eliminates any need for the designer
to worry about PCI bus compliance, yet allows for the
maximum 32-bit PCI bus bandwidth (132 MB/s).

The programmable logic portion of the device con­tains 619 QuickLogic Logic Cells, and 12 QuickLogic
Dual-Port RAM Blocks. These configurable RAM
blocks can be configured in many width/depth combi­nations. They can also be combined with logic cells to
form FIFOs, or be initialized via Serial EEPROM on
power-up and used as ROMs. See the RAM section of
this data sheet for more information.

The QL5130 device meets PCI 2.2 electrical and tim­ing specifications and has been fully hardware-tested.
This device also supports the Win’98 and PC’98 stan­dards. The QL5130 device features 3.3-volt opera­tion with multi-volt compatible I/Os. Thus it can
easily operate in 3.3-volt systems and is fully compati­ble with 3.3V, 5V and Universal PCI card develop­ment.

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EVICE HIGHLIGHTS

A

RCHITECTURE OVERVIEW

2 Rev B

QL5130 - QuickPCI

TM

PCI Interface

The PCI target is PCI 2.2 compliant and supports
32-bit/33 MHz operation. It is capable of zero wait­state infinite-length read and write transactions (132
MBytes/second). Transaction control is available via
the user interface as retries, wait-states, or premature
transaction termination may be induced if necessary.
The PCI configuration registers are implemented in
the programmable region of the device, leaving the
designer with ample flexibility to support optional
features.

The QL5130 device supports maximum 32-bit PCI
transfer rates, so many applications exist which are
ideally suited to the device’s high performance.
High-speed data communications, telecommunica­tions, and computing systems are just a few of the
broad range of applications areas that can benefit
from the high speed PCI interface and programmable
logic.

PCI Configuration Space

The QL5130 supports customization of required
Configuration Registers such as Vendor ID, Device
ID, Subsystem Vendor ID, etc.. QuickLogic provides
a reference Configuration Space design block.

Since the PCI Configuration Registers are imple­mented in the programmable region of the QL5130,
the designer can implement optional features such as
multiple 32-bit Base Address Registers (BARs) and
multiple functions, as well as support the following
PCI commands: I/O Read, I/O Write, Memory Read,
Memory Write, Config Read (required), Configuration
Write (required), Memory Read Multiple, Memory
Read Line, and Memory Write and Invalidate. Addi­tionally, the device supports Extended Capabilities
Registers, Expansion ROMs, power management,
CompactPCI hot-plug/hot-swap, Vital Product Data,
I

2

0, and mailbox registers.

PCI address and command decoding is performed by
logic in the programmable section of the device. This
allows support for any size of memory or I/O space
for back-end logic. It also allows the user to imple­ment any subset of the PCI commands supported by
the QL5130. QuickLogic provides a reference
Address Register/Counter and Command Decode
block.

Architecture Overview

The RAM modules in the programmable region can
be used to create configurable 32-bit FIFOs. Each
32-bit FIFO can be independently assigned to Target
address space for read pre-fetch or write posting.
Using the 12 QuickLogic RAM modules, the combi­nations include:

• 6 independent 64-deep FIFO (2 RAMs each),
or

• 3 independent 128-deep FIFOs (4 RAMs each),
or

• a combination of the above that requires 12 or less
QuickLogic RAM Modules

Asynchronous FIFOs (with independent read and
write clocks) are also supported.

FIGURE 2. Graphical Interface to create FIFO

PCI I

NTERFACE

A

DDRESS AND

C

OMMAND

D

ECODE

PCI C

ONFIGURATION SPACE

A

RCHITECTURE OVERVIEW

Rev B 3

QL5130 - QuickPCI

TM

Internal PCI Interface

FIGURE 3. PCI Interface Symbol

The symbol used to connect to the PCI interface of the QL5130 is shown below. This symbol is

used in schematic or mixed schematic/HDL design flows in the Quick

Works

software.

Internal PCI Interface

4 Rev B

QL5130 - QuickPCI

TM

Internal Interface Signal Descriptions

Signals used to connect to the PCI interface in the QL5130 are described below. The direction of the signal indi­cates if it is an input provided by the local interface (I) or an output provided by the PCI interface (O).

Usr_Addr_WrData[31:0] O Target address, and data from target writes. During all target

accesses, the address will be presented on
Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will
be active. During target write transactions, this por t will also
present write data to the PCI configuration space or user logic.

Usr_CBE[3:0] O PCI command and byte enables. During target accesses, the PCI

command will be presented on Usr_CBE[3:0] and simultaneously,
Usr_Adr_Valid will be active. During target read or write
transactions, this port will present acti ve-low byte-enables to the
PCI configuration space or user logic.

Usr_Adr_Valid O Indicates the beginning of a PCI transaction, and that a target

address is valid on Usr_Addr_WrData[31:0] and the PCI
command is valid on Usr_CBE[3:0]. When this signal is active,
the target address must be latched and decoded to determine if this

address belongs to the device’s memory space. Also, the PCI
command must be decoded to determine the type of PCI
transaction. On subsequent clocks of a target access, this signal
will be low, indicating that an address is NOT present on
Usr_Addr_WrData[31:0].

Usr_Adr_Inc O Indicates that the target address should be incremented, because

the previous data transfer has completed. During burst target
accesses, the target address is only presented to the back-end logic
at the beginning of the transaction (when Usr_Adr_Valid is
active), and must therefore be latched and incremented (by 4) for
subsequent data transfers. Note that during write transactions,
Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that
must be accepted by the back-end logic (regardless of the state of
Usr_Rdy). During read transactions, Usr_Adr_Inc will signal to
the back-end that the PCI core is ready to accept data.
Usr_Adr_Inc and Usr_Rdy both active during a read transaction
signals a data transfer between the FPGA and the PCI core (and
that the address counter must be incremented).

Usr_RdDecode I This signal should be driven active when a “user read” command

has been decoded from the Usr_CBE[3:0] bus (while
Usr_Adr_Valid is active). This command may be mapped from
any of the PCI “read” commands, such as Memory Read, Memory
Read Line, Memory Read Multiple, I/O Read, etc.

Usr_WrDecode I This signal should be driven active when a “user write” command

has been decoded from the Usr_CBE[3:0] bus (while
Usr_Adr_Valid is active). This command may be mapped from
any of the PCI “write” commands, such as Memory Write or I/O
Write.

Internal Interface
Signal Descriptions

Rev B 5

QL5130 - QuickPCI

TM

Internal Interface Signal Descriptions (Continued)

Usr_Select I This signal should be driven active when the address on

Usr_Addr_WrData[31:0] has been decoded and determined to be
within the address space of the device. Usr_Addr_WrData[31:0]
must be compared to each of the valid Base Address Registers in
the PCI configuration space. Also, this signal must be gated by the
Memory Access Enable or I/O Access Enable registers in the PCI
configuration space (Command Register bits 1 or 0 at offset 04h).

Usr_Write O This signal will be active throughout a “user write” transaction,

which has been decoded by Usr_WrDecode at the beginning of the
transaction. The write-enable for individual double-words of data
(on Usr_Addr_WrData[31:0]) during a user write transaction
should be generated by logically ANDing this signal with
Usr_Adr_Inc.

Cfg_Write O This signal will be active throughout a configuration write

transaction. The write-enable for individual double-words of data
(on Usr_Add r_WrData[ 31:0]) during a configuration write
transaction should be generated by logically ANDing this signal
with Usr_Adr_Inc.

Cfg_RdData[31:0] I Data from the PCI configuration registers, required to be presented

to the PCI core during PCI configuration reads.

Usr_RdData[31:0] I Data from the back-end user logic, required to be presented during

PCI reads.
Cfg_CmdReg8
Cfg_CmdReg6

I Bits 6 and 8 from the Command Register in the PCI configuration

space (offset 04h).
Cfg_PERR_Det O Parity error detected on the PCI bus. When this signal is active, bit

15 of the Status Register must be set in the PCI configuration

space (offset 04h).
Cfg_SERR_Sig O System error asserted on the PCI bus. When this signal is active,

the Signaled System Error bit, bit 14 of the Status Register, must

be set in the PCI configuration space (offset 04h).
Usr_TRDYN O Copy of the TRDYN signal as driven by the PCI target interface.
Usr_STOPN O Copy of the STOPN signal as driven by the PCI target interface.
Usr_Devsel O Inverted copy of the DEVSELN signal as driven by the PCI target

interface.
Usr_Last_Cycle_D1 O Indicates that the last transfer in a PCI transaction is occurring.
RdPipe_Stat[1:0] O Indicates the number of dwords currently in the read pipeline

(“00” = 0 elements, “01” = 1 element, “11” = 2 elements). This

value is important at the end of a transaction (i.e. when

Usr_Last_Cycle_D1 is active) if non-prefetchable memory is

being read. Non-prefetchable memory is defined as registers or

memory elements whose value changes when they are read.

Examples are status registers which are cleared when they are

read, or FIFO memories, since consecutive reads from the same

address in these elements may not produce the same data values.
Usr_Rdy I Used to delay (add wait states to) a PCI transaction when the back

end needs additional time. Subject to PCI latenc y restrictions.
Usr_Stop I Used to prematurely stop a PCI target access on the next PCI

clock.

6 Rev B

QL5130 - QuickPCI

TM

Array of Logic Cells

A wide range of additional features complements the
QL5130 device. The FPGA portion of the device is
5 volt and 3.3-volt PCI-compliant and can perform
high-speed logic functions such as 160 MHz FIFOs.
I/O pins provide individually controlled output
enables, dedicated input/feedback registers, and full
JTAG capability for boundary scan and test. In addi­tion, the QL5130 device provides the benefits of
non-volatility, high design security, immediate func­tionality on power-up, and a single chip solution.

The QL5130 programmable logic architecture con­sists of an array of user-configurable logic building
blocks, called logic cells, set beneath a grid of metal
wiring channels similar to those of a gate array.

Through ViaLink

®

elements located at the wire inter­sections, the output(s) of any cell may be pro­grammed to connect to the input(s) of any other cell.
Using the programmable logic in the QL5130,
designers can quickly and easily customize their

“back-end” design for any number of applications.

FIGURE 4. Logic Cell

RAM Module Features

The QL5130 device has twelve 1,152-bit RAM mod­ules, for a total of 13,824 RAM bits. Using two
“mode” pins, designers can configure each module
into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2
blocks. See the figure below. The blocks are also
easily cascadable to increase their effective width or
depth.

FIGURE 5. RAM Module

A

RRAY OF LOGIC CELLS

QS
A1

A2
A3
A4
A5
A6

OS
OP
B1
B2
C1
C2

MS

D1
E1
NP

E2

D2

NS
F1
F3
F5

F6

F2
F4

QC
QR

MP

AZ

OZ

QZ

NZ

FZ

Mode: Address

Buses [a:0]

Data Buses

[w:0]

64x18 [5:0] [17:0]
128x9 [6:0] [8:0]
256x4 [7:0] [3:0]
512x2 [8:0] [1:0]

RAM M

ODULE FEATURES

MODE[1:0]
WA[a:0]
WD[w:0]

WE

WCLK

RAM Module

ASYNCRD

RA[a:0]

RD[w:0]

RE

RCLK

Rev B 7

QL5130 - QuickPCI

TM

The RAM modules are “dual-ported”, with
completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports
support asynchronous and synchronous operation,
while the WRITE ports support synchronous opera­tion. Each port has 18 data lines and 9 address lines,
allowing word lengths of up to 18 bits and address
spaces of up to 512 words. Depending on the mode
selected, however, some higher order data or address
lines may not be used.

The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera­tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYNCRD
input high).

Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 28 bits wide in the QL5130 device.

A similar technique can be used to create depths
greater than 512 words. In this case, address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer SELECT
signals.

JTAG Support

JTAG pins support IEEE standard 1149.1a to provide
boundary scan capability for the QL5130 device. Six
pins are dedicated to JTAG and programming func­tions on each QL5130 device, and are unavailable for
general design input and output signals. TDI, TDO,
TCK, TMS, and TRSTB are JTAG pins. A sixth pin,
STM, is used only for programming.

Development Tools

Software support for the QL5130 device is available
through the QuickWorks

“

development package. This
turnkey PC-based QuickWorks package, shown in Fig­ure 6, provides a complete ESP software solution with
design entry, logic synthesis, place and route, and sim­ulation. QuickWorks includes VHDL, Verilog, sche­matic, and mixed-mode entry with fast and efficient
logic synthesis provided by the integrated Synplicity

Synplify Lite‘ tool, specially tuned to take advantage of
the QL5130 architecture. QuickWorks also provides
functional and timing simulation for guaranteed timing
and source-level debugging.

The UNIX-based QuickTool s ‘ and PC-based Quick­Work s - Lite‘ packages are a subset of QuickWorks and
provide a solution for designers who use schematic­only design flow third-party tools for design entry, syn­thesis, or simulation. QuickTools and QuickWorks-
Lite read EDIF netlists and provide support for all
QuickLogic devices. QuickTo o ls and QuickWorks-Li te
also support a wide range of third-party modeling and
simulation tools. In addition, the PC-based package
combines all the features of QuickWor ks-Lite with the
SCS schematic capture environment, providing a low­cost design entry and compilation solution.

FIGURE 6. QuickWorks Tool Suite

JTAG S

UPPORT

D

EVELOPMENT TOOLS

Schematic

Schematic

Turbo

HDL Editor

Third Party

Design

Entry

& Synthesis

Third Party

Simulation

VHDL/

VHDL/

Verilog

Verilog

SCS

Tools

Silos III

Simulator

SpDE

Mixed-Mode Design

Mixed-Mode Design

Synplify-

HDL

Synthesi

Quick

Works

Design Software

VeriBest

8 Rev B

QL5130 - QuickPCI

TM

QL5130 External Device Pins

The QL5130 Device Pins are indicated in the table below. These are pins on the device, some of which connect

to the PCI bus, and others that are programmable as user IO.

* See QuickNote 65 on the QuickLogic web site for

information on RAM initialization.

QL5130 E

XTERNAL DEVICE PINS

Type Description

IN

Input. A standard input-only
signal

OUT

Totem pole output. A standard
active output driver

T/S

Tri-state. A bi-directional, tri­state input/output pin

S/T/S

Sustained Tri-state. An active
low tri-state signal driven by
one PCI agent at a time. It
must be driven high for at least
one clock before being dis­abled (set to Hi-Z). A pull-up
needs to be provided by the
PCI system central resource to
sustain the inactive state once
the active driver has released
the signal.

O/D

Open Drain. Allows multiple
devices to share this pin as a
wired-or.

Pin/Bus

Name

Type

Function

VCC

IN

Supply pin. Tie to 3.3V supply.

VCCIO

IN

Supply pin for I/O. Set to 3.3V for

3.3V I/O, 5V for 5.0V compliant I/O

GND

IN

Ground pin. Tie to GND on the PCB.

I/O

T/S

Programmable Input/Output/Tri­State/Bi-directional Pin.

GLCK/I

IN

Programmable Global Network or
Input-only pin. Tie to VCC or GND if
unused.

ACLK/I

IN

Programmable Array Network or Input­only pin. Tie to VCC or GND if
unused.

TDI/
RSI*

IN

JTAG Data In/Ram Init. Serial Data In.
Tie to VCC if unused. Connect to
Serial EPROM data for RAM init.

TDO/
RCO*

OUT

JTAG Data Out/Ram Init Clock.
Leave unconnected if unused. Connect
to Serial EPROM clock for RAM init.

TCK

IN

JTAG Clock. Tie to GND if unused.

TMS

IN

JTAG Test Mode Select. Tie to VCC if
unused.

TRSTB/
RRO*

IN

JTAG Reset/RAM Init. Reset Out. Tie
to GND if unused. Connect to Serial
EPROM reset for RAM init.

STM

IN

QuickLogic Reserved pin. Tie to GND
on the PCB.

Rev B 9

QL5130 - QuickPCI

TM

External Device Pins

E

XTERNAL DEVICE PINS

Pin/Bus Name

Type

Function

AD[31:0] T/S PCI Address and Data: 32 bit multiplexed address/data

bus.

CBEN[3:0] T/S PCI Bus Command and Byte Enables: Multiplexed bus

which contains byte enables for AD[31:0] or the Bus
Command during the address phase of a PCI transac­tion.

PAR T /S PCI Parity: Even Parity across AD[31:0] and C/

BEN[3:0] busses. Driven one clock after address or
data phases. Master drives PAR on address cycles and
PCI writes. The Target drives PAR on PCI reads.

FRAMEN S/T/S PCI Cycle Frame: Driven active by current PCI Master

during a PCI transaction. Driven low to indicate the
address cycle, driven high at the end of the transaction.

DEVSELN S/T/S PCI Device Select. Driven by a Target that has decoded

a valid base address.

CLK IN PCI System Clock Input.

RSTN IN PCI System Reset Input

PERRN S/T/S PCI Data Parity Error. Driven active by the initiator or

target two clock cycles after a data parity error is
detected on the AD and C/BEN busses.

SERRN O/D PCI System Error: Driven active when an address cycle

parity error, data parity error during a special cycle, or
other catastrophic error is detected.

IDSEL IN PCI Initialization Device Select. Use to select a specific

PCI Agent during System Initialization.

IRDYN S/T/S PCI Initiator Ready. Indicates the Initiator’s ability to

complete a read or write transaction. Data transfer
occurs only on clock cycles where both IRDYN and
TRDYN are active.

TRDYN S/T/S PCI Target Ready. Indicates the Target’s ability to com-

plete a read or write transaction. Data transfer occurs
only on clock cycles where both IRDYN and TRDYN
are active.

STOPN S/T/S PCI Stop. Used by a PCI Target to end a burst transac-

tion.

10 Rev B

QL5130 - QuickPCI

TM

FIGURE 7. 144-pin TQFP

FIGURE 8. 208-pin PQFP

FIGURE 9. 256-pin PBGA

QL5130-33APF144C

QuickPCI

PIN #73

PIN #1

PIN #37

PIN #109

QL5130-33APQ208C

QuickPCI

PIN #1

PIN # 53

PIN # 105

PIN #157

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C

E

D

F
G
H

K

J

L
M
N

R

P

T
U
V

Y

W

Bottom View

PIN A1
CORNER

Rev B 11

QL5130 - QuickPCI

TM

QL5130 - 144 TQFP Pinout

PF144 Function PF144 Function PF144 Function PF144 Function

1 I/O 37 AD[21] 73 AD[4] 109

TCK

2I/O38

TDI/RSI

74 AD[3] 110

STM

3 I/O 39 AD[20] 75 AD[2] 111 I/O
4 I/O 40 AD[19] 76 AD[1] 112 I/O
5 I/O 41 AD[18] 77 AD[0] 113 I/O
6I/O42

VCC

78 I/O 114

VCC

7

VCC

43 AD[17] 79

VCC

115 I/O
8 I/O 44 AD[16] 80 I/O 116 I/O
9 I/O 45 CBEN[2] 81 I/O 117 I/O

10 I/O 46 FRAMEN 82 I/O 118 I/O
11 I/O 47 IRDYN 83 I/O 119 I/O
12 I/O 48 TRDYN 84 I/O 120 I/O
13 I/O 49 DEVSELN 85 I/O 121 I/O
14 I/O 50

GND

86 I/O 122

GND

15

GND

51 STOPN 87

GND

123 I/O

16 I/O 52 PERRN 88 I/O 124 I/O
17 GCLK/I 53 SERRN 89 GCLK/I 125 I/O
18 ACLK/I 54

GND

90

ACLK/I

126

GND

19

VCC

55 PAR 91

VCC

127 I/O

20 RSTN 56 CBEN[1] 92

GCLK/I

128 I/O

21 CLK 57 AD[15] 93 GCLK/I 129 I/O
22

VCC

58

VCCIO

94

VCC

130

VCCIO

23 I/O 59 AD[14] 95 I/O 131 I/O
24 AD[31] 60 AD[13] 96 I/O 132 I/O
25 AD[30] 61 AD[12] 97 I/O 133 I/O
26 AD[29] 62 AD[11] 98 I/O 134 I/O
27 AD[28] 63 AD[10] 99 I/O 135 I/O
28 AD[27] 64 AD[9] 100 I/O 136 I/O
29 AD[26] 65 AD[8] 101 I/O 137 I/O
30

GND

66

GND

102

GND

138

GND

31 AD[25] 67 CBEN[0] 103 I/O 139 I/O
32 AD[24] 68 AD[7] 104 I/O 140 I/O
33 CBEN[3] 69 AD[6] 105 I/O 141 I/O
34 IDSEL 70 AD[5] 106 I/O 142 I/O
35 AD[23] 71

TRSTB/RRO

107 I/O 143

TDO/RCO

36 AD[22] 72

TMS

108 I/O 144 I/O

QL5130 - 144 TQFP P

INOUT

12 Rev B

QL5130 - QuickPCI

TM

QL5130 - 208 PQFP Pinout

QL5130 - 208 PQFP P

INOUT

PQ208 Function PQ20 Function PQ208

Function

PQ208 Function PQ208 Function

1 I/O 43 GND 85 AD[3] 127 GND 169 I/O
2 I/O 44 IDSEL 86 AD[2] 128 I/O 170 I/O
3 I/O 45 AD[23] 87 AD[1] 129 GCLK/I 171 I/O
4 I/O 46 AD[22] 88 AD[0] 130 ACLK/I 172 I/O
5 I/O 47 AD[21] 89 I/O 131 VCC 173 I/O
6 I/O 48 AD[20] 90 I/O 132 GCLK/I 174 I/O
7 I/O 49 AD[19] 91 I/O 133 GCLK/I 175 I/O
8 I/O 50 AD[18] 92 I/O 134 VCC 176 I/O
9 I/O 51 AD[17] 93 I/O 135 I/O 177 GND
10 VCC 52 AD[16] 94 I/O 136 I/O 178 I/O
11 I/O 53 CBEN[2] 95 GND 137 I/O 179 I/O
12 GND 54 TDI 96 I/O 138 I/O 180 I/O
13 I/O 55 FRAMEN 97 VCC 139 I/O 181 I/O
14 I/O 56 IRDYN 98 I/O 140 I/O 182 GND
15 I/O 57 TRDYN 99 I/O 141 I/O 183 I/O
16 I/O 58 DEVSELN 100 I/O 142 I/O 184 I/O
17 I/O 59 GND 101 I/O 143 I/O 185 I/O
18 I/O 60 STOPN 102 I/O 144 I/O 186 I/O
19 I/O 61 VCC 103 TRSTB 145 VCC 187 VCCIO
20 I/O 62 I/O 104 TMS 146 I/O 188 I/O
21 I/O 63 I/O 105 I/O 147 GND 189 I/O
22 I/O 64 PERRN 106 I/O 148 I/O 190 I/O
23 GND 65 I/O 107 I/O 149 I/O 191 I/O
24 I/O 66 SERRN 108 I/O 150 I/O 192 I/O
25 RSTN 67 PAR 109 I/O 151 I/O 193 I/O
26 ACLK/I 68 CBEN[1] 110 I/O 152 I/O 194 I/O
27 VCC 69 AD[15] 111 I/O 153 I/O 195 I/O
28 GCLK/I 70 AD[14] 112 I/O 154 I/O 196 I/O
29 CLK 71 AD[13] 113 I/O 155 I/O 197 I/O
30 VCC 72 AD[12] 114 VCC 156 I/O 198 I/O
31 I/O 73 GND 115 I/O 157 TCK 199 GND
32 I/O 74 AD[11] 116 GND 158 STM 200 I/O
33 AD[31] 75 AD[10] 117 I/O 159 I/O 201 VCC
34 AD[30] 76 AD[9] 118 I/O 160 I/O 202 I/O
35 AD[29] 77 AD[8] 119 I/O 161 I/O 203 I/O
36 AD[28] 78 GND 120 I/O 162 I/O 204 I/O
37 AD[27] 79 CBEN[0] 121 I/O 163 GND 205 I/O
38 AD[26] 80 AD[7] 122 I/O 164 I/O 206 I/O
39 AD[25] 81 AD[6] 123 I/O 165 VCC 207 TDO
40 AD[24] 82 AD[5] 124 I/O 166 I/O 208 I/O
41 VCC 83 VCCIO 125

I/O

167 I/O

42 CBEN[3] 84 AD[4] 126 I/O 168 I/O

Rev B 13

QL5130 - QuickPCI

TM

QL5130 - 256 PBGA Pinout

QL5130 - 256 PBGA P

INOUT

PB256 Function PB256 Function PB256 Function PB256

Function

PB256 Function PB256 Function

A1 GND C4 I/O E19 I/O L2 ACLK/I T17 I/O V20 I/O
A2 I/O C5 I/O E20 I/O L3 RSTN T18 I/O W1 I/O
A3 I /O C6 I /O F1 I/O L4 GCLK/I T19 NC W2 I/O
A4 I/O C7 I/O F2 I/O L17 VCC T20 I/O W3 TDI
A5 I/O C8 I/O F3 I/O L18 I/O U1 I/O W4 I/O
A6 I/O C9 VCCIO F4 VCC L19 I/O U2 I/O W5 AD[27]
A7 I/O C10 I/O F17 VCC L20 I/O U3 I/O W6 CBEN[3]
A8 I /O C11 I /O F18 NC M1 I/O U4 GND W7 AD[21]

A9 I /O C12 I /O F19 I /O M2 I/O U5 AD[ 26] W8 AD[20]
A10 I /O C13 I /O F20 I /O M3 I/O U6 VCC W9 CBEN[2]
A11 I/O C14 I/O G1 I/O M4 NC U7 AD[22] W10 DEVSELN
A12 I /O C15 I /O G2 NC M17 NC U8 GND W11 PERRN
A13 I /O C16 I /O G3 I/O M18 I/O U9 FRAMEN W12 CBEN[1]
A14 I /O C17 I/O G4 I/O M19 I/O U10 VCC W13 PAR
A15 I /O C18 I/O G17 I /O M20 I /O U11 I/O W14 AD[ 10]
A16 I /O C19 I/O G18 I /O N1 I /O U12 I/O W15 AD[9]
A17 I /O C20 I /O G19 NC N2 I/O U13 GND W16 AD[5]
A18 I/O D1 I/O G20 I/O N3 I/O U14 AD[11] W17 AD[1]
A19 TCK D2 I /O H1 I/O N4 GND U15 VCC W18 AD[0]
A20 I /O D3 I/ O H2 I /O N17 GND U16 AD[4] W19 I/O

B1 TDOD4GNDH3 I/ON18I/OU17GNDW20TRSTB

B2 I/O D5 I/O H4 GND N19 I/O U18 I/O Y1 I/O

B3 I/O D6VCCH17GNDN20I/OU19I/O Y2 NC

B4 I/O D7 I/O H18 I/O P1 I/O U20 I/O Y3 I/O

B5 I /O D8 GND H19 I/O P2 I/O V1 I/O Y4 AD[31]

B6 I/O D9 I/O H20 I/O P3 I/O V2 NC Y5 AD[29]

B7 I/O D10 I/O J1 I/O P4 I/O V3 I/O Y6 AD[25]

B8 I/O D11 VCC J2 I/O P17 I/O V4 AD[30] Y7 AD[23]

B9 I/O D12 I/O J3 NC P18 I/O V5 AD[28] Y8 AD[19]
B10 I/O D13 GND J4 I/O P19 NC V6 AD[24] Y9 AD[17]
B11 I/O D14 I/O J17 NC P20 I/O V7 IDSEL Y10 IRDYN
B12 I/O D15 VCC J18 I/O R1 NC V8 AD[18] Y11 I/O
B13 I/O D16 I/O J19 I/O R2 I/O V9 AD[16] Y12 SERRN
B14 I/O D17 GND J20 GCLK / I R3 I/O V10 TRDYN Y13 AD[14]
B15 I/O D18 I/O K1 I/O R4 VCC V11 STOPN Y14 AD[12]
B16 I/O D19 I/O K2 I/O R17 VCC V12 VCCIO Y15 AD[8]
B17 NC D20 I/O K3 I/O R18 I/O V13 AD[15] Y16 AD[7]
B18 STM E1 NC K4 VCC R19 I/O V14 AD[13] Y17 AD[3]
B19 NC E2 I/O K17 GCLK/I R20 I/O V15 CBEN[0] Y18 I/O
B20 I/O E3 I/O K18 ACLK/I T1 NC V16 AD[6] Y19 I/O

C1 I /O E4 I/O K19 GCLK/I T2 I/O V17 AD[2] Y20 NC

C2 I/O E17 I/O K20 NC T3 I/O V18 I/O

C3 I /O E18 I/O L1 CLK T4 NC V19 TMS

14 Rev B

QL5130 - QuickPCI

TM

Absolute Maximum Ratings

Operating Range

DC Characteristics

DC Input Current........................... .....±20 mA

ESD Pad Protection .......................

.....±2000V

Storage Temperature .............. -65

°C to +150C

Lead Temperature .............................. ...300

°C

VCC Voltage ............ ............-0.5 to 4.6V

VCCIO Voltage......... ............-0.5 to 7.0V

Input Voltage ............-0.5 to VCCIO+0.5V

Latch-up Immunity .................

.....±200mA

Symbol Parameter Industrial Commercial Unit

Min Max Min Max

VCC Supply Voltage 3.0 3.6 3.0 3.6 V
VCCIO I/O Input Tolerance Voltage 3.0 5.5 3.0 5.25 V
TA Ambient Temperature -40 85 0 70

°C

K Delay Factor -A Speed Grade 0.43 0.90 0.46 0.88

Symbol Parameter Conditions Min Max Unit

VIH Input HIGH Voltage 0.5VCC VCCIO+0.5 V
VIL Input LOW Voltage -0.5 0.3VCC V
VOH Output HIGH Voltage IOH = -12 mA 2.4 V

IOH = -500 µA

0.9VCC V

VOL Output LOW Voltage IOL = 16 mA 0.45 V

IOL = 1.5 mA 0.1VCC V

II I or I/O Input Leakage Current VI = VCCIO or GND -10 10

µ

A

IOZ 3-State Output Leakage Current VI = VCCIO or GND -10 10

µ

A
CI Input Capacitance [1] 10 pF
IOS Output Short Circuit Current [2] VO = GND -15 -180 mA

VO = VCC 40 210 mA

ICC D.C. Supply Current [3] VI, VIO = VCCIO or GND 0.50 (typ

)

2mA

ICCIO D.C. Supply Current on VCCIO 0 100

µ

A

[1] Capacitance is sample tested only. Clock pins are 12 pF maximum.
[2] Only one output at a time. Duration should not exceed 30 seconds.
[3] For -A commercial grade device only. Maximum ICC is 3 mA for all industrial grade devices. For AC

conditions, contact QuickLogic Customer Engineering.

Rev B 15

QL5130 - QuickPCI

TM

AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the “Operating Range” section by the following numbers.)

Logic Cells

RAM Cell Synchronous Write Timing

Notes:

[4] Stated timing for worst case Propagatio n Delay ov er proces s va riatio n at VCC=3.3 V and TA=25°C. Multiply by

the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating
Range.

[5] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell

including typical net delays. W or st case delay values for specific paths should be determined from timing analy­sis of your particular design.

Symbol Parameter

Propagation Delays (ns)

Fanout [5]

12348

tPD Combinatorial Delay [6] 1.4 1.7 1.9 2.2 3.2
tSU Setup Time [6] 1.7 1.7 1.7 1.7 1.7
tH Hold Time 0.0 0.0 0.0 0.0 0.0
tCLK Clock to Q Delay 0.7 1.0 1.2 1.5 2.5
tCWHI Clock High Time 1.2 1 .2 1 .2 1.2 1.2
tCWLO Clock Low Time 1.2 1.2 1.2 1.2 1.2
tSET Set Delay 1.0 1.3 1.5 1.8 2.8
tRESET Reset Delay 0.8 1.1 1 .3 1.6 2.6
tSW Set Width 1.9 1.9 1.9 1.9 1.9
tRW Reset Width 1.8 1.8 1.8 1.8 1.8

Symbol Parameter

Propagation Delays (ns)

Fanout

12348

TSWA WA Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
THWA WA Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
TSWD WD Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
THWD WD Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
TSWE WE Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
THWE WE Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
TWCRD WCLK to RD (WA=RA) [4] 5.0 5.3 5.6 5.9 7.1

16 Rev B

QL5130 - QuickPCI

TM

RAM Cell Synchronous Read Timing

RAM Cell Asynchronous Read T iming

Input-Only Cells

Clock Cells

Notes:
[6] The array distributed networks consist of 40 half columns and the global distributed networks consist of

44 half columns, each driven by an indepen dent buf fer. The number of half columns used does not af fect
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11
loads per half column.

Symbol Parameter

Propagation Delays (ns)

Fanout

12348

TSRA RA Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0
THRA RA Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0
TSRE RE Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0
THRE RE Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0
TRCRD RCLK to RD [4] 4.0 4.3 4.6 4. 9 6.1

Symbol Parameter

Propagation Delays (ns)

Fanout

12348

RPDRD RA to RD [4

]

3.0

3.3 3.6 3.9 5.1

Symbol Parameter

Propagation Delays (ns)

Fanout [5]

123481224

TIN High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4
TINI High Drive Input, Inverting Delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5
TISU Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1
TIH Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
TlCLK Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6
TlRST Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5
TlESU Input Register Clock Enable Setup Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3
TlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

Symbol Parameter

Propagation Delays (ns)

Loads per Half Column [7]

123481011

tACK Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7
tGCKP Global Clock Pin Delay 0.7 0.7 0 .7 0.7 0.7 0.7 0.7
tGCKB Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3

Rev B 17

QL5130 - QuickPCI

TM

I/O Cell Input Delays

I/O Cell Output Delays

Notes:

[7] The following loads are used for tPXZ:

Symbol Parameter

Propagation Delays (ns)

Fanout [5]

1234810

tI/O Input Delay (bidirectional pad)

1.3 1.6 1.8 2.1 3.1 3.6

TISU Input Register Set-Up Time

3.1 3.1 3.1 3.1 3.1 3.1

TIH Input Register Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

TlOCLK I nput Register Clock To Q

0.7 1.0 1.2 1.5 2.5 3.0

TlORST Input Register Reset Delay

0.6 0.9 1.1 1.4 2.4 2.9

TlESU Input Register clock Enable Set-Up Time

2.3 2.3 2.3 2.3 2.3 2.3

TlEH Input Register Clock Enable Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

Symbol Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

30 50 75 100 150

TOUTLH Output Delay Low to High

2.1 2.5 3.1 3.6 4.7

TOUTHL Output Delay High to Low

2.2 2.6 3.2 3.7 4.8

TPZH Output Delay Tri-state to High

1.2 1.7 2.2 2.8 3.9

TPZL Output Delay Tri-stat e to Low

1.6 2.0 2.6 3.1 4.2

TPHZ Output Delay High to Tri-State [8]

2.0

TPLZ Output Delay Low to Tri-State [8]

1.2

5 pF

1KΩ

5 pF

1KΩ

tPHZ

tPLZ